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cslr_dmm.h

cslr_dmm.h 122 KB
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
  1. /********************************************************************
    2. 

  2.  * Copyright (C) 2013-2014 Texas Instruments Incorporated.
    3. 

  3.  *
    4. 

  4.  *  Redistribution and use in source and binary forms, with or without
    5. 

  5.  *  modification, are permitted provided that the following conditions
    6. 

  6.  *  are met:
    7. 

  7.  *
    8. 

  8.  *    Redistributions of source code must retain the above copyright
    9. 

  9.  *    notice, this list of conditions and the following disclaimer.
    10. 

  10.  *
    11. 

  11.  *    Redistributions in binary form must reproduce the above copyright
    12. 

  12.  *    notice, this list of conditions and the following disclaimer in the
    13. 

  13.  *    documentation and/or other materials provided with the
    14. 

  14.  *    distribution.
    15. 

  15.  *
    16. 

  16.  *    Neither the name of Texas Instruments Incorporated nor the names of
    17. 

  17.  *    its contributors may be used to endorse or promote products derived
    18. 

  18.  *    from this software without specific prior written permission.
    19. 

  19.  *
    20. 

  20.  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    21. 

  21.  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    22. 

  22.  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    23. 

  23.  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    24. 

  24.  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    25. 

  25.  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    26. 

  26.  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    27. 

  27.  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    28. 

  28.  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    29. 

  29.  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    30. 

  30.  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31. 

  31.  *
    32. 

  32. */
    33. 

  33. #ifndef CSLR_DMM_H_
    34. 

  34. #define CSLR_DMM_H_
    35. 

  35. 

  36. #ifdef __cplusplus
    37. 

  37. extern "C"
    38. 

  38. {
    39. 

  39. #endif
    40. 

  40. #include <ti/csl/cslr.h>
    41. 

  41. #include <ti/csl/tistdtypes.h>
    42. 

  42. 

  43. 

  44. /**************************************************************************
    45. 

  45. * Register Overlay Structure for PAT_AREAS
    46. 

  46. **************************************************************************/
    47. 

  47. typedef struct {
    48. 

  48.     volatile Uint32 PAT_DESCR;
    49. 

  49.     volatile Uint32 PAT_AREA;
    50. 

  50.     volatile Uint32 PAT_CTRL;
    51. 

  51.     volatile Uint32 PAT_DATA;
    52. 

  52. } CSL_DmmPat_areasRegs;
    53. 

  53. 

  54. 

  55. /**************************************************************************
    56. 

  56. * Register Overlay Structure for Trailer
    57. 

  57. **************************************************************************/
    58. 

  58. typedef struct {
    59. 

  59.     volatile Uint32 PEG_HWINFO;
    60. 

  60.     volatile Uint8  RSVD0[20];
    61. 

  61.     volatile Uint32 PEG_PRIO[8];
    62. 

  62.     volatile Uint32 PEG_PRIO_PAT;
    63. 

  63. } CSL_DmmTrailerRegs;
    64. 

  64. 

  65. 

  66. /**************************************************************************
    67. 

  67. * Register Overlay Structure
    68. 

  68. **************************************************************************/
    69. 

  69. typedef struct {
    70. 

  70.     volatile Uint32 REVISION;
    71. 

  71.     volatile Uint32 HWINFO;
    72. 

  72.     volatile Uint32 LISA_HWINFO;
    73. 

  73.     volatile Uint8  RSVD1[4];
    74. 

  74.     volatile Uint32 SYSCONFIG;
    75. 

  75.     volatile Uint8  RSVD2[8];
    76. 

  76.     volatile Uint32 LISA_LOCK;
    77. 

  77.     volatile Uint32 EMERGENCY;
    78. 

  78.     volatile Uint8  RSVD3[28];
    79. 

  79.     volatile Uint32 LISA_MAP[4];
    80. 

  80.     volatile Uint8  RSVD4[440];
    81. 

  81.     volatile Uint32 TILER_HWINFO;
    82. 

  82.     volatile Uint8  RSVD5[20];
    83. 

  83.     volatile Uint32 TILER_OR[2];
    84. 

  84.     volatile Uint8  RSVD6[480];
    85. 

  85.     volatile Uint32 PAT_HWINFO;
    86. 

  86.     volatile Uint32 PAT_GEOMETRY;
    87. 

  87.     volatile Uint32 PAT_CONFIG;
    88. 

  88.     volatile Uint8  RSVD7[12];
    89. 

  89.     volatile Uint32 PAT_VIEW[2];
    90. 

  90.     volatile Uint8  RSVD8[24];
    91. 

  91.     volatile Uint32 PAT_VIEW_MAP[4];
    92. 

  92.     volatile Uint8  RSVD9[16];
    93. 

  93.     volatile Uint32 PAT_VIEW_MAP_BASE;
    94. 

  94.     volatile Uint8  RSVD10[20];
    95. 

  95.     volatile Uint32 PAT_IRQ_EOI;
    96. 

  96.     volatile Uint8  RSVD11[4];
    97. 

  97.     volatile Uint32 PAT_IRQSTS_RAW;
    98. 

  98.     volatile Uint8  RSVD12[12];
    99. 

  99.     volatile Uint32 PAT_IRQSTS;
    100. 

  100.     volatile Uint8  RSVD13[12];
    101. 

  101.     volatile Uint32 PAT_IRQEN_SET;
    102. 

  102.     volatile Uint8  RSVD14[12];
    103. 

  103.     volatile Uint32 PAT_IRQEN_CLR;
    104. 

  104.     volatile Uint8  RSVD15[12];
    105. 

  105.     volatile Uint32 PAT_STS[4];
    106. 

  106.     volatile Uint8  RSVD16[48];
    107. 

  107.     CSL_DmmPat_areasRegs	PAT_AREAS[4];
    108. 

  108.     volatile Uint8  RSVD17[200];
    109. 

  109.     CSL_DmmTrailerRegs	TRAILER;
    110. 

  110. } CSL_DmmRegs;
    111. 

  111. 

  112. 

  113. 

  114. 

  115. /**************************************************************************
    116. 

  116. * Register Macros
    117. 

  117. **************************************************************************/
    118. 

  118. 

  119. /* DMM Revision Identifier (X.Y.R) */
    120. 

  120. #define CSL_DMM_REVISION                                        (0x0U)
    121. 

  121. 

  122. /* DMM hardware configuration */
    123. 

  123. #define CSL_DMM_HWINFO                                          (0x4U)
    124. 

  124. 

  125. /* DMM hardware configuration for LISA */
    126. 

  126. #define CSL_DMM_LISA_HWINFO                                     (0x8U)
    127. 

  127. 

  128. /* DMM clock management configuration */
    129. 

  129. #define CSL_DMM_SYSCONFIG                                       (0x10U)
    130. 

  130. 

  131. /* DMM memory mapping lock */
    132. 

  132. #define CSL_DMM_LISA_LOCK                                       (0x1CU)
    133. 

  133. 

  134. /* EMERGENCY */
    135. 

  135. #define CSL_DMM_EMERGENCY                                       (0x20U)
    136. 

  136. 

  137. /* DMM memory mapping n = 0 for the first memory mapping register, n = 1 for
    138. 

  138.  * the second memory mapping register... */
    139. 

  139. #define CSL_DMM_LISA_MAP(i)                                     (0x40U + ((i) * (0x4U)))
    140. 

  140. 

  141. /* DMM hardware configuration for TILER */
    142. 

  142. #define CSL_DMM_TILER_HWINFO                                    (0x208U)
    143. 

  143. 

  144. /* DMM TILER orientation. n = 0 for the first orientation register, n = 1 for
    145. 

  145.  * the second orientation register... */
    146. 

  146. #define CSL_DMM_TILER_OR(i)                                     (0x220U + ((i) * (0x4U)))
    147. 

  147. 

  148. /* DMM hardware configuration for PAT */
    149. 

  149. #define CSL_DMM_PAT_HWINFO                                      (0x408U)
    150. 

  150. 

  151. /* PAT geometry-related settings */
    152. 

  152. #define CSL_DMM_PAT_GEOMETRY                                    (0x40CU)
    153. 

  153. 

  154. /* This is the PAT configuration register aimed at defining the major PAT
    155. 

  155.  * configuration of each refill engine. */
    156. 

  156. #define CSL_DMM_PAT_CONFIG                                      (0x410U)
    157. 

  157. 

  158. /* DMM PAT view register n = 0 for the first view register, n = 1 for the
    159. 

  159.  * second view register... */
    160. 

  160. #define CSL_DMM_PAT_VIEW(i)                                     (0x420U + ((i) * (0x4U)))
    161. 

  161. 

  162. /* PAT view mapping register n = 0 for the first view mapping register, n = 1
    163. 

  163.  * for the second view mapping register... */
    164. 

  164. #define CSL_DMM_PAT_VIEW_MAP(i)                                 (0x440U + ((i) * (0x4U)))
    165. 

  165. 

  166. /* Base address of all view mappings */
    167. 

  167. #define CSL_DMM_PAT_VIEW_MAP_BASE                               (0x460U)
    168. 

  168. 

  169. /* PAT end of interrupt */
    170. 

  170. #define CSL_DMM_PAT_IRQ_EOI                                     (0x478U)
    171. 

  171. 

  172. /* Per-event raw interrupt status vector. Raw status is set even if the
    173. 

  173.  * related event is not enabled. Write 1 to set the (raw) status, mostly for
    174. 

  174.  * debug. n = 0 for the first interrupt status raw register, n = 1 for the
    175. 

  175.  * second interrupt status raw register... */
    176. 

  176. #define CSL_DMM_PAT_IRQSTS_RAW                                  (0x480U)
    177. 

  177. 

  178. /* Per-event "enabled" interrupt status vector. Enabled status isn't set
    179. 

  179.  * unless the event is enabled. Write 1 to clear the status after interrupt
    180. 

  180.  * has been serviced (raw status gets cleared, i.e. even if not enabled). n =
    181. 

  181.  * 0 for the first interrupt status register, n = 1 for the second interrupt
    182. 

  182.  * status register... */
    183. 

  183. #define CSL_DMM_PAT_IRQSTS                                      (0x490U)
    184. 

  184. 

  185. /* Per-event interrupt enable bit vector. Write 1 to set (enable interrupt).
    186. 

  186.  * Readout equal to corresponding _CLR register. n = 0 for the first interrupt
    187. 

  187.  * enable set register, n = 1 for the second interrupt enable set register... */
    188. 

  188. #define CSL_DMM_PAT_IRQEN_SET                                   (0x4A0U)
    189. 

  189. 

  190. /* Per-event interrupt enable bit vector. Write 1 to clear (disable
    191. 

  191.  * interrupt). Readout equal to corresponding _SET register. n = 0 for the
    192. 

  192.  * first interrupt enable clear register, n = 1 for the second interrupt
    193. 

  193.  * enable clear register... */
    194. 

  194. #define CSL_DMM_PAT_IRQEN_CLR                                   (0x4B0U)
    195. 

  195. 

  196. /* Status register for each refill engine n = 0 for the first engine status
    197. 

  197.  * register, n = 1 for the second engine status register... */
    198. 

  198. #define CSL_DMM_PAT_STS(i)                                      (0x4C0U + ((i) * (0x4U)))
    199. 

  199. 

  200. /* Physical address of the next table refill descriptor n = 0 for the
    201. 

  201.  * descriptor register of the first engine, n = 1 for the descriptor register
    202. 

  202.  * of the second engine... Writing to this register aborts the current ongoing
    203. 

  203.  * area reload and resets the corresponding DMM_PAT_AREA__x, DMM_PAT_CTRL__x
    204. 

  204.  * and DMM_PAT_DATA__x registers */
    205. 

  205. #define CSL_DMM_PAT_DESCR(n)                                    (0x500U + ((n) * (0x10U)))
    206. 

  206. 

  207. /* Area definition for DMM physical address translator n = 0 for the area
    208. 

  208.  * register of the first engine, n = 1 for the area register of the second
    209. 

  209.  * engine... */
    210. 

  210. #define CSL_DMM_PAT_AREA(n)                                     (0x504U + ((n) * (0x10U)))
    211. 

  211. 

  212. /* DMM physical address translator control register n = 0 for the control
    213. 

  213.  * register of the first engine, n = 1 for the control register of the second
    214. 

  214.  * engine... */
    215. 

  215. #define CSL_DMM_PAT_CTRL(n)                                     (0x508U + ((n) * (0x10U)))
    216. 

  216. 

  217. /* Physical address of the current table refill entry data n = 0 for the data
    218. 

  218.  * register of the first engine, n = 1 for the data register of the second
    219. 

  219.  * engine... */
    220. 

  220. #define CSL_DMM_PAT_DATA(n)                                     (0x50CU + ((n) * (0x10U)))
    221. 

  221. 

  222. /* DMM hardware configuration for PEG */
    223. 

  223. #define CSL_DMM_PEG_HWINFO                                      (0x608U)
    224. 

  224. 

  225. /* DMM PEG Priority register n = 0 for the first priority register, n = 1 for
    226. 

  226.  * the second priority register... */
    227. 

  227. #define CSL_DMM_PEG_PRIO(i)                                     (0x620U + ((i) * (0x4U)))
    228. 

  228. 

  229. /* DMM PEG Priority register for the internal PAT engine. */
    230. 

  230. #define CSL_DMM_PEG_PRIO_PAT                                    (0x640U)
    231. 

  231. 

  232. 

  233. /**************************************************************************
    234. 

  234. * Field Definition Macros
    235. 

  235. **************************************************************************/
    236. 

  236. 

  237. /* REVISION */
    238. 

  238. 

  239. #define CSL_DMM_REVISION_Y_MINOR_MASK                           (0x0000003FU)
    240. 

  240. #define CSL_DMM_REVISION_Y_MINOR_SHIFT                          (0U)
    241. 

  241. #define CSL_DMM_REVISION_Y_MINOR_RESETVAL                       (0x00000009U)
    242. 

  242. #define CSL_DMM_REVISION_Y_MINOR_MAX                            (0x0000003fU)
    243. 

  243. 

  244. #define CSL_DMM_REVISION_CUSTOM_MASK                            (0x000000C0U)
    245. 

  245. #define CSL_DMM_REVISION_CUSTOM_SHIFT                           (6U)
    246. 

  246. #define CSL_DMM_REVISION_CUSTOM_RESETVAL                        (0x00000000U)
    247. 

  247. #define CSL_DMM_REVISION_CUSTOM_STD                             (0x00000000U)
    248. 

  248. 

  249. #define CSL_DMM_REVISION_X_MAJOR_MASK                           (0x00000700U)
    250. 

  250. #define CSL_DMM_REVISION_X_MAJOR_SHIFT                          (8U)
    251. 

  251. #define CSL_DMM_REVISION_X_MAJOR_RESETVAL                       (0x00000000U)
    252. 

  252. #define CSL_DMM_REVISION_X_MAJOR_MAX                            (0x00000007U)
    253. 

  253. 

  254. #define CSL_DMM_REVISION_R_RTL_MASK                             (0x0000F800U)
    255. 

  255. #define CSL_DMM_REVISION_R_RTL_SHIFT                            (11U)
    256. 

  256. #define CSL_DMM_REVISION_R_RTL_RESETVAL                         (0x00000000U)
    257. 

  257. #define CSL_DMM_REVISION_R_RTL_MAX                              (0x0000001fU)
    258. 

  258. 

  259. #define CSL_DMM_REVISION_FUNC_MASK                              (0x0FFF0000U)
    260. 

  260. #define CSL_DMM_REVISION_FUNC_SHIFT                             (16U)
    261. 

  261. #define CSL_DMM_REVISION_FUNC_RESETVAL                          (0x00000000U)
    262. 

  262. #define CSL_DMM_REVISION_FUNC_MAX                               (0x00000fffU)
    263. 

  263. 

  264. #define CSL_DMM_REVISION_SCHEME_MASK                            (0xC0000000U)
    265. 

  265. #define CSL_DMM_REVISION_SCHEME_SHIFT                           (30U)
    266. 

  266. #define CSL_DMM_REVISION_SCHEME_RESETVAL                        (0x00000001U)
    267. 

  267. #define CSL_DMM_REVISION_SCHEME_H08                             (0x00000001U)
    268. 

  268. 

  269. #define CSL_DMM_REVISION_RESETVAL                               (0x40000009U)
    270. 

  270. 

  271. /* HWINFO */
    272. 

  272. 

  273. #define CSL_DMM_HWINFO_TILER_CNT_MASK                           (0x0000000FU)
    274. 

  274. #define CSL_DMM_HWINFO_TILER_CNT_SHIFT                          (0U)
    275. 

  275. #define CSL_DMM_HWINFO_TILER_CNT_RESETVAL                       (0x00000002U)
    276. 

  276. #define CSL_DMM_HWINFO_TILER_CNT_MAX                            (0x0000000fU)
    277. 

  277. 

  278. #define CSL_DMM_HWINFO_ELLA_CNT_MASK                            (0x00000F00U)
    279. 

  279. #define CSL_DMM_HWINFO_ELLA_CNT_SHIFT                           (8U)
    280. 

  280. #define CSL_DMM_HWINFO_ELLA_CNT_RESETVAL                        (0x00000000U)
    281. 

  281. #define CSL_DMM_HWINFO_ELLA_CNT_MAX                             (0x0000000fU)
    282. 

  282. 

  283. #define CSL_DMM_HWINFO_ROBIN_CNT_MASK                           (0x000F0000U)
    284. 

  284. #define CSL_DMM_HWINFO_ROBIN_CNT_SHIFT                          (16U)
    285. 

  285. #define CSL_DMM_HWINFO_ROBIN_CNT_RESETVAL                       (0x00000002U)
    286. 

  286. #define CSL_DMM_HWINFO_ROBIN_CNT_MAX                            (0x0000000fU)
    287. 

  287. 

  288. #define CSL_DMM_HWINFO_RESETVAL                                 (0x00020002U)
    289. 

  289. 

  290. /* LISA_HWINFO */
    291. 

  291. 

  292. #define CSL_DMM_LISA_HWINFO_SECTION_CNT_MASK                    (0x0000001FU)
    293. 

  293. #define CSL_DMM_LISA_HWINFO_SECTION_CNT_SHIFT                   (0U)
    294. 

  294. #define CSL_DMM_LISA_HWINFO_SECTION_CNT_RESETVAL                (0x00000004U)
    295. 

  295. #define CSL_DMM_LISA_HWINFO_SECTION_CNT_MAX                     (0x0000001fU)
    296. 

  296. 

  297. #define CSL_DMM_LISA_HWINFO_SDRC_CNT_MASK                       (0x00000F00U)
    298. 

  298. #define CSL_DMM_LISA_HWINFO_SDRC_CNT_SHIFT                      (8U)
    299. 

  299. #define CSL_DMM_LISA_HWINFO_SDRC_CNT_RESETVAL                   (0x00000002U)
    300. 

  300. #define CSL_DMM_LISA_HWINFO_SDRC_CNT_MAX                        (0x0000000fU)
    301. 

  301. 

  302. #define CSL_DMM_LISA_HWINFO_RESETVAL                            (0x00000204U)
    303. 

  303. 

  304. /* SYSCONFIG */
    305. 

  305. 

  306. #define CSL_DMM_SYSCONFIG_IDLE_MODE_MASK                        (0x0000000CU)
    307. 

  307. #define CSL_DMM_SYSCONFIG_IDLE_MODE_SHIFT                       (2U)
    308. 

  308. #define CSL_DMM_SYSCONFIG_IDLE_MODE_RESETVAL                    (0x00000002U)
    309. 

  309. #define CSL_DMM_SYSCONFIG_IDLE_MODE_SMART                       (0x00000002U)
    310. 

  310. #define CSL_DMM_SYSCONFIG_IDLE_MODE_FORCE_IDLE                  (0x00000000U)
    311. 

  311. #define CSL_DMM_SYSCONFIG_IDLE_MODE_NO_IDLE                     (0x00000001U)
    312. 

  312. #define CSL_DMM_SYSCONFIG_IDLE_MODE_RESERVED3                   (0x00000003U)
    313. 

  313. 

  314. #define CSL_DMM_SYSCONFIG_RESETVAL                              (0x00000008U)
    315. 

  315. 

  316. /* LISA_LOCK */
    317. 

  317. 

  318. #define CSL_DMM_LISA_LOCK_LOCK_MASK                             (0x00000001U)
    319. 

  319. #define CSL_DMM_LISA_LOCK_LOCK_SHIFT                            (0U)
    320. 

  320. #define CSL_DMM_LISA_LOCK_LOCK_RESETVAL                         (0x00000000U)
    321. 

  321. #define CSL_DMM_LISA_LOCK_LOCK_UNLOCKED                         (0x00000000U)
    322. 

  322. #define CSL_DMM_LISA_LOCK_LOCK_LOCKED                           (0x00000001U)
    323. 

  323. #define CSL_DMM_LISA_LOCK_LOCK_LOCKING                          (0x00000001U)
    324. 

  324. #define CSL_DMM_LISA_LOCK_LOCK_KEEP                             (0x00000000U)
    325. 

  325. 

  326. #define CSL_DMM_LISA_LOCK_RESETVAL                              (0x00000000U)
    327. 

  327. 

  328. /* EMERGENCY */
    329. 

  329. 

  330. #define CSL_DMM_EMERGENCY_EN_MASK                               (0x00000001U)
    331. 

  331. #define CSL_DMM_EMERGENCY_EN_SHIFT                              (0U)
    332. 

  332. #define CSL_DMM_EMERGENCY_EN_RESETVAL                           (0x00000000U)
    333. 

  333. #define CSL_DMM_EMERGENCY_EN_MAX                                (0x00000001U)
    334. 

  334. 

  335. #define CSL_DMM_EMERGENCY_WEIGHT_MASK                           (0x001F0000U)
    336. 

  336. #define CSL_DMM_EMERGENCY_WEIGHT_SHIFT                          (16U)
    337. 

  337. #define CSL_DMM_EMERGENCY_WEIGHT_RESETVAL                       (0x00000004U)
    338. 

  338. #define CSL_DMM_EMERGENCY_WEIGHT_MAX                            (0x0000001fU)
    339. 

  339. 

  340. #define CSL_DMM_EMERGENCY_RESETVAL                              (0x00040000U)
    341. 

  341. 

  342. /* LISA_MAP */
    343. 

  343. 

  344. #define CSL_DMM_LISA_MAP_SDRC_ADDR_MASK                         (0x000000FFU)
    345. 

  345. #define CSL_DMM_LISA_MAP_SDRC_ADDR_SHIFT                        (0U)
    346. 

  346. #define CSL_DMM_LISA_MAP_SDRC_ADDR_RESETVAL                     (0x00000000U)
    347. 

  347. #define CSL_DMM_LISA_MAP_SDRC_ADDR_MAX                          (0x000000ffU)
    348. 

  348. 

  349. #define CSL_DMM_LISA_MAP_SDRC_ADDRSPC_MASK                      (0x00030000U)
    350. 

  350. #define CSL_DMM_LISA_MAP_SDRC_ADDRSPC_SHIFT                     (16U)
    351. 

  351. #define CSL_DMM_LISA_MAP_SDRC_ADDRSPC_RESETVAL                  (0x00000000U)
    352. 

  352. #define CSL_DMM_LISA_MAP_SDRC_ADDRSPC_MAX                       (0x00000003U)
    353. 

  353. 

  354. #define CSL_DMM_LISA_MAP_SDRC_MAP_MASK                          (0x00000300U)
    355. 

  355. #define CSL_DMM_LISA_MAP_SDRC_MAP_SHIFT                         (8U)
    356. 

  356. #define CSL_DMM_LISA_MAP_SDRC_MAP_RESETVAL                      (0x00000000U)
    357. 

  357. #define CSL_DMM_LISA_MAP_SDRC_MAP_MAX                           (0x00000003U)
    358. 

  358. 

  359. #define CSL_DMM_LISA_MAP_SDRC_INTL_MASK                         (0x000C0000U)
    360. 

  360. #define CSL_DMM_LISA_MAP_SDRC_INTL_SHIFT                        (18U)
    361. 

  361. #define CSL_DMM_LISA_MAP_SDRC_INTL_RESETVAL                     (0x00000000U)
    362. 

  362. #define CSL_DMM_LISA_MAP_SDRC_INTL_NONE                         (0x00000000U)
    363. 

  363. #define CSL_DMM_LISA_MAP_SDRC_INTL__128B                        (0x00000001U)
    364. 

  364. #define CSL_DMM_LISA_MAP_SDRC_INTL__256B                        (0x00000002U)
    365. 

  365. #define CSL_DMM_LISA_MAP_SDRC_INTL__512B                        (0x00000003U)
    366. 

  366. 

  367. #define CSL_DMM_LISA_MAP_SYS_SIZE_MASK                          (0x00700000U)
    368. 

  368. #define CSL_DMM_LISA_MAP_SYS_SIZE_SHIFT                         (20U)
    369. 

  369. #define CSL_DMM_LISA_MAP_SYS_SIZE_RESETVAL                      (0x00000000U)
    370. 

  370. #define CSL_DMM_LISA_MAP_SYS_SIZE__16MB                         (0x00000000U)
    371. 

  371. #define CSL_DMM_LISA_MAP_SYS_SIZE__32MB                         (0x00000001U)
    372. 

  372. #define CSL_DMM_LISA_MAP_SYS_SIZE__64MB                         (0x00000002U)
    373. 

  373. #define CSL_DMM_LISA_MAP_SYS_SIZE__128MB                        (0x00000003U)
    374. 

  374. #define CSL_DMM_LISA_MAP_SYS_SIZE__256MB                        (0x00000004U)
    375. 

  375. #define CSL_DMM_LISA_MAP_SYS_SIZE__512MB                        (0x00000005U)
    376. 

  376. #define CSL_DMM_LISA_MAP_SYS_SIZE__1GB                          (0x00000006U)
    377. 

  377. #define CSL_DMM_LISA_MAP_SYS_SIZE__2GB                          (0x00000007U)
    378. 

  378. 

  379. #define CSL_DMM_LISA_MAP_SYS_ADDR_MASK                          (0xFF000000U)
    380. 

  380. #define CSL_DMM_LISA_MAP_SYS_ADDR_SHIFT                         (24U)
    381. 

  381. #define CSL_DMM_LISA_MAP_SYS_ADDR_RESETVAL                      (0x00000000U)
    382. 

  382. #define CSL_DMM_LISA_MAP_SYS_ADDR_MAX                           (0x000000ffU)
    383. 

  383. 

  384. #define CSL_DMM_LISA_MAP_RESETVAL                               (0x00000000U)
    385. 

  385. 

  386. /* TILER_HWINFO */
    387. 

  387. 

  388. #define CSL_DMM_TILER_HWINFO_OR_CNT_MASK                        (0x0000007FU)
    389. 

  389. #define CSL_DMM_TILER_HWINFO_OR_CNT_SHIFT                       (0U)
    390. 

  390. #define CSL_DMM_TILER_HWINFO_OR_CNT_RESETVAL                    (0x00000010U)
    391. 

  391. #define CSL_DMM_TILER_HWINFO_OR_CNT_MAX                         (0x0000007fU)
    392. 

  392. 

  393. #define CSL_DMM_TILER_HWINFO_RESETVAL                           (0x00000010U)
    394. 

  394. 

  395. /* TILER_OR */
    396. 

  396. 

  397. #define CSL_DMM_TILER_OR_OR0_MASK                               (0x00000007U)
    398. 

  398. #define CSL_DMM_TILER_OR_OR0_SHIFT                              (0U)
    399. 

  399. #define CSL_DMM_TILER_OR_OR0_RESETVAL                           (0x00000000U)
    400. 

  400. #define CSL_DMM_TILER_OR_OR0_MAX                                (0x00000007U)
    401. 

  401. 

  402. #define CSL_DMM_TILER_OR_W0_MASK                                (0x00000008U)
    403. 

  403. #define CSL_DMM_TILER_OR_W0_SHIFT                               (3U)
    404. 

  404. #define CSL_DMM_TILER_OR_W0_RESETVAL                            (0x00000000U)
    405. 

  405. #define CSL_DMM_TILER_OR_W0_UPDATE                              (0x00000001U)
    406. 

  406. #define CSL_DMM_TILER_OR_W0_KEEP                                (0x00000000U)
    407. 

  407. 

  408. #define CSL_DMM_TILER_OR_OR1_MASK                               (0x00000070U)
    409. 

  409. #define CSL_DMM_TILER_OR_OR1_SHIFT                              (4U)
    410. 

  410. #define CSL_DMM_TILER_OR_OR1_RESETVAL                           (0x00000000U)
    411. 

  411. #define CSL_DMM_TILER_OR_OR1_MAX                                (0x00000007U)
    412. 

  412. 

  413. #define CSL_DMM_TILER_OR_W1_MASK                                (0x00000080U)
    414. 

  414. #define CSL_DMM_TILER_OR_W1_SHIFT                               (7U)
    415. 

  415. #define CSL_DMM_TILER_OR_W1_RESETVAL                            (0x00000000U)
    416. 

  416. #define CSL_DMM_TILER_OR_W1_UPDATE                              (0x00000001U)
    417. 

  417. #define CSL_DMM_TILER_OR_W1_KEEP                                (0x00000000U)
    418. 

  418. 

  419. #define CSL_DMM_TILER_OR_OR2_MASK                               (0x00000700U)
    420. 

  420. #define CSL_DMM_TILER_OR_OR2_SHIFT                              (8U)
    421. 

  421. #define CSL_DMM_TILER_OR_OR2_RESETVAL                           (0x00000000U)
    422. 

  422. #define CSL_DMM_TILER_OR_OR2_MAX                                (0x00000007U)
    423. 

  423. 

  424. #define CSL_DMM_TILER_OR_W2_MASK                                (0x00000800U)
    425. 

  425. #define CSL_DMM_TILER_OR_W2_SHIFT                               (11U)
    426. 

  426. #define CSL_DMM_TILER_OR_W2_RESETVAL                            (0x00000000U)
    427. 

  427. #define CSL_DMM_TILER_OR_W2_UPDATE                              (0x00000001U)
    428. 

  428. #define CSL_DMM_TILER_OR_W2_KEEP                                (0x00000000U)
    429. 

  429. 

  430. #define CSL_DMM_TILER_OR_OR3_MASK                               (0x00007000U)
    431. 

  431. #define CSL_DMM_TILER_OR_OR3_SHIFT                              (12U)
    432. 

  432. #define CSL_DMM_TILER_OR_OR3_RESETVAL                           (0x00000000U)
    433. 

  433. #define CSL_DMM_TILER_OR_OR3_MAX                                (0x00000007U)
    434. 

  434. 

  435. #define CSL_DMM_TILER_OR_W3_MASK                                (0x00008000U)
    436. 

  436. #define CSL_DMM_TILER_OR_W3_SHIFT                               (15U)
    437. 

  437. #define CSL_DMM_TILER_OR_W3_RESETVAL                            (0x00000000U)
    438. 

  438. #define CSL_DMM_TILER_OR_W3_UPDATE                              (0x00000001U)
    439. 

  439. #define CSL_DMM_TILER_OR_W3_KEEP                                (0x00000000U)
    440. 

  440. 

  441. #define CSL_DMM_TILER_OR_OR4_MASK                               (0x00070000U)
    442. 

  442. #define CSL_DMM_TILER_OR_OR4_SHIFT                              (16U)
    443. 

  443. #define CSL_DMM_TILER_OR_OR4_RESETVAL                           (0x00000000U)
    444. 

  444. #define CSL_DMM_TILER_OR_OR4_MAX                                (0x00000007U)
    445. 

  445. 

  446. #define CSL_DMM_TILER_OR_W4_MASK                                (0x00080000U)
    447. 

  447. #define CSL_DMM_TILER_OR_W4_SHIFT                               (19U)
    448. 

  448. #define CSL_DMM_TILER_OR_W4_RESETVAL                            (0x00000000U)
    449. 

  449. #define CSL_DMM_TILER_OR_W4_UPDATE                              (0x00000001U)
    450. 

  450. #define CSL_DMM_TILER_OR_W4_KEEP                                (0x00000000U)
    451. 

  451. 

  452. #define CSL_DMM_TILER_OR_OR5_MASK                               (0x00700000U)
    453. 

  453. #define CSL_DMM_TILER_OR_OR5_SHIFT                              (20U)
    454. 

  454. #define CSL_DMM_TILER_OR_OR5_RESETVAL                           (0x00000000U)
    455. 

  455. #define CSL_DMM_TILER_OR_OR5_MAX                                (0x00000007U)
    456. 

  456. 

  457. #define CSL_DMM_TILER_OR_W5_MASK                                (0x00800000U)
    458. 

  458. #define CSL_DMM_TILER_OR_W5_SHIFT                               (23U)
    459. 

  459. #define CSL_DMM_TILER_OR_W5_RESETVAL                            (0x00000000U)
    460. 

  460. #define CSL_DMM_TILER_OR_W5_UPDATE                              (0x00000001U)
    461. 

  461. #define CSL_DMM_TILER_OR_W5_KEEP                                (0x00000000U)
    462. 

  462. 

  463. #define CSL_DMM_TILER_OR_OR6_MASK                               (0x07000000U)
    464. 

  464. #define CSL_DMM_TILER_OR_OR6_SHIFT                              (24U)
    465. 

  465. #define CSL_DMM_TILER_OR_OR6_RESETVAL                           (0x00000000U)
    466. 

  466. #define CSL_DMM_TILER_OR_OR6_MAX                                (0x00000007U)
    467. 

  467. 

  468. #define CSL_DMM_TILER_OR_W6_MASK                                (0x08000000U)
    469. 

  469. #define CSL_DMM_TILER_OR_W6_SHIFT                               (27U)
    470. 

  470. #define CSL_DMM_TILER_OR_W6_RESETVAL                            (0x00000000U)
    471. 

  471. #define CSL_DMM_TILER_OR_W6_UPDATE                              (0x00000001U)
    472. 

  472. #define CSL_DMM_TILER_OR_W6_KEEP                                (0x00000000U)
    473. 

  473. 

  474. #define CSL_DMM_TILER_OR_OR7_MASK                               (0x70000000U)
    475. 

  475. #define CSL_DMM_TILER_OR_OR7_SHIFT                              (28U)
    476. 

  476. #define CSL_DMM_TILER_OR_OR7_RESETVAL                           (0x00000000U)
    477. 

  477. #define CSL_DMM_TILER_OR_OR7_MAX                                (0x00000007U)
    478. 

  478. 

  479. #define CSL_DMM_TILER_OR_W7_MASK                                (0x80000000U)
    480. 

  480. #define CSL_DMM_TILER_OR_W7_SHIFT                               (31U)
    481. 

  481. #define CSL_DMM_TILER_OR_W7_RESETVAL                            (0x00000000U)
    482. 

  482. #define CSL_DMM_TILER_OR_W7_UPDATE                              (0x00000001U)
    483. 

  483. #define CSL_DMM_TILER_OR_W7_KEEP                                (0x00000000U)
    484. 

  484. 

  485. #define CSL_DMM_TILER_OR_RESETVAL                               (0x00000000U)
    486. 

  486. 

  487. /* PAT_HWINFO */
    488. 

  488. 

  489. #define CSL_DMM_PAT_HWINFO_VIEW_MAP_CNT_MASK                    (0x00000F00U)
    490. 

  490. #define CSL_DMM_PAT_HWINFO_VIEW_MAP_CNT_SHIFT                   (8U)
    491. 

  491. #define CSL_DMM_PAT_HWINFO_VIEW_MAP_CNT_RESETVAL                (0x00000004U)
    492. 

  492. #define CSL_DMM_PAT_HWINFO_VIEW_MAP_CNT_MAX                     (0x0000000fU)
    493. 

  493. 

  494. #define CSL_DMM_PAT_HWINFO_LUT_CNT_MASK                         (0x001F0000U)
    495. 

  495. #define CSL_DMM_PAT_HWINFO_LUT_CNT_SHIFT                        (16U)
    496. 

  496. #define CSL_DMM_PAT_HWINFO_LUT_CNT_RESETVAL                     (0x00000001U)
    497. 

  497. #define CSL_DMM_PAT_HWINFO_LUT_CNT_MAX                          (0x0000001fU)
    498. 

  498. 

  499. #define CSL_DMM_PAT_HWINFO_ENGINE_CNT_MASK                      (0x1F000000U)
    500. 

  500. #define CSL_DMM_PAT_HWINFO_ENGINE_CNT_SHIFT                     (24U)
    501. 

  501. #define CSL_DMM_PAT_HWINFO_ENGINE_CNT_RESETVAL                  (0x00000004U)
    502. 

  502. #define CSL_DMM_PAT_HWINFO_ENGINE_CNT_MAX                       (0x0000001fU)
    503. 

  503. 

  504. #define CSL_DMM_PAT_HWINFO_VIEW_CNT_MASK                        (0x0000007FU)
    505. 

  505. #define CSL_DMM_PAT_HWINFO_VIEW_CNT_SHIFT                       (0U)
    506. 

  506. #define CSL_DMM_PAT_HWINFO_VIEW_CNT_RESETVAL                    (0x00000010U)
    507. 

  507. #define CSL_DMM_PAT_HWINFO_VIEW_CNT_MAX                         (0x0000007fU)
    508. 

  508. 

  509. #define CSL_DMM_PAT_HWINFO_RESETVAL                             (0x04010410U)
    510. 

  510. 

  511. /* PAT_GEOMETRY */
    512. 

  512. 

  513. #define CSL_DMM_PAT_GEOMETRY_PAGE_SZ_MASK                       (0x0000001FU)
    514. 

  514. #define CSL_DMM_PAT_GEOMETRY_PAGE_SZ_SHIFT                      (0U)
    515. 

  515. #define CSL_DMM_PAT_GEOMETRY_PAGE_SZ_RESETVAL                   (0x00000001U)
    516. 

  516. #define CSL_DMM_PAT_GEOMETRY_PAGE_SZ_MAX                        (0x0000001fU)
    517. 

  517. 

  518. #define CSL_DMM_PAT_GEOMETRY_CONT_WDTH_MASK                     (0x000F0000U)
    519. 

  519. #define CSL_DMM_PAT_GEOMETRY_CONT_WDTH_SHIFT                    (16U)
    520. 

  520. #define CSL_DMM_PAT_GEOMETRY_CONT_WDTH_RESETVAL                 (0x00000008U)
    521. 

  521. #define CSL_DMM_PAT_GEOMETRY_CONT_WDTH_MAX                      (0x0000000fU)
    522. 

  522. 

  523. #define CSL_DMM_PAT_GEOMETRY_CONT_HGHT_MASK                     (0x0F000000U)
    524. 

  524. #define CSL_DMM_PAT_GEOMETRY_CONT_HGHT_SHIFT                    (24U)
    525. 

  525. #define CSL_DMM_PAT_GEOMETRY_CONT_HGHT_RESETVAL                 (0x00000008U)
    526. 

  526. #define CSL_DMM_PAT_GEOMETRY_CONT_HGHT_MAX                      (0x0000000fU)
    527. 

  527. 

  528. #define CSL_DMM_PAT_GEOMETRY_ADDR_RANGE_MASK                    (0x00003F00U)
    529. 

  529. #define CSL_DMM_PAT_GEOMETRY_ADDR_RANGE_SHIFT                   (8U)
    530. 

  530. #define CSL_DMM_PAT_GEOMETRY_ADDR_RANGE_RESETVAL                (0x00000010U)
    531. 

  531. #define CSL_DMM_PAT_GEOMETRY_ADDR_RANGE_MAX                     (0x0000003fU)
    532. 

  532. 

  533. #define CSL_DMM_PAT_GEOMETRY_RESETVAL                           (0x08081001U)
    534. 

  534. 

  535. /* PAT_CONFIG */
    536. 

  536. 

  537. #define CSL_DMM_PAT_CONFIG_MODE0_MASK                           (0x00000001U)
    538. 

  538. #define CSL_DMM_PAT_CONFIG_MODE0_SHIFT                          (0U)
    539. 

  539. #define CSL_DMM_PAT_CONFIG_MODE0_RESETVAL                       (0x00000000U)
    540. 

  540. #define CSL_DMM_PAT_CONFIG_MODE0_PROG                           (0x00000000U)
    541. 

  541. #define CSL_DMM_PAT_CONFIG_MODE0_BYPASS                         (0x00000001U)
    542. 

  542. 

  543. #define CSL_DMM_PAT_CONFIG_MODE1_MASK                           (0x00000002U)
    544. 

  544. #define CSL_DMM_PAT_CONFIG_MODE1_SHIFT                          (1U)
    545. 

  545. #define CSL_DMM_PAT_CONFIG_MODE1_RESETVAL                       (0x00000000U)
    546. 

  546. #define CSL_DMM_PAT_CONFIG_MODE1_PROG                           (0x00000000U)
    547. 

  547. #define CSL_DMM_PAT_CONFIG_MODE1_BYPASS                         (0x00000001U)
    548. 

  548. 

  549. #define CSL_DMM_PAT_CONFIG_MODE2_MASK                           (0x00000004U)
    550. 

  550. #define CSL_DMM_PAT_CONFIG_MODE2_SHIFT                          (2U)
    551. 

  551. #define CSL_DMM_PAT_CONFIG_MODE2_RESETVAL                       (0x00000000U)
    552. 

  552. #define CSL_DMM_PAT_CONFIG_MODE2_PROG                           (0x00000000U)
    553. 

  553. #define CSL_DMM_PAT_CONFIG_MODE2_BYPASS                         (0x00000001U)
    554. 

  554. 

  555. #define CSL_DMM_PAT_CONFIG_MODE3_MASK                           (0x00000008U)
    556. 

  556. #define CSL_DMM_PAT_CONFIG_MODE3_SHIFT                          (3U)
    557. 

  557. #define CSL_DMM_PAT_CONFIG_MODE3_RESETVAL                       (0x00000000U)
    558. 

  558. #define CSL_DMM_PAT_CONFIG_MODE3_PROG                           (0x00000000U)
    559. 

  559. #define CSL_DMM_PAT_CONFIG_MODE3_BYPASS                         (0x00000001U)
    560. 

  560. 

  561. #define CSL_DMM_PAT_CONFIG_MODE4_MASK                           (0x00000000U)
    562. 

  562. #define CSL_DMM_PAT_CONFIG_MODE4_SHIFT                          (4U)
    563. 

  563. #define CSL_DMM_PAT_CONFIG_MODE4_RESETVAL                       (0x00000000U)
    564. 

  564. #define CSL_DMM_PAT_CONFIG_MODE4_PROG                           (0x00000000U)
    565. 

  565. #define CSL_DMM_PAT_CONFIG_MODE4_BYPASS                         (0x00000001U)
    566. 

  566. 

  567. #define CSL_DMM_PAT_CONFIG_MODE5_MASK                           (0x00000000U)
    568. 

  568. #define CSL_DMM_PAT_CONFIG_MODE5_SHIFT                          (5U)
    569. 

  569. #define CSL_DMM_PAT_CONFIG_MODE5_RESETVAL                       (0x00000000U)
    570. 

  570. #define CSL_DMM_PAT_CONFIG_MODE5_PROG                           (0x00000000U)
    571. 

  571. #define CSL_DMM_PAT_CONFIG_MODE5_BYPASS                         (0x00000001U)
    572. 

  572. 

  573. #define CSL_DMM_PAT_CONFIG_MODE6_MASK                           (0x00000000U)
    574. 

  574. #define CSL_DMM_PAT_CONFIG_MODE6_SHIFT                          (6U)
    575. 

  575. #define CSL_DMM_PAT_CONFIG_MODE6_RESETVAL                       (0x00000000U)
    576. 

  576. #define CSL_DMM_PAT_CONFIG_MODE6_PROG                           (0x00000000U)
    577. 

  577. #define CSL_DMM_PAT_CONFIG_MODE6_BYPASS                         (0x00000001U)
    578. 

  578. 

  579. #define CSL_DMM_PAT_CONFIG_MODE7_MASK                           (0x00000000U)
    580. 

  580. #define CSL_DMM_PAT_CONFIG_MODE7_SHIFT                          (7U)
    581. 

  581. #define CSL_DMM_PAT_CONFIG_MODE7_RESETVAL                       (0x00000000U)
    582. 

  582. #define CSL_DMM_PAT_CONFIG_MODE7_PROG                           (0x00000000U)
    583. 

  583. #define CSL_DMM_PAT_CONFIG_MODE7_BYPASS                         (0x00000001U)
    584. 

  584. 

  585. #define CSL_DMM_PAT_CONFIG_MODE8_MASK                           (0x00000000U)
    586. 

  586. #define CSL_DMM_PAT_CONFIG_MODE8_SHIFT                          (8U)
    587. 

  587. #define CSL_DMM_PAT_CONFIG_MODE8_RESETVAL                       (0x00000000U)
    588. 

  588. #define CSL_DMM_PAT_CONFIG_MODE8_PROG                           (0x00000000U)
    589. 

  589. #define CSL_DMM_PAT_CONFIG_MODE8_BYPASS                         (0x00000001U)
    590. 

  590. 

  591. #define CSL_DMM_PAT_CONFIG_MODE9_MASK                           (0x00000000U)
    592. 

  592. #define CSL_DMM_PAT_CONFIG_MODE9_SHIFT                          (9U)
    593. 

  593. #define CSL_DMM_PAT_CONFIG_MODE9_RESETVAL                       (0x00000000U)
    594. 

  594. #define CSL_DMM_PAT_CONFIG_MODE9_PROG                           (0x00000000U)
    595. 

  595. #define CSL_DMM_PAT_CONFIG_MODE9_BYPASS                         (0x00000001U)
    596. 

  596. 

  597. #define CSL_DMM_PAT_CONFIG_MODE10_MASK                          (0x00000000U)
    598. 

  598. #define CSL_DMM_PAT_CONFIG_MODE10_SHIFT                         (10U)
    599. 

  599. #define CSL_DMM_PAT_CONFIG_MODE10_RESETVAL                      (0x00000000U)
    600. 

  600. #define CSL_DMM_PAT_CONFIG_MODE10_PROG                          (0x00000000U)
    601. 

  601. #define CSL_DMM_PAT_CONFIG_MODE10_BYPASS                        (0x00000001U)
    602. 

  602. 

  603. #define CSL_DMM_PAT_CONFIG_MODE11_MASK                          (0x00000000U)
    604. 

  604. #define CSL_DMM_PAT_CONFIG_MODE11_SHIFT                         (11U)
    605. 

  605. #define CSL_DMM_PAT_CONFIG_MODE11_RESETVAL                      (0x00000000U)
    606. 

  606. #define CSL_DMM_PAT_CONFIG_MODE11_PROG                          (0x00000000U)
    607. 

  607. #define CSL_DMM_PAT_CONFIG_MODE11_BYPASS                        (0x00000001U)
    608. 

  608. 

  609. #define CSL_DMM_PAT_CONFIG_MODE12_MASK                          (0x00000000U)
    610. 

  610. #define CSL_DMM_PAT_CONFIG_MODE12_SHIFT                         (12U)
    611. 

  611. #define CSL_DMM_PAT_CONFIG_MODE12_RESETVAL                      (0x00000000U)
    612. 

  612. #define CSL_DMM_PAT_CONFIG_MODE12_PROG                          (0x00000000U)
    613. 

  613. #define CSL_DMM_PAT_CONFIG_MODE12_BYPASS                        (0x00000001U)
    614. 

  614. 

  615. #define CSL_DMM_PAT_CONFIG_MODE13_MASK                          (0x00000000U)
    616. 

  616. #define CSL_DMM_PAT_CONFIG_MODE13_SHIFT                         (13U)
    617. 

  617. #define CSL_DMM_PAT_CONFIG_MODE13_RESETVAL                      (0x00000000U)
    618. 

  618. #define CSL_DMM_PAT_CONFIG_MODE13_PROG                          (0x00000000U)
    619. 

  619. #define CSL_DMM_PAT_CONFIG_MODE13_BYPASS                        (0x00000001U)
    620. 

  620. 

  621. #define CSL_DMM_PAT_CONFIG_MODE14_MASK                          (0x00000000U)
    622. 

  622. #define CSL_DMM_PAT_CONFIG_MODE14_SHIFT                         (14U)
    623. 

  623. #define CSL_DMM_PAT_CONFIG_MODE14_RESETVAL                      (0x00000000U)
    624. 

  624. #define CSL_DMM_PAT_CONFIG_MODE14_PROG                          (0x00000000U)
    625. 

  625. #define CSL_DMM_PAT_CONFIG_MODE14_BYPASS                        (0x00000001U)
    626. 

  626. 

  627. #define CSL_DMM_PAT_CONFIG_MODE15_MASK                          (0x00000000U)
    628. 

  628. #define CSL_DMM_PAT_CONFIG_MODE15_SHIFT                         (15U)
    629. 

  629. #define CSL_DMM_PAT_CONFIG_MODE15_RESETVAL                      (0x00000000U)
    630. 

  630. #define CSL_DMM_PAT_CONFIG_MODE15_PROG                          (0x00000000U)
    631. 

  631. #define CSL_DMM_PAT_CONFIG_MODE15_BYPASS                        (0x00000001U)
    632. 

  632. 

  633. #define CSL_DMM_PAT_CONFIG_RESETVAL                             (0x00000000U)
    634. 

  634. 

  635. /* PAT_VIEW */
    636. 

  636. 

  637. #define CSL_DMM_PAT_VIEW_V0_MASK                                (0x00000003U)
    638. 

  638. #define CSL_DMM_PAT_VIEW_V0_SHIFT                               (0U)
    639. 

  639. #define CSL_DMM_PAT_VIEW_V0_RESETVAL                            (0x00000000U)
    640. 

  640. #define CSL_DMM_PAT_VIEW_V0_MAX                                 (0x00000003U)
    641. 

  641. 

  642. #define CSL_DMM_PAT_VIEW_W0_MASK                                (0x00000008U)
    643. 

  643. #define CSL_DMM_PAT_VIEW_W0_SHIFT                               (3U)
    644. 

  644. #define CSL_DMM_PAT_VIEW_W0_RESETVAL                            (0x00000000U)
    645. 

  645. #define CSL_DMM_PAT_VIEW_W0_UPDATE                              (0x00000001U)
    646. 

  646. #define CSL_DMM_PAT_VIEW_W0_KEEP                                (0x00000000U)
    647. 

  647. 

  648. #define CSL_DMM_PAT_VIEW_V1_MASK                                (0x00000030U)
    649. 

  649. #define CSL_DMM_PAT_VIEW_V1_SHIFT                               (4U)
    650. 

  650. #define CSL_DMM_PAT_VIEW_V1_RESETVAL                            (0x00000000U)
    651. 

  651. #define CSL_DMM_PAT_VIEW_V1_MAX                                 (0x00000003U)
    652. 

  652. 

  653. #define CSL_DMM_PAT_VIEW_W1_MASK                                (0x00000080U)
    654. 

  654. #define CSL_DMM_PAT_VIEW_W1_SHIFT                               (7U)
    655. 

  655. #define CSL_DMM_PAT_VIEW_W1_RESETVAL                            (0x00000000U)
    656. 

  656. #define CSL_DMM_PAT_VIEW_W1_UPDATE                              (0x00000001U)
    657. 

  657. #define CSL_DMM_PAT_VIEW_W1_KEEP                                (0x00000000U)
    658. 

  658. 

  659. #define CSL_DMM_PAT_VIEW_V2_MASK                                (0x00000300U)
    660. 

  660. #define CSL_DMM_PAT_VIEW_V2_SHIFT                               (8U)
    661. 

  661. #define CSL_DMM_PAT_VIEW_V2_RESETVAL                            (0x00000000U)
    662. 

  662. #define CSL_DMM_PAT_VIEW_V2_MAX                                 (0x00000003U)
    663. 

  663. 

  664. #define CSL_DMM_PAT_VIEW_W2_MASK                                (0x00000800U)
    665. 

  665. #define CSL_DMM_PAT_VIEW_W2_SHIFT                               (11U)
    666. 

  666. #define CSL_DMM_PAT_VIEW_W2_RESETVAL                            (0x00000000U)
    667. 

  667. #define CSL_DMM_PAT_VIEW_W2_UPDATE                              (0x00000001U)
    668. 

  668. #define CSL_DMM_PAT_VIEW_W2_KEEP                                (0x00000000U)
    669. 

  669. 

  670. #define CSL_DMM_PAT_VIEW_V3_MASK                                (0x00003000U)
    671. 

  671. #define CSL_DMM_PAT_VIEW_V3_SHIFT                               (12U)
    672. 

  672. #define CSL_DMM_PAT_VIEW_V3_RESETVAL                            (0x00000000U)
    673. 

  673. #define CSL_DMM_PAT_VIEW_V3_MAX                                 (0x00000003U)
    674. 

  674. 

  675. #define CSL_DMM_PAT_VIEW_W3_MASK                                (0x00008000U)
    676. 

  676. #define CSL_DMM_PAT_VIEW_W3_SHIFT                               (15U)
    677. 

  677. #define CSL_DMM_PAT_VIEW_W3_RESETVAL                            (0x00000000U)
    678. 

  678. #define CSL_DMM_PAT_VIEW_W3_UPDATE                              (0x00000001U)
    679. 

  679. #define CSL_DMM_PAT_VIEW_W3_KEEP                                (0x00000000U)
    680. 

  680. 

  681. #define CSL_DMM_PAT_VIEW_V4_MASK                                (0x00030000U)
    682. 

  682. #define CSL_DMM_PAT_VIEW_V4_SHIFT                               (16U)
    683. 

  683. #define CSL_DMM_PAT_VIEW_V4_RESETVAL                            (0x00000000U)
    684. 

  684. #define CSL_DMM_PAT_VIEW_V4_MAX                                 (0x00000003U)
    685. 

  685. 

  686. #define CSL_DMM_PAT_VIEW_W4_MASK                                (0x00080000U)
    687. 

  687. #define CSL_DMM_PAT_VIEW_W4_SHIFT                               (19U)
    688. 

  688. #define CSL_DMM_PAT_VIEW_W4_RESETVAL                            (0x00000000U)
    689. 

  689. #define CSL_DMM_PAT_VIEW_W4_UPDATE                              (0x00000001U)
    690. 

  690. #define CSL_DMM_PAT_VIEW_W4_KEEP                                (0x00000000U)
    691. 

  691. 

  692. #define CSL_DMM_PAT_VIEW_V5_MASK                                (0x00300000U)
    693. 

  693. #define CSL_DMM_PAT_VIEW_V5_SHIFT                               (20U)
    694. 

  694. #define CSL_DMM_PAT_VIEW_V5_RESETVAL                            (0x00000000U)
    695. 

  695. #define CSL_DMM_PAT_VIEW_V5_MAX                                 (0x00000003U)
    696. 

  696. 

  697. #define CSL_DMM_PAT_VIEW_W5_MASK                                (0x00800000U)
    698. 

  698. #define CSL_DMM_PAT_VIEW_W5_SHIFT                               (23U)
    699. 

  699. #define CSL_DMM_PAT_VIEW_W5_RESETVAL                            (0x00000000U)
    700. 

  700. #define CSL_DMM_PAT_VIEW_W5_UPDATE                              (0x00000001U)
    701. 

  701. #define CSL_DMM_PAT_VIEW_W5_KEEP                                (0x00000000U)
    702. 

  702. 

  703. #define CSL_DMM_PAT_VIEW_V6_MASK                                (0x03000000U)
    704. 

  704. #define CSL_DMM_PAT_VIEW_V6_SHIFT                               (24U)
    705. 

  705. #define CSL_DMM_PAT_VIEW_V6_RESETVAL                            (0x00000000U)
    706. 

  706. #define CSL_DMM_PAT_VIEW_V6_MAX                                 (0x00000003U)
    707. 

  707. 

  708. #define CSL_DMM_PAT_VIEW_W6_MASK                                (0x08000000U)
    709. 

  709. #define CSL_DMM_PAT_VIEW_W6_SHIFT                               (27U)
    710. 

  710. #define CSL_DMM_PAT_VIEW_W6_RESETVAL                            (0x00000000U)
    711. 

  711. #define CSL_DMM_PAT_VIEW_W6_UPDATE                              (0x00000001U)
    712. 

  712. #define CSL_DMM_PAT_VIEW_W6_KEEP                                (0x00000000U)
    713. 

  713. 

  714. #define CSL_DMM_PAT_VIEW_V7_MASK                                (0x30000000U)
    715. 

  715. #define CSL_DMM_PAT_VIEW_V7_SHIFT                               (28U)
    716. 

  716. #define CSL_DMM_PAT_VIEW_V7_RESETVAL                            (0x00000000U)
    717. 

  717. #define CSL_DMM_PAT_VIEW_V7_MAX                                 (0x00000003U)
    718. 

  718. 

  719. #define CSL_DMM_PAT_VIEW_W7_MASK                                (0x80000000U)
    720. 

  720. #define CSL_DMM_PAT_VIEW_W7_SHIFT                               (31U)
    721. 

  721. #define CSL_DMM_PAT_VIEW_W7_RESETVAL                            (0x00000000U)
    722. 

  722. #define CSL_DMM_PAT_VIEW_W7_UPDATE                              (0x00000001U)
    723. 

  723. #define CSL_DMM_PAT_VIEW_W7_KEEP                                (0x00000000U)
    724. 

  724. 

  725. #define CSL_DMM_PAT_VIEW_RESETVAL                               (0x00000000U)
    726. 

  726. 

  727. /* PAT_VIEW_MAP */
    728. 

  728. 

  729. #define CSL_DMM_PAT_VIEW_MAP_CONT_8_MASK                        (0x00000007U)
    730. 

  730. #define CSL_DMM_PAT_VIEW_MAP_CONT_8_SHIFT                       (0U)
    731. 

  731. #define CSL_DMM_PAT_VIEW_MAP_CONT_8_RESETVAL                    (0x00000000U)
    732. 

  732. #define CSL_DMM_PAT_VIEW_MAP_CONT_8_MAX                         (0x00000007U)
    733. 

  733. 

  734. #define CSL_DMM_PAT_VIEW_MAP_CONT_16_MASK                       (0x00000700U)
    735. 

  735. #define CSL_DMM_PAT_VIEW_MAP_CONT_16_SHIFT                      (8U)
    736. 

  736. #define CSL_DMM_PAT_VIEW_MAP_CONT_16_RESETVAL                   (0x00000000U)
    737. 

  737. #define CSL_DMM_PAT_VIEW_MAP_CONT_16_MAX                        (0x00000007U)
    738. 

  738. 

  739. #define CSL_DMM_PAT_VIEW_MAP_CONT_32_MASK                       (0x00070000U)
    740. 

  740. #define CSL_DMM_PAT_VIEW_MAP_CONT_32_SHIFT                      (16U)
    741. 

  741. #define CSL_DMM_PAT_VIEW_MAP_CONT_32_RESETVAL                   (0x00000000U)
    742. 

  742. #define CSL_DMM_PAT_VIEW_MAP_CONT_32_MAX                        (0x00000007U)
    743. 

  743. 

  744. #define CSL_DMM_PAT_VIEW_MAP_CONT_PAGE_MASK                     (0x07000000U)
    745. 

  745. #define CSL_DMM_PAT_VIEW_MAP_CONT_PAGE_SHIFT                    (24U)
    746. 

  746. #define CSL_DMM_PAT_VIEW_MAP_CONT_PAGE_RESETVAL                 (0x00000000U)
    747. 

  747. #define CSL_DMM_PAT_VIEW_MAP_CONT_PAGE_MAX                      (0x00000007U)
    748. 

  748. 

  749. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_8_MASK                      (0x00000080U)
    750. 

  750. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_8_SHIFT                     (7U)
    751. 

  751. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_8_RESETVAL                  (0x00000000U)
    752. 

  752. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_8_DIRECT                    (0x00000000U)
    753. 

  753. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_8_LUT                       (0x00000001U)
    754. 

  754. 

  755. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_16_MASK                     (0x00008000U)
    756. 

  756. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_16_SHIFT                    (15U)
    757. 

  757. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_16_RESETVAL                 (0x00000000U)
    758. 

  758. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_16_DIRECT                   (0x00000000U)
    759. 

  759. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_16_LUT                      (0x00000001U)
    760. 

  760. 

  761. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_32_MASK                     (0x00800000U)
    762. 

  762. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_32_SHIFT                    (23U)
    763. 

  763. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_32_RESETVAL                 (0x00000000U)
    764. 

  764. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_32_DIRECT                   (0x00000000U)
    765. 

  765. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_32_LUT                      (0x00000001U)
    766. 

  766. 

  767. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_PAGE_MASK                   (0x80000000U)
    768. 

  768. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_PAGE_SHIFT                  (31U)
    769. 

  769. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_PAGE_RESETVAL               (0x00000000U)
    770. 

  770. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_PAGE_DIRECT                 (0x00000000U)
    771. 

  771. #define CSL_DMM_PAT_VIEW_MAP_ACCESS_PAGE_LUT                    (0x00000001U)
    772. 

  772. 

  773. #define CSL_DMM_PAT_VIEW_MAP_RESETVAL                           (0x00000000U)
    774. 

  774. 

  775. /* PAT_VIEW_MAP_BASE */
    776. 

  776. 

  777. #define CSL_DMM_PAT_VIEW_MAP_BASE_BASE_ADDR_MASK                (0x80000000U)
    778. 

  778. #define CSL_DMM_PAT_VIEW_MAP_BASE_BASE_ADDR_SHIFT               (31U)
    779. 

  779. #define CSL_DMM_PAT_VIEW_MAP_BASE_BASE_ADDR_RESETVAL            (0x00000000U)
    780. 

  780. #define CSL_DMM_PAT_VIEW_MAP_BASE_BASE_ADDR_MAX                 (0x00000001U)
    781. 

  781. 

  782. #define CSL_DMM_PAT_VIEW_MAP_BASE_RESETVAL                      (0x00000000U)
    783. 

  783. 

  784. /* PAT_IRQ_EOI */
    785. 

  785. 

  786. #define CSL_DMM_PAT_IRQ_EOI_EOI_MASK                            (0x00000001U)
    787. 

  787. #define CSL_DMM_PAT_IRQ_EOI_EOI_SHIFT                           (0U)
    788. 

  788. #define CSL_DMM_PAT_IRQ_EOI_EOI_RESETVAL                        (0x00000000U)
    789. 

  789. #define CSL_DMM_PAT_IRQ_EOI_EOI_ACK                             (0x00000000U)
    790. 

  790. 

  791. #define CSL_DMM_PAT_IRQ_EOI_RESETVAL                            (0x00000000U)
    792. 

  792. 

  793. /* PAT_IRQSTS_RAW */
    794. 

  794. 

  795. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_MASK                   (0x00000001U)
    796. 

  796. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_SHIFT                  (0U)
    797. 

  797. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_RESETVAL               (0x00000000U)
    798. 

  798. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_KEEP                   (0x00000000U)
    799. 

  799. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_SET                    (0x00000001U)
    800. 

  800. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_NOT                    (0x00000000U)
    801. 

  801. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC0_DONE                   (0x00000001U)
    802. 

  802. 

  803. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_MASK                (0x00000004U)
    804. 

  804. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_SHIFT               (2U)
    805. 

  805. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_RESETVAL            (0x00000000U)
    806. 

  806. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_KEEP                (0x00000000U)
    807. 

  807. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_SET                 (0x00000001U)
    808. 

  808. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_NONE                (0x00000000U)
    809. 

  809. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC0_HAPPEN              (0x00000001U)
    810. 

  810. 

  811. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_MASK               (0x00000008U)
    812. 

  812. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_SHIFT              (3U)
    813. 

  813. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_RESETVAL           (0x00000000U)
    814. 

  814. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_KEEP               (0x00000000U)
    815. 

  815. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_SET                (0x00000001U)
    816. 

  816. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_NONE               (0x00000000U)
    817. 

  817. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA0_HAPPEN             (0x00000001U)
    818. 

  818. 

  819. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_MASK                   (0x00000002U)
    820. 

  820. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_SHIFT                  (1U)
    821. 

  821. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_RESETVAL               (0x00000000U)
    822. 

  822. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_KEEP                   (0x00000000U)
    823. 

  823. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_SET                    (0x00000001U)
    824. 

  824. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_NOT                    (0x00000000U)
    825. 

  825. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST0_DONE                   (0x00000001U)
    826. 

  826. 

  827. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_MASK               (0x00000010U)
    828. 

  828. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_SHIFT              (4U)
    829. 

  829. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_RESETVAL           (0x00000000U)
    830. 

  830. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_KEEP               (0x00000000U)
    831. 

  831. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_SET                (0x00000001U)
    832. 

  832. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_NONE               (0x00000000U)
    833. 

  833. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA0_HAPPEN             (0x00000001U)
    834. 

  834. 

  835. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_MASK               (0x00000020U)
    836. 

  836. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_SHIFT              (5U)
    837. 

  837. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_RESETVAL           (0x00000000U)
    838. 

  838. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_KEEP               (0x00000000U)
    839. 

  839. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_SET                (0x00000001U)
    840. 

  840. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_NONE               (0x00000000U)
    841. 

  841. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL0_HAPPEN             (0x00000001U)
    842. 

  842. 

  843. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_MASK               (0x00000040U)
    844. 

  844. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_SHIFT              (6U)
    845. 

  845. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_RESETVAL           (0x00000000U)
    846. 

  846. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_KEEP               (0x00000000U)
    847. 

  847. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_SET                (0x00000001U)
    848. 

  848. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_NONE               (0x00000000U)
    849. 

  849. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA0_HAPPEN             (0x00000001U)
    850. 

  850. 

  851. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_MASK               (0x00000080U)
    852. 

  852. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_SHIFT              (7U)
    853. 

  853. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_RESETVAL           (0x00000000U)
    854. 

  854. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_KEEP               (0x00000000U)
    855. 

  855. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_SET                (0x00000001U)
    856. 

  856. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_NONE               (0x00000000U)
    857. 

  857. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS0_HAPPEN             (0x00000001U)
    858. 

  858. 

  859. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_MASK                   (0x00000100U)
    860. 

  860. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_SHIFT                  (8U)
    861. 

  861. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_RESETVAL               (0x00000000U)
    862. 

  862. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_KEEP                   (0x00000000U)
    863. 

  863. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_SET                    (0x00000001U)
    864. 

  864. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_NOT                    (0x00000000U)
    865. 

  865. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC1_DONE                   (0x00000001U)
    866. 

  866. 

  867. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_MASK                (0x00000400U)
    868. 

  868. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_SHIFT               (10U)
    869. 

  869. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_RESETVAL            (0x00000000U)
    870. 

  870. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_KEEP                (0x00000000U)
    871. 

  871. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_SET                 (0x00000001U)
    872. 

  872. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_NONE                (0x00000000U)
    873. 

  873. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC1_HAPPEN              (0x00000001U)
    874. 

  874. 

  875. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_MASK               (0x00000800U)
    876. 

  876. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_SHIFT              (11U)
    877. 

  877. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_RESETVAL           (0x00000000U)
    878. 

  878. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_KEEP               (0x00000000U)
    879. 

  879. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_SET                (0x00000001U)
    880. 

  880. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_NONE               (0x00000000U)
    881. 

  881. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA1_HAPPEN             (0x00000001U)
    882. 

  882. 

  883. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_MASK                   (0x00000200U)
    884. 

  884. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_SHIFT                  (9U)
    885. 

  885. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_RESETVAL               (0x00000000U)
    886. 

  886. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_KEEP                   (0x00000000U)
    887. 

  887. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_SET                    (0x00000001U)
    888. 

  888. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_NOT                    (0x00000000U)
    889. 

  889. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST1_DONE                   (0x00000001U)
    890. 

  890. 

  891. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_MASK               (0x00001000U)
    892. 

  892. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_SHIFT              (12U)
    893. 

  893. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_RESETVAL           (0x00000000U)
    894. 

  894. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_KEEP               (0x00000000U)
    895. 

  895. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_SET                (0x00000001U)
    896. 

  896. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_NONE               (0x00000000U)
    897. 

  897. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA1_HAPPEN             (0x00000001U)
    898. 

  898. 

  899. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_MASK               (0x00002000U)
    900. 

  900. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_SHIFT              (13U)
    901. 

  901. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_RESETVAL           (0x00000000U)
    902. 

  902. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_KEEP               (0x00000000U)
    903. 

  903. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_SET                (0x00000001U)
    904. 

  904. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_NONE               (0x00000000U)
    905. 

  905. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL1_HAPPEN             (0x00000001U)
    906. 

  906. 

  907. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_MASK               (0x00004000U)
    908. 

  908. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_SHIFT              (14U)
    909. 

  909. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_RESETVAL           (0x00000000U)
    910. 

  910. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_KEEP               (0x00000000U)
    911. 

  911. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_SET                (0x00000001U)
    912. 

  912. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_NONE               (0x00000000U)
    913. 

  913. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA1_HAPPEN             (0x00000001U)
    914. 

  914. 

  915. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_MASK               (0x00008000U)
    916. 

  916. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_SHIFT              (15U)
    917. 

  917. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_RESETVAL           (0x00000000U)
    918. 

  918. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_KEEP               (0x00000000U)
    919. 

  919. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_SET                (0x00000001U)
    920. 

  920. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_NONE               (0x00000000U)
    921. 

  921. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS1_HAPPEN             (0x00000001U)
    922. 

  922. 

  923. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_MASK                   (0x00010000U)
    924. 

  924. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_SHIFT                  (16U)
    925. 

  925. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_RESETVAL               (0x00000000U)
    926. 

  926. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_KEEP                   (0x00000000U)
    927. 

  927. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_SET                    (0x00000001U)
    928. 

  928. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_NOT                    (0x00000000U)
    929. 

  929. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC2_DONE                   (0x00000001U)
    930. 

  930. 

  931. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_MASK                (0x00040000U)
    932. 

  932. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_SHIFT               (18U)
    933. 

  933. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_RESETVAL            (0x00000000U)
    934. 

  934. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_KEEP                (0x00000000U)
    935. 

  935. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_SET                 (0x00000001U)
    936. 

  936. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_NONE                (0x00000000U)
    937. 

  937. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC2_HAPPEN              (0x00000001U)
    938. 

  938. 

  939. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_MASK               (0x00080000U)
    940. 

  940. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_SHIFT              (19U)
    941. 

  941. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_RESETVAL           (0x00000000U)
    942. 

  942. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_KEEP               (0x00000000U)
    943. 

  943. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_SET                (0x00000001U)
    944. 

  944. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_NONE               (0x00000000U)
    945. 

  945. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA2_HAPPEN             (0x00000001U)
    946. 

  946. 

  947. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_MASK                   (0x00020000U)
    948. 

  948. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_SHIFT                  (17U)
    949. 

  949. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_RESETVAL               (0x00000000U)
    950. 

  950. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_KEEP                   (0x00000000U)
    951. 

  951. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_SET                    (0x00000001U)
    952. 

  952. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_NOT                    (0x00000000U)
    953. 

  953. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST2_DONE                   (0x00000001U)
    954. 

  954. 

  955. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_MASK               (0x00100000U)
    956. 

  956. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_SHIFT              (20U)
    957. 

  957. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_RESETVAL           (0x00000000U)
    958. 

  958. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_KEEP               (0x00000000U)
    959. 

  959. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_SET                (0x00000001U)
    960. 

  960. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_NONE               (0x00000000U)
    961. 

  961. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA2_HAPPEN             (0x00000001U)
    962. 

  962. 

  963. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_MASK               (0x00200000U)
    964. 

  964. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_SHIFT              (21U)
    965. 

  965. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_RESETVAL           (0x00000000U)
    966. 

  966. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_KEEP               (0x00000000U)
    967. 

  967. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_SET                (0x00000001U)
    968. 

  968. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_NONE               (0x00000000U)
    969. 

  969. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL2_HAPPEN             (0x00000001U)
    970. 

  970. 

  971. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_MASK               (0x00400000U)
    972. 

  972. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_SHIFT              (22U)
    973. 

  973. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_RESETVAL           (0x00000000U)
    974. 

  974. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_KEEP               (0x00000000U)
    975. 

  975. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_SET                (0x00000001U)
    976. 

  976. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_NONE               (0x00000000U)
    977. 

  977. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA2_HAPPEN             (0x00000001U)
    978. 

  978. 

  979. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_MASK               (0x00800000U)
    980. 

  980. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_SHIFT              (23U)
    981. 

  981. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_RESETVAL           (0x00000000U)
    982. 

  982. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_KEEP               (0x00000000U)
    983. 

  983. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_SET                (0x00000001U)
    984. 

  984. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_NONE               (0x00000000U)
    985. 

  985. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS2_HAPPEN             (0x00000001U)
    986. 

  986. 

  987. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_MASK                   (0x01000000U)
    988. 

  988. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_SHIFT                  (24U)
    989. 

  989. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_RESETVAL               (0x00000000U)
    990. 

  990. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_KEEP                   (0x00000000U)
    991. 

  991. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_SET                    (0x00000001U)
    992. 

  992. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_NOT                    (0x00000000U)
    993. 

  993. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_DSC3_DONE                   (0x00000001U)
    994. 

  994. 

  995. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_MASK                (0x04000000U)
    996. 

  996. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_SHIFT               (26U)
    997. 

  997. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_RESETVAL            (0x00000000U)
    998. 

  998. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_KEEP                (0x00000000U)
    999. 

  999. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_SET                 (0x00000001U)
    1000. 

  1000. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_NONE                (0x00000000U)
    1001. 

  1001. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DSC3_HAPPEN              (0x00000001U)
    1002. 

  1002. 

  1003. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_MASK               (0x08000000U)
    1004. 

  1004. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_SHIFT              (27U)
    1005. 

  1005. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_RESETVAL           (0x00000000U)
    1006. 

  1006. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_KEEP               (0x00000000U)
    1007. 

  1007. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_SET                (0x00000001U)
    1008. 

  1008. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_NONE               (0x00000000U)
    1009. 

  1009. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_INV_DATA3_HAPPEN             (0x00000001U)
    1010. 

  1010. 

  1011. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_MASK                   (0x02000000U)
    1012. 

  1012. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_SHIFT                  (25U)
    1013. 

  1013. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_RESETVAL               (0x00000000U)
    1014. 

  1014. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_KEEP                   (0x00000000U)
    1015. 

  1015. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_SET                    (0x00000001U)
    1016. 

  1016. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_NOT                    (0x00000000U)
    1017. 

  1017. #define CSL_DMM_PAT_IRQSTS_RAW_FILL_LST3_DONE                   (0x00000001U)
    1018. 

  1018. 

  1019. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_MASK               (0x10000000U)
    1020. 

  1020. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_SHIFT              (28U)
    1021. 

  1021. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_RESETVAL           (0x00000000U)
    1022. 

  1022. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_KEEP               (0x00000000U)
    1023. 

  1023. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_SET                (0x00000001U)
    1024. 

  1024. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_NONE               (0x00000000U)
    1025. 

  1025. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_AREA3_HAPPEN             (0x00000001U)
    1026. 

  1026. 

  1027. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_MASK               (0x20000000U)
    1028. 

  1028. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_SHIFT              (29U)
    1029. 

  1029. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_RESETVAL           (0x00000000U)
    1030. 

  1030. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_KEEP               (0x00000000U)
    1031. 

  1031. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_SET                (0x00000001U)
    1032. 

  1032. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_NONE               (0x00000000U)
    1033. 

  1033. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_CTRL3_HAPPEN             (0x00000001U)
    1034. 

  1034. 

  1035. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_MASK               (0x40000000U)
    1036. 

  1036. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_SHIFT              (30U)
    1037. 

  1037. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_RESETVAL           (0x00000000U)
    1038. 

  1038. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_KEEP               (0x00000000U)
    1039. 

  1039. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_SET                (0x00000001U)
    1040. 

  1040. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_NONE               (0x00000000U)
    1041. 

  1041. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_UPD_DATA3_HAPPEN             (0x00000001U)
    1042. 

  1042. 

  1043. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_MASK               (0x80000000U)
    1044. 

  1044. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_SHIFT              (31U)
    1045. 

  1045. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_RESETVAL           (0x00000000U)
    1046. 

  1046. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_KEEP               (0x00000000U)
    1047. 

  1047. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_SET                (0x00000001U)
    1048. 

  1048. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_NONE               (0x00000000U)
    1049. 

  1049. #define CSL_DMM_PAT_IRQSTS_RAW_ERR_LUT_MISS3_HAPPEN             (0x00000001U)
    1050. 

  1050. 

  1051. #define CSL_DMM_PAT_IRQSTS_RAW_RESETVAL                         (0x00000000U)
    1052. 

  1052. 

  1053. /* PAT_IRQSTS */
    1054. 

  1054. 

  1055. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_MASK                       (0x00000001U)
    1056. 

  1056. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_SHIFT                      (0U)
    1057. 

  1057. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_RESETVAL                   (0x00000000U)
    1058. 

  1058. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_KEEP                       (0x00000000U)
    1059. 

  1059. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_CLR                        (0x00000001U)
    1060. 

  1060. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_NOT                        (0x00000000U)
    1061. 

  1061. #define CSL_DMM_PAT_IRQSTS_FILL_DSC0_DONE                       (0x00000001U)
    1062. 

  1062. 

  1063. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_MASK                       (0x00000002U)
    1064. 

  1064. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_SHIFT                      (1U)
    1065. 

  1065. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_RESETVAL                   (0x00000000U)
    1066. 

  1066. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_KEEP                       (0x00000000U)
    1067. 

  1067. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_CLR                        (0x00000001U)
    1068. 

  1068. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_NOT                        (0x00000000U)
    1069. 

  1069. #define CSL_DMM_PAT_IRQSTS_FILL_LST0_DONE                       (0x00000001U)
    1070. 

  1070. 

  1071. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_MASK                    (0x00000004U)
    1072. 

  1072. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_SHIFT                   (2U)
    1073. 

  1073. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_RESETVAL                (0x00000000U)
    1074. 

  1074. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_KEEP                    (0x00000000U)
    1075. 

  1075. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_CLR                     (0x00000001U)
    1076. 

  1076. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_NONE                    (0x00000000U)
    1077. 

  1077. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC0_HAPPEN                  (0x00000001U)
    1078. 

  1078. 

  1079. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_MASK                   (0x00000008U)
    1080. 

  1080. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_SHIFT                  (3U)
    1081. 

  1081. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_RESETVAL               (0x00000000U)
    1082. 

  1082. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_KEEP                   (0x00000000U)
    1083. 

  1083. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_CLR                    (0x00000001U)
    1084. 

  1084. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_NONE                   (0x00000000U)
    1085. 

  1085. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA0_HAPPEN                 (0x00000001U)
    1086. 

  1086. 

  1087. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_MASK                   (0x00000010U)
    1088. 

  1088. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_SHIFT                  (4U)
    1089. 

  1089. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_RESETVAL               (0x00000000U)
    1090. 

  1090. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_KEEP                   (0x00000000U)
    1091. 

  1091. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_CLR                    (0x00000001U)
    1092. 

  1092. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_NONE                   (0x00000000U)
    1093. 

  1093. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA0_HAPPEN                 (0x00000001U)
    1094. 

  1094. 

  1095. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_MASK                   (0x00000020U)
    1096. 

  1096. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_SHIFT                  (5U)
    1097. 

  1097. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_RESETVAL               (0x00000000U)
    1098. 

  1098. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_KEEP                   (0x00000000U)
    1099. 

  1099. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_CLR                    (0x00000001U)
    1100. 

  1100. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_NONE                   (0x00000000U)
    1101. 

  1101. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL0_HAPPEN                 (0x00000001U)
    1102. 

  1102. 

  1103. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_MASK                   (0x00000040U)
    1104. 

  1104. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_SHIFT                  (6U)
    1105. 

  1105. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_RESETVAL               (0x00000000U)
    1106. 

  1106. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_KEEP                   (0x00000000U)
    1107. 

  1107. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_CLR                    (0x00000001U)
    1108. 

  1108. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_NONE                   (0x00000000U)
    1109. 

  1109. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA0_HAPPEN                 (0x00000001U)
    1110. 

  1110. 

  1111. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_MASK                   (0x00000080U)
    1112. 

  1112. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_SHIFT                  (7U)
    1113. 

  1113. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_RESETVAL               (0x00000000U)
    1114. 

  1114. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_KEEP                   (0x00000000U)
    1115. 

  1115. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_CLR                    (0x00000001U)
    1116. 

  1116. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_NONE                   (0x00000000U)
    1117. 

  1117. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS0_HAPPEN                 (0x00000001U)
    1118. 

  1118. 

  1119. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_MASK                       (0x00000100U)
    1120. 

  1120. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_SHIFT                      (8U)
    1121. 

  1121. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_RESETVAL                   (0x00000000U)
    1122. 

  1122. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_KEEP                       (0x00000000U)
    1123. 

  1123. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_CLR                        (0x00000001U)
    1124. 

  1124. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_NOT                        (0x00000000U)
    1125. 

  1125. #define CSL_DMM_PAT_IRQSTS_FILL_DSC1_DONE                       (0x00000001U)
    1126. 

  1126. 

  1127. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_MASK                       (0x00000200U)
    1128. 

  1128. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_SHIFT                      (9U)
    1129. 

  1129. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_RESETVAL                   (0x00000000U)
    1130. 

  1130. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_KEEP                       (0x00000000U)
    1131. 

  1131. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_CLR                        (0x00000001U)
    1132. 

  1132. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_NOT                        (0x00000000U)
    1133. 

  1133. #define CSL_DMM_PAT_IRQSTS_FILL_LST1_DONE                       (0x00000001U)
    1134. 

  1134. 

  1135. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_MASK                    (0x00000400U)
    1136. 

  1136. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_SHIFT                   (10U)
    1137. 

  1137. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_RESETVAL                (0x00000000U)
    1138. 

  1138. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_KEEP                    (0x00000000U)
    1139. 

  1139. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_CLR                     (0x00000001U)
    1140. 

  1140. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_NONE                    (0x00000000U)
    1141. 

  1141. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC1_HAPPEN                  (0x00000001U)
    1142. 

  1142. 

  1143. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_MASK                   (0x00000800U)
    1144. 

  1144. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_SHIFT                  (11U)
    1145. 

  1145. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_RESETVAL               (0x00000000U)
    1146. 

  1146. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_KEEP                   (0x00000000U)
    1147. 

  1147. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_CLR                    (0x00000001U)
    1148. 

  1148. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_NONE                   (0x00000000U)
    1149. 

  1149. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA1_HAPPEN                 (0x00000001U)
    1150. 

  1150. 

  1151. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_MASK                   (0x00001000U)
    1152. 

  1152. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_SHIFT                  (12U)
    1153. 

  1153. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_RESETVAL               (0x00000000U)
    1154. 

  1154. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_KEEP                   (0x00000000U)
    1155. 

  1155. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_CLR                    (0x00000001U)
    1156. 

  1156. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_NONE                   (0x00000000U)
    1157. 

  1157. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA1_HAPPEN                 (0x00000001U)
    1158. 

  1158. 

  1159. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_MASK                   (0x00002000U)
    1160. 

  1160. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_SHIFT                  (13U)
    1161. 

  1161. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_RESETVAL               (0x00000000U)
    1162. 

  1162. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_KEEP                   (0x00000000U)
    1163. 

  1163. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_CLR                    (0x00000001U)
    1164. 

  1164. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_NONE                   (0x00000000U)
    1165. 

  1165. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL1_HAPPEN                 (0x00000001U)
    1166. 

  1166. 

  1167. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_MASK                   (0x00004000U)
    1168. 

  1168. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_SHIFT                  (14U)
    1169. 

  1169. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_RESETVAL               (0x00000000U)
    1170. 

  1170. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_KEEP                   (0x00000000U)
    1171. 

  1171. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_CLR                    (0x00000001U)
    1172. 

  1172. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_NONE                   (0x00000000U)
    1173. 

  1173. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA1_HAPPEN                 (0x00000001U)
    1174. 

  1174. 

  1175. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_MASK                   (0x00008000U)
    1176. 

  1176. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_SHIFT                  (15U)
    1177. 

  1177. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_RESETVAL               (0x00000000U)
    1178. 

  1178. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_KEEP                   (0x00000000U)
    1179. 

  1179. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_CLR                    (0x00000001U)
    1180. 

  1180. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_NONE                   (0x00000000U)
    1181. 

  1181. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS1_HAPPEN                 (0x00000001U)
    1182. 

  1182. 

  1183. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_MASK                       (0x00010000U)
    1184. 

  1184. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_SHIFT                      (16U)
    1185. 

  1185. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_RESETVAL                   (0x00000000U)
    1186. 

  1186. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_KEEP                       (0x00000000U)
    1187. 

  1187. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_CLR                        (0x00000001U)
    1188. 

  1188. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_NOT                        (0x00000000U)
    1189. 

  1189. #define CSL_DMM_PAT_IRQSTS_FILL_DSC2_DONE                       (0x00000001U)
    1190. 

  1190. 

  1191. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_MASK                       (0x00020000U)
    1192. 

  1192. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_SHIFT                      (17U)
    1193. 

  1193. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_RESETVAL                   (0x00000000U)
    1194. 

  1194. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_KEEP                       (0x00000000U)
    1195. 

  1195. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_CLR                        (0x00000001U)
    1196. 

  1196. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_NOT                        (0x00000000U)
    1197. 

  1197. #define CSL_DMM_PAT_IRQSTS_FILL_LST2_DONE                       (0x00000001U)
    1198. 

  1198. 

  1199. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_MASK                    (0x00040000U)
    1200. 

  1200. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_SHIFT                   (18U)
    1201. 

  1201. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_RESETVAL                (0x00000000U)
    1202. 

  1202. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_KEEP                    (0x00000000U)
    1203. 

  1203. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_CLR                     (0x00000001U)
    1204. 

  1204. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_NONE                    (0x00000000U)
    1205. 

  1205. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC2_HAPPEN                  (0x00000001U)
    1206. 

  1206. 

  1207. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_MASK                   (0x00080000U)
    1208. 

  1208. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_SHIFT                  (19U)
    1209. 

  1209. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_RESETVAL               (0x00000000U)
    1210. 

  1210. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_KEEP                   (0x00000000U)
    1211. 

  1211. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_CLR                    (0x00000001U)
    1212. 

  1212. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_NONE                   (0x00000000U)
    1213. 

  1213. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA2_HAPPEN                 (0x00000001U)
    1214. 

  1214. 

  1215. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_MASK                   (0x00100000U)
    1216. 

  1216. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_SHIFT                  (20U)
    1217. 

  1217. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_RESETVAL               (0x00000000U)
    1218. 

  1218. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_KEEP                   (0x00000000U)
    1219. 

  1219. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_CLR                    (0x00000001U)
    1220. 

  1220. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_NONE                   (0x00000000U)
    1221. 

  1221. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA2_HAPPEN                 (0x00000001U)
    1222. 

  1222. 

  1223. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_MASK                   (0x00200000U)
    1224. 

  1224. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_SHIFT                  (21U)
    1225. 

  1225. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_RESETVAL               (0x00000000U)
    1226. 

  1226. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_KEEP                   (0x00000000U)
    1227. 

  1227. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_CLR                    (0x00000001U)
    1228. 

  1228. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_NONE                   (0x00000000U)
    1229. 

  1229. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL2_HAPPEN                 (0x00000001U)
    1230. 

  1230. 

  1231. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_MASK                   (0x00400000U)
    1232. 

  1232. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_SHIFT                  (22U)
    1233. 

  1233. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_RESETVAL               (0x00000000U)
    1234. 

  1234. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_KEEP                   (0x00000000U)
    1235. 

  1235. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_CLR                    (0x00000001U)
    1236. 

  1236. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_NONE                   (0x00000000U)
    1237. 

  1237. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA2_HAPPEN                 (0x00000001U)
    1238. 

  1238. 

  1239. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_MASK                   (0x00800000U)
    1240. 

  1240. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_SHIFT                  (23U)
    1241. 

  1241. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_RESETVAL               (0x00000000U)
    1242. 

  1242. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_KEEP                   (0x00000000U)
    1243. 

  1243. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_CLR                    (0x00000001U)
    1244. 

  1244. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_NONE                   (0x00000000U)
    1245. 

  1245. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS2_HAPPEN                 (0x00000001U)
    1246. 

  1246. 

  1247. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_MASK                       (0x01000000U)
    1248. 

  1248. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_SHIFT                      (24U)
    1249. 

  1249. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_RESETVAL                   (0x00000000U)
    1250. 

  1250. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_KEEP                       (0x00000000U)
    1251. 

  1251. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_CLR                        (0x00000001U)
    1252. 

  1252. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_NOT                        (0x00000000U)
    1253. 

  1253. #define CSL_DMM_PAT_IRQSTS_FILL_DSC3_DONE                       (0x00000001U)
    1254. 

  1254. 

  1255. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_MASK                       (0x02000000U)
    1256. 

  1256. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_SHIFT                      (25U)
    1257. 

  1257. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_RESETVAL                   (0x00000000U)
    1258. 

  1258. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_KEEP                       (0x00000000U)
    1259. 

  1259. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_CLR                        (0x00000001U)
    1260. 

  1260. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_NOT                        (0x00000000U)
    1261. 

  1261. #define CSL_DMM_PAT_IRQSTS_FILL_LST3_DONE                       (0x00000001U)
    1262. 

  1262. 

  1263. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_MASK                    (0x04000000U)
    1264. 

  1264. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_SHIFT                   (26U)
    1265. 

  1265. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_RESETVAL                (0x00000000U)
    1266. 

  1266. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_KEEP                    (0x00000000U)
    1267. 

  1267. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_CLR                     (0x00000001U)
    1268. 

  1268. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_NONE                    (0x00000000U)
    1269. 

  1269. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DSC3_HAPPEN                  (0x00000001U)
    1270. 

  1270. 

  1271. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_MASK                   (0x08000000U)
    1272. 

  1272. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_SHIFT                  (27U)
    1273. 

  1273. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_RESETVAL               (0x00000000U)
    1274. 

  1274. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_KEEP                   (0x00000000U)
    1275. 

  1275. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_CLR                    (0x00000001U)
    1276. 

  1276. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_NONE                   (0x00000000U)
    1277. 

  1277. #define CSL_DMM_PAT_IRQSTS_ERR_INV_DATA3_HAPPEN                 (0x00000001U)
    1278. 

  1278. 

  1279. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_MASK                   (0x10000000U)
    1280. 

  1280. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_SHIFT                  (28U)
    1281. 

  1281. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_RESETVAL               (0x00000000U)
    1282. 

  1282. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_KEEP                   (0x00000000U)
    1283. 

  1283. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_CLR                    (0x00000001U)
    1284. 

  1284. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_NONE                   (0x00000000U)
    1285. 

  1285. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_AREA3_HAPPEN                 (0x00000001U)
    1286. 

  1286. 

  1287. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_MASK                   (0x20000000U)
    1288. 

  1288. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_SHIFT                  (29U)
    1289. 

  1289. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_RESETVAL               (0x00000000U)
    1290. 

  1290. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_KEEP                   (0x00000000U)
    1291. 

  1291. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_CLR                    (0x00000001U)
    1292. 

  1292. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_NONE                   (0x00000000U)
    1293. 

  1293. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_CTRL3_HAPPEN                 (0x00000001U)
    1294. 

  1294. 

  1295. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_MASK                   (0x40000000U)
    1296. 

  1296. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_SHIFT                  (30U)
    1297. 

  1297. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_RESETVAL               (0x00000000U)
    1298. 

  1298. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_KEEP                   (0x00000000U)
    1299. 

  1299. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_CLR                    (0x00000001U)
    1300. 

  1300. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_NONE                   (0x00000000U)
    1301. 

  1301. #define CSL_DMM_PAT_IRQSTS_ERR_UPD_DATA3_HAPPEN                 (0x00000001U)
    1302. 

  1302. 

  1303. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_MASK                   (0x80000000U)
    1304. 

  1304. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_SHIFT                  (31U)
    1305. 

  1305. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_RESETVAL               (0x00000000U)
    1306. 

  1306. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_KEEP                   (0x00000000U)
    1307. 

  1307. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_CLR                    (0x00000001U)
    1308. 

  1308. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_NONE                   (0x00000000U)
    1309. 

  1309. #define CSL_DMM_PAT_IRQSTS_ERR_LUT_MISS3_HAPPEN                 (0x00000001U)
    1310. 

  1310. 

  1311. #define CSL_DMM_PAT_IRQSTS_RESETVAL                             (0x00000000U)
    1312. 

  1312. 

  1313. /* PAT_IRQEN_SET */
    1314. 

  1314. 

  1315. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_MASK                    (0x00000001U)
    1316. 

  1316. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_SHIFT                   (0U)
    1317. 

  1317. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_RESETVAL                (0x00000000U)
    1318. 

  1318. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_KEEP                    (0x00000000U)
    1319. 

  1319. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_ENABLE                  (0x00000001U)
    1320. 

  1320. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_DISABLED                (0x00000000U)
    1321. 

  1321. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC0_ENABLED                 (0x00000001U)
    1322. 

  1322. 

  1323. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_MASK                    (0x00000002U)
    1324. 

  1324. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_SHIFT                   (1U)
    1325. 

  1325. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_RESETVAL                (0x00000000U)
    1326. 

  1326. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_KEEP                    (0x00000000U)
    1327. 

  1327. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_ENABLE                  (0x00000001U)
    1328. 

  1328. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_DISABLED                (0x00000000U)
    1329. 

  1329. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST0_ENABLED                 (0x00000001U)
    1330. 

  1330. 

  1331. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_MASK                 (0x00000004U)
    1332. 

  1332. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_SHIFT                (2U)
    1333. 

  1333. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_RESETVAL             (0x00000000U)
    1334. 

  1334. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_KEEP                 (0x00000000U)
    1335. 

  1335. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_ENABLE               (0x00000001U)
    1336. 

  1336. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_DISABLED             (0x00000000U)
    1337. 

  1337. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC0_ENABLED              (0x00000001U)
    1338. 

  1338. 

  1339. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_MASK                (0x00000008U)
    1340. 

  1340. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_SHIFT               (3U)
    1341. 

  1341. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_RESETVAL            (0x00000000U)
    1342. 

  1342. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_KEEP                (0x00000000U)
    1343. 

  1343. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_ENABLE              (0x00000001U)
    1344. 

  1344. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_DISABLED            (0x00000000U)
    1345. 

  1345. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA0_ENABLED             (0x00000001U)
    1346. 

  1346. 

  1347. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_MASK                (0x00000010U)
    1348. 

  1348. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_SHIFT               (4U)
    1349. 

  1349. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_RESETVAL            (0x00000000U)
    1350. 

  1350. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_KEEP                (0x00000000U)
    1351. 

  1351. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_ENABLE              (0x00000001U)
    1352. 

  1352. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_DISABLED            (0x00000000U)
    1353. 

  1353. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA0_ENABLED             (0x00000001U)
    1354. 

  1354. 

  1355. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_MASK                (0x00000020U)
    1356. 

  1356. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_SHIFT               (5U)
    1357. 

  1357. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_RESETVAL            (0x00000000U)
    1358. 

  1358. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_KEEP                (0x00000000U)
    1359. 

  1359. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_ENABLE              (0x00000001U)
    1360. 

  1360. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_DISABLED            (0x00000000U)
    1361. 

  1361. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL0_ENABLED             (0x00000001U)
    1362. 

  1362. 

  1363. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_MASK                (0x00000040U)
    1364. 

  1364. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_SHIFT               (6U)
    1365. 

  1365. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_RESETVAL            (0x00000000U)
    1366. 

  1366. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_KEEP                (0x00000000U)
    1367. 

  1367. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_ENABLE              (0x00000001U)
    1368. 

  1368. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_DISABLED            (0x00000000U)
    1369. 

  1369. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA0_ENABLED             (0x00000001U)
    1370. 

  1370. 

  1371. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_MASK                (0x00000080U)
    1372. 

  1372. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_SHIFT               (7U)
    1373. 

  1373. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_RESETVAL            (0x00000000U)
    1374. 

  1374. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_KEEP                (0x00000000U)
    1375. 

  1375. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_ENABLE              (0x00000001U)
    1376. 

  1376. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_DISABLED            (0x00000000U)
    1377. 

  1377. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS0_ENABLED             (0x00000001U)
    1378. 

  1378. 

  1379. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_MASK                    (0x00000100U)
    1380. 

  1380. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_SHIFT                   (8U)
    1381. 

  1381. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_RESETVAL                (0x00000000U)
    1382. 

  1382. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_KEEP                    (0x00000000U)
    1383. 

  1383. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_ENABLE                  (0x00000001U)
    1384. 

  1384. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_DISABLED                (0x00000000U)
    1385. 

  1385. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC1_ENABLED                 (0x00000001U)
    1386. 

  1386. 

  1387. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_MASK                    (0x00000200U)
    1388. 

  1388. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_SHIFT                   (9U)
    1389. 

  1389. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_RESETVAL                (0x00000000U)
    1390. 

  1390. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_KEEP                    (0x00000000U)
    1391. 

  1391. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_ENABLE                  (0x00000001U)
    1392. 

  1392. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_DISABLED                (0x00000000U)
    1393. 

  1393. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST1_ENABLED                 (0x00000001U)
    1394. 

  1394. 

  1395. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_MASK                 (0x00000400U)
    1396. 

  1396. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_SHIFT                (10U)
    1397. 

  1397. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_RESETVAL             (0x00000000U)
    1398. 

  1398. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_KEEP                 (0x00000000U)
    1399. 

  1399. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_ENABLE               (0x00000001U)
    1400. 

  1400. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_DISABLED             (0x00000000U)
    1401. 

  1401. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC1_ENABLED              (0x00000001U)
    1402. 

  1402. 

  1403. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_MASK                (0x00000800U)
    1404. 

  1404. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_SHIFT               (11U)
    1405. 

  1405. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_RESETVAL            (0x00000000U)
    1406. 

  1406. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_KEEP                (0x00000000U)
    1407. 

  1407. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_ENABLE              (0x00000001U)
    1408. 

  1408. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_DISABLED            (0x00000000U)
    1409. 

  1409. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA1_ENABLED             (0x00000001U)
    1410. 

  1410. 

  1411. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_MASK                (0x00001000U)
    1412. 

  1412. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_SHIFT               (12U)
    1413. 

  1413. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_RESETVAL            (0x00000000U)
    1414. 

  1414. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_KEEP                (0x00000000U)
    1415. 

  1415. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_ENABLE              (0x00000001U)
    1416. 

  1416. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_DISABLED            (0x00000000U)
    1417. 

  1417. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA1_ENABLED             (0x00000001U)
    1418. 

  1418. 

  1419. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_MASK                (0x00002000U)
    1420. 

  1420. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_SHIFT               (13U)
    1421. 

  1421. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_RESETVAL            (0x00000000U)
    1422. 

  1422. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_KEEP                (0x00000000U)
    1423. 

  1423. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_ENABLE              (0x00000001U)
    1424. 

  1424. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_DISABLED            (0x00000000U)
    1425. 

  1425. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL1_ENABLED             (0x00000001U)
    1426. 

  1426. 

  1427. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_MASK                (0x00004000U)
    1428. 

  1428. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_SHIFT               (14U)
    1429. 

  1429. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_RESETVAL            (0x00000000U)
    1430. 

  1430. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_KEEP                (0x00000000U)
    1431. 

  1431. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_ENABLE              (0x00000001U)
    1432. 

  1432. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_DISABLED            (0x00000000U)
    1433. 

  1433. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA1_ENABLED             (0x00000001U)
    1434. 

  1434. 

  1435. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_MASK                (0x00008000U)
    1436. 

  1436. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_SHIFT               (15U)
    1437. 

  1437. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_RESETVAL            (0x00000000U)
    1438. 

  1438. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_KEEP                (0x00000000U)
    1439. 

  1439. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_ENABLE              (0x00000001U)
    1440. 

  1440. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_DISABLED            (0x00000000U)
    1441. 

  1441. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS1_ENABLED             (0x00000001U)
    1442. 

  1442. 

  1443. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_MASK                    (0x00010000U)
    1444. 

  1444. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_SHIFT                   (16U)
    1445. 

  1445. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_RESETVAL                (0x00000000U)
    1446. 

  1446. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_KEEP                    (0x00000000U)
    1447. 

  1447. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_ENABLE                  (0x00000001U)
    1448. 

  1448. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_DISABLED                (0x00000000U)
    1449. 

  1449. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC2_ENABLED                 (0x00000001U)
    1450. 

  1450. 

  1451. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_MASK                    (0x00020000U)
    1452. 

  1452. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_SHIFT                   (17U)
    1453. 

  1453. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_RESETVAL                (0x00000000U)
    1454. 

  1454. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_KEEP                    (0x00000000U)
    1455. 

  1455. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_ENABLE                  (0x00000001U)
    1456. 

  1456. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_DISABLED                (0x00000000U)
    1457. 

  1457. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST2_ENABLED                 (0x00000001U)
    1458. 

  1458. 

  1459. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_MASK                 (0x00040000U)
    1460. 

  1460. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_SHIFT                (18U)
    1461. 

  1461. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_RESETVAL             (0x00000000U)
    1462. 

  1462. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_KEEP                 (0x00000000U)
    1463. 

  1463. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_ENABLE               (0x00000001U)
    1464. 

  1464. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_DISABLED             (0x00000000U)
    1465. 

  1465. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC2_ENABLED              (0x00000001U)
    1466. 

  1466. 

  1467. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_MASK                (0x00080000U)
    1468. 

  1468. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_SHIFT               (19U)
    1469. 

  1469. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_RESETVAL            (0x00000000U)
    1470. 

  1470. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_KEEP                (0x00000000U)
    1471. 

  1471. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_ENABLE              (0x00000001U)
    1472. 

  1472. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_DISABLED            (0x00000000U)
    1473. 

  1473. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA2_ENABLED             (0x00000001U)
    1474. 

  1474. 

  1475. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_MASK                (0x00100000U)
    1476. 

  1476. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_SHIFT               (20U)
    1477. 

  1477. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_RESETVAL            (0x00000000U)
    1478. 

  1478. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_KEEP                (0x00000000U)
    1479. 

  1479. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_ENABLE              (0x00000001U)
    1480. 

  1480. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_DISABLED            (0x00000000U)
    1481. 

  1481. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA2_ENABLED             (0x00000001U)
    1482. 

  1482. 

  1483. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_MASK                (0x00200000U)
    1484. 

  1484. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_SHIFT               (21U)
    1485. 

  1485. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_RESETVAL            (0x00000000U)
    1486. 

  1486. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_KEEP                (0x00000000U)
    1487. 

  1487. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_ENABLE              (0x00000001U)
    1488. 

  1488. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_DISABLED            (0x00000000U)
    1489. 

  1489. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL2_ENABLED             (0x00000001U)
    1490. 

  1490. 

  1491. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_MASK                (0x00400000U)
    1492. 

  1492. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_SHIFT               (22U)
    1493. 

  1493. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_RESETVAL            (0x00000000U)
    1494. 

  1494. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_KEEP                (0x00000000U)
    1495. 

  1495. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_ENABLE              (0x00000001U)
    1496. 

  1496. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_DISABLED            (0x00000000U)
    1497. 

  1497. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA2_ENABLED             (0x00000001U)
    1498. 

  1498. 

  1499. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_MASK                (0x00800000U)
    1500. 

  1500. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_SHIFT               (23U)
    1501. 

  1501. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_RESETVAL            (0x00000000U)
    1502. 

  1502. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_KEEP                (0x00000000U)
    1503. 

  1503. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_ENABLE              (0x00000001U)
    1504. 

  1504. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_DISABLED            (0x00000000U)
    1505. 

  1505. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS2_ENABLED             (0x00000001U)
    1506. 

  1506. 

  1507. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_MASK                    (0x01000000U)
    1508. 

  1508. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_SHIFT                   (24U)
    1509. 

  1509. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_RESETVAL                (0x00000000U)
    1510. 

  1510. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_KEEP                    (0x00000000U)
    1511. 

  1511. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_ENABLE                  (0x00000001U)
    1512. 

  1512. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_DISABLED                (0x00000000U)
    1513. 

  1513. #define CSL_DMM_PAT_IRQEN_SET_FILL_DSC3_ENABLED                 (0x00000001U)
    1514. 

  1514. 

  1515. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_MASK                    (0x02000000U)
    1516. 

  1516. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_SHIFT                   (25U)
    1517. 

  1517. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_RESETVAL                (0x00000000U)
    1518. 

  1518. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_KEEP                    (0x00000000U)
    1519. 

  1519. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_ENABLE                  (0x00000001U)
    1520. 

  1520. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_DISABLED                (0x00000000U)
    1521. 

  1521. #define CSL_DMM_PAT_IRQEN_SET_FILL_LST3_ENABLED                 (0x00000001U)
    1522. 

  1522. 

  1523. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_MASK                 (0x04000000U)
    1524. 

  1524. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_SHIFT                (26U)
    1525. 

  1525. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_RESETVAL             (0x00000000U)
    1526. 

  1526. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_KEEP                 (0x00000000U)
    1527. 

  1527. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_ENABLE               (0x00000001U)
    1528. 

  1528. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_DISABLED             (0x00000000U)
    1529. 

  1529. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DSC3_ENABLED              (0x00000001U)
    1530. 

  1530. 

  1531. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_MASK                (0x08000000U)
    1532. 

  1532. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_SHIFT               (27U)
    1533. 

  1533. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_RESETVAL            (0x00000000U)
    1534. 

  1534. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_KEEP                (0x00000000U)
    1535. 

  1535. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_ENABLE              (0x00000001U)
    1536. 

  1536. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_DISABLED            (0x00000000U)
    1537. 

  1537. #define CSL_DMM_PAT_IRQEN_SET_ERR_INV_DATA3_ENABLED             (0x00000001U)
    1538. 

  1538. 

  1539. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_MASK                (0x10000000U)
    1540. 

  1540. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_SHIFT               (28U)
    1541. 

  1541. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_RESETVAL            (0x00000000U)
    1542. 

  1542. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_KEEP                (0x00000000U)
    1543. 

  1543. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_ENABLE              (0x00000001U)
    1544. 

  1544. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_DISABLED            (0x00000000U)
    1545. 

  1545. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_AREA3_ENABLED             (0x00000001U)
    1546. 

  1546. 

  1547. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_MASK                (0x20000000U)
    1548. 

  1548. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_SHIFT               (29U)
    1549. 

  1549. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_RESETVAL            (0x00000000U)
    1550. 

  1550. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_KEEP                (0x00000000U)
    1551. 

  1551. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_ENABLE              (0x00000001U)
    1552. 

  1552. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_DISABLED            (0x00000000U)
    1553. 

  1553. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_CTRL3_ENABLED             (0x00000001U)
    1554. 

  1554. 

  1555. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_MASK                (0x40000000U)
    1556. 

  1556. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_SHIFT               (30U)
    1557. 

  1557. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_RESETVAL            (0x00000000U)
    1558. 

  1558. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_KEEP                (0x00000000U)
    1559. 

  1559. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_ENABLE              (0x00000001U)
    1560. 

  1560. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_DISABLED            (0x00000000U)
    1561. 

  1561. #define CSL_DMM_PAT_IRQEN_SET_ERR_UPD_DATA3_ENABLED             (0x00000001U)
    1562. 

  1562. 

  1563. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_MASK                (0x80000000U)
    1564. 

  1564. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_SHIFT               (31U)
    1565. 

  1565. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_RESETVAL            (0x00000000U)
    1566. 

  1566. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_KEEP                (0x00000000U)
    1567. 

  1567. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_ENABLE              (0x00000001U)
    1568. 

  1568. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_DISABLED            (0x00000000U)
    1569. 

  1569. #define CSL_DMM_PAT_IRQEN_SET_ERR_LUT_MISS3_ENABLED             (0x00000001U)
    1570. 

  1570. 

  1571. #define CSL_DMM_PAT_IRQEN_SET_RESETVAL                          (0x00000000U)
    1572. 

  1572. 

  1573. /* PAT_IRQEN_CLR */
    1574. 

  1574. 

  1575. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_MASK                    (0x00000001U)
    1576. 

  1576. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_SHIFT                   (0U)
    1577. 

  1577. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_RESETVAL                (0x00000000U)
    1578. 

  1578. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_KEEP                    (0x00000000U)
    1579. 

  1579. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_DISABLE                 (0x00000001U)
    1580. 

  1580. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_DISABLED                (0x00000000U)
    1581. 

  1581. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC0_ENABLED                 (0x00000001U)
    1582. 

  1582. 

  1583. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_MASK                    (0x00000002U)
    1584. 

  1584. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_SHIFT                   (1U)
    1585. 

  1585. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_RESETVAL                (0x00000000U)
    1586. 

  1586. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_KEEP                    (0x00000000U)
    1587. 

  1587. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_DISABLE                 (0x00000001U)
    1588. 

  1588. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_DISABLED                (0x00000000U)
    1589. 

  1589. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST0_ENABLED                 (0x00000001U)
    1590. 

  1590. 

  1591. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_MASK                 (0x00000004U)
    1592. 

  1592. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_SHIFT                (2U)
    1593. 

  1593. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_RESETVAL             (0x00000000U)
    1594. 

  1594. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_KEEP                 (0x00000000U)
    1595. 

  1595. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_DISABLE              (0x00000001U)
    1596. 

  1596. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_DISABLED             (0x00000000U)
    1597. 

  1597. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC0_ENABLED              (0x00000001U)
    1598. 

  1598. 

  1599. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_MASK                (0x00000008U)
    1600. 

  1600. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_SHIFT               (3U)
    1601. 

  1601. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_RESETVAL            (0x00000000U)
    1602. 

  1602. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_KEEP                (0x00000000U)
    1603. 

  1603. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_DISABLE             (0x00000001U)
    1604. 

  1604. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_DISABLED            (0x00000000U)
    1605. 

  1605. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA0_ENABLED             (0x00000001U)
    1606. 

  1606. 

  1607. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_MASK                (0x00000010U)
    1608. 

  1608. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_SHIFT               (4U)
    1609. 

  1609. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_RESETVAL            (0x00000000U)
    1610. 

  1610. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_KEEP                (0x00000000U)
    1611. 

  1611. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_DISABLE             (0x00000001U)
    1612. 

  1612. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_DISABLED            (0x00000000U)
    1613. 

  1613. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA0_ENABLED             (0x00000001U)
    1614. 

  1614. 

  1615. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_MASK                (0x00000020U)
    1616. 

  1616. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_SHIFT               (5U)
    1617. 

  1617. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_RESETVAL            (0x00000000U)
    1618. 

  1618. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_KEEP                (0x00000000U)
    1619. 

  1619. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_DISABLE             (0x00000001U)
    1620. 

  1620. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_DISABLED            (0x00000000U)
    1621. 

  1621. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL0_ENABLED             (0x00000001U)
    1622. 

  1622. 

  1623. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_MASK                (0x00000040U)
    1624. 

  1624. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_SHIFT               (6U)
    1625. 

  1625. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_RESETVAL            (0x00000000U)
    1626. 

  1626. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_KEEP                (0x00000000U)
    1627. 

  1627. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_DISABLE             (0x00000001U)
    1628. 

  1628. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_DISABLED            (0x00000000U)
    1629. 

  1629. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA0_ENABLED             (0x00000001U)
    1630. 

  1630. 

  1631. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_MASK                (0x00000080U)
    1632. 

  1632. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_SHIFT               (7U)
    1633. 

  1633. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_RESETVAL            (0x00000000U)
    1634. 

  1634. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_KEEP                (0x00000000U)
    1635. 

  1635. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_DISABLE             (0x00000001U)
    1636. 

  1636. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_DISABLED            (0x00000000U)
    1637. 

  1637. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS0_ENABLED             (0x00000001U)
    1638. 

  1638. 

  1639. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_MASK                    (0x00000100U)
    1640. 

  1640. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_SHIFT                   (8U)
    1641. 

  1641. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_RESETVAL                (0x00000000U)
    1642. 

  1642. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_KEEP                    (0x00000000U)
    1643. 

  1643. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_DISABLE                 (0x00000001U)
    1644. 

  1644. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_DISABLED                (0x00000000U)
    1645. 

  1645. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC1_ENABLED                 (0x00000001U)
    1646. 

  1646. 

  1647. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_MASK                    (0x00000200U)
    1648. 

  1648. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_SHIFT                   (9U)
    1649. 

  1649. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_RESETVAL                (0x00000000U)
    1650. 

  1650. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_KEEP                    (0x00000000U)
    1651. 

  1651. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_DISABLE                 (0x00000001U)
    1652. 

  1652. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_DISABLED                (0x00000000U)
    1653. 

  1653. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST1_ENABLED                 (0x00000001U)
    1654. 

  1654. 

  1655. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_MASK                 (0x00000400U)
    1656. 

  1656. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_SHIFT                (10U)
    1657. 

  1657. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_RESETVAL             (0x00000000U)
    1658. 

  1658. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_KEEP                 (0x00000000U)
    1659. 

  1659. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_DISABLE              (0x00000001U)
    1660. 

  1660. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_DISABLED             (0x00000000U)
    1661. 

  1661. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC1_ENABLED              (0x00000001U)
    1662. 

  1662. 

  1663. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_MASK                (0x00000800U)
    1664. 

  1664. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_SHIFT               (11U)
    1665. 

  1665. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_RESETVAL            (0x00000000U)
    1666. 

  1666. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_KEEP                (0x00000000U)
    1667. 

  1667. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_DISABLE             (0x00000001U)
    1668. 

  1668. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_DISABLED            (0x00000000U)
    1669. 

  1669. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA1_ENABLED             (0x00000001U)
    1670. 

  1670. 

  1671. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_MASK                (0x00001000U)
    1672. 

  1672. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_SHIFT               (12U)
    1673. 

  1673. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_RESETVAL            (0x00000000U)
    1674. 

  1674. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_KEEP                (0x00000000U)
    1675. 

  1675. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_DISABLE             (0x00000001U)
    1676. 

  1676. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_DISABLED            (0x00000000U)
    1677. 

  1677. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA1_ENABLED             (0x00000001U)
    1678. 

  1678. 

  1679. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_MASK                (0x00002000U)
    1680. 

  1680. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_SHIFT               (13U)
    1681. 

  1681. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_RESETVAL            (0x00000000U)
    1682. 

  1682. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_KEEP                (0x00000000U)
    1683. 

  1683. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_DISABLE             (0x00000001U)
    1684. 

  1684. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_DISABLED            (0x00000000U)
    1685. 

  1685. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL1_ENABLED             (0x00000001U)
    1686. 

  1686. 

  1687. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_MASK                (0x00004000U)
    1688. 

  1688. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_SHIFT               (14U)
    1689. 

  1689. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_RESETVAL            (0x00000000U)
    1690. 

  1690. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_KEEP                (0x00000000U)
    1691. 

  1691. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_DISABLE             (0x00000001U)
    1692. 

  1692. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_DISABLED            (0x00000000U)
    1693. 

  1693. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA1_ENABLED             (0x00000001U)
    1694. 

  1694. 

  1695. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_MASK                (0x00008000U)
    1696. 

  1696. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_SHIFT               (15U)
    1697. 

  1697. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_RESETVAL            (0x00000000U)
    1698. 

  1698. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_KEEP                (0x00000000U)
    1699. 

  1699. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_DISABLE             (0x00000001U)
    1700. 

  1700. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_DISABLED            (0x00000000U)
    1701. 

  1701. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS1_ENABLED             (0x00000001U)
    1702. 

  1702. 

  1703. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_MASK                    (0x00010000U)
    1704. 

  1704. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_SHIFT                   (16U)
    1705. 

  1705. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_RESETVAL                (0x00000000U)
    1706. 

  1706. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_KEEP                    (0x00000000U)
    1707. 

  1707. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_DISABLE                 (0x00000001U)
    1708. 

  1708. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_DISABLED                (0x00000000U)
    1709. 

  1709. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC2_ENABLED                 (0x00000001U)
    1710. 

  1710. 

  1711. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_MASK                    (0x00020000U)
    1712. 

  1712. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_SHIFT                   (17U)
    1713. 

  1713. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_RESETVAL                (0x00000000U)
    1714. 

  1714. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_KEEP                    (0x00000000U)
    1715. 

  1715. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_DISABLE                 (0x00000001U)
    1716. 

  1716. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_DISABLED                (0x00000000U)
    1717. 

  1717. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST2_ENABLED                 (0x00000001U)
    1718. 

  1718. 

  1719. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_MASK                 (0x00040000U)
    1720. 

  1720. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_SHIFT                (18U)
    1721. 

  1721. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_RESETVAL             (0x00000000U)
    1722. 

  1722. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_KEEP                 (0x00000000U)
    1723. 

  1723. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_DISABLE              (0x00000001U)
    1724. 

  1724. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_DISABLED             (0x00000000U)
    1725. 

  1725. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC2_ENABLED              (0x00000001U)
    1726. 

  1726. 

  1727. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_MASK                (0x00080000U)
    1728. 

  1728. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_SHIFT               (19U)
    1729. 

  1729. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_RESETVAL            (0x00000000U)
    1730. 

  1730. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_KEEP                (0x00000000U)
    1731. 

  1731. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_DISABLE             (0x00000001U)
    1732. 

  1732. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_DISABLED            (0x00000000U)
    1733. 

  1733. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA2_ENABLED             (0x00000001U)
    1734. 

  1734. 

  1735. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_MASK                (0x00100000U)
    1736. 

  1736. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_SHIFT               (20U)
    1737. 

  1737. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_RESETVAL            (0x00000000U)
    1738. 

  1738. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_KEEP                (0x00000000U)
    1739. 

  1739. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_DISABLE             (0x00000001U)
    1740. 

  1740. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_DISABLED            (0x00000000U)
    1741. 

  1741. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA2_ENABLED             (0x00000001U)
    1742. 

  1742. 

  1743. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_MASK                (0x00200000U)
    1744. 

  1744. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_SHIFT               (21U)
    1745. 

  1745. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_RESETVAL            (0x00000000U)
    1746. 

  1746. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_KEEP                (0x00000000U)
    1747. 

  1747. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_DISABLE             (0x00000001U)
    1748. 

  1748. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_DISABLED            (0x00000000U)
    1749. 

  1749. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL2_ENABLED             (0x00000001U)
    1750. 

  1750. 

  1751. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_MASK                (0x00400000U)
    1752. 

  1752. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_SHIFT               (22U)
    1753. 

  1753. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_RESETVAL            (0x00000000U)
    1754. 

  1754. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_KEEP                (0x00000000U)
    1755. 

  1755. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_DISABLE             (0x00000001U)
    1756. 

  1756. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_DISABLED            (0x00000000U)
    1757. 

  1757. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA2_ENABLED             (0x00000001U)
    1758. 

  1758. 

  1759. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_MASK                (0x00800000U)
    1760. 

  1760. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_SHIFT               (23U)
    1761. 

  1761. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_RESETVAL            (0x00000000U)
    1762. 

  1762. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_KEEP                (0x00000000U)
    1763. 

  1763. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_DISABLE             (0x00000001U)
    1764. 

  1764. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_DISABLED            (0x00000000U)
    1765. 

  1765. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS2_ENABLED             (0x00000001U)
    1766. 

  1766. 

  1767. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_MASK                    (0x01000000U)
    1768. 

  1768. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_SHIFT                   (24U)
    1769. 

  1769. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_RESETVAL                (0x00000000U)
    1770. 

  1770. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_KEEP                    (0x00000000U)
    1771. 

  1771. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_DISABLE                 (0x00000001U)
    1772. 

  1772. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_DISABLED                (0x00000000U)
    1773. 

  1773. #define CSL_DMM_PAT_IRQEN_CLR_FILL_DSC3_ENABLED                 (0x00000001U)
    1774. 

  1774. 

  1775. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_MASK                    (0x02000000U)
    1776. 

  1776. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_SHIFT                   (25U)
    1777. 

  1777. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_RESETVAL                (0x00000000U)
    1778. 

  1778. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_KEEP                    (0x00000000U)
    1779. 

  1779. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_DISABLE                 (0x00000001U)
    1780. 

  1780. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_DISABLED                (0x00000000U)
    1781. 

  1781. #define CSL_DMM_PAT_IRQEN_CLR_FILL_LST3_ENABLED                 (0x00000001U)
    1782. 

  1782. 

  1783. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_MASK                 (0x04000000U)
    1784. 

  1784. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_SHIFT                (26U)
    1785. 

  1785. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_RESETVAL             (0x00000000U)
    1786. 

  1786. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_KEEP                 (0x00000000U)
    1787. 

  1787. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_DISABLE              (0x00000001U)
    1788. 

  1788. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_DISABLED             (0x00000000U)
    1789. 

  1789. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DSC3_ENABLED              (0x00000001U)
    1790. 

  1790. 

  1791. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_MASK                (0x08000000U)
    1792. 

  1792. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_SHIFT               (27U)
    1793. 

  1793. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_RESETVAL            (0x00000000U)
    1794. 

  1794. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_KEEP                (0x00000000U)
    1795. 

  1795. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_DISABLE             (0x00000001U)
    1796. 

  1796. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_DISABLED            (0x00000000U)
    1797. 

  1797. #define CSL_DMM_PAT_IRQEN_CLR_ERR_INV_DATA3_ENABLED             (0x00000001U)
    1798. 

  1798. 

  1799. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_MASK                (0x10000000U)
    1800. 

  1800. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_SHIFT               (28U)
    1801. 

  1801. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_RESETVAL            (0x00000000U)
    1802. 

  1802. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_KEEP                (0x00000000U)
    1803. 

  1803. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_DISABLE             (0x00000001U)
    1804. 

  1804. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_DISABLED            (0x00000000U)
    1805. 

  1805. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_AREA3_ENABLED             (0x00000001U)
    1806. 

  1806. 

  1807. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_MASK                (0x20000000U)
    1808. 

  1808. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_SHIFT               (29U)
    1809. 

  1809. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_RESETVAL            (0x00000000U)
    1810. 

  1810. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_KEEP                (0x00000000U)
    1811. 

  1811. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_DISABLE             (0x00000001U)
    1812. 

  1812. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_DISABLED            (0x00000000U)
    1813. 

  1813. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_CTRL3_ENABLED             (0x00000001U)
    1814. 

  1814. 

  1815. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_MASK                (0x40000000U)
    1816. 

  1816. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_SHIFT               (30U)
    1817. 

  1817. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_RESETVAL            (0x00000000U)
    1818. 

  1818. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_KEEP                (0x00000000U)
    1819. 

  1819. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_DISABLE             (0x00000001U)
    1820. 

  1820. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_DISABLED            (0x00000000U)
    1821. 

  1821. #define CSL_DMM_PAT_IRQEN_CLR_ERR_UPD_DATA3_ENABLED             (0x00000001U)
    1822. 

  1822. 

  1823. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_MASK                (0x80000000U)
    1824. 

  1824. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_SHIFT               (31U)
    1825. 

  1825. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_RESETVAL            (0x00000000U)
    1826. 

  1826. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_KEEP                (0x00000000U)
    1827. 

  1827. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_DISABLE             (0x00000001U)
    1828. 

  1828. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_DISABLED            (0x00000000U)
    1829. 

  1829. #define CSL_DMM_PAT_IRQEN_CLR_ERR_LUT_MISS3_ENABLED             (0x00000001U)
    1830. 

  1830. 

  1831. #define CSL_DMM_PAT_IRQEN_CLR_RESETVAL                          (0x00000000U)
    1832. 

  1832. 

  1833. /* PAT_STS */
    1834. 

  1834. 

  1835. #define CSL_DMM_PAT_STS_READY_MASK                              (0x00000001U)
    1836. 

  1836. #define CSL_DMM_PAT_STS_READY_SHIFT                             (0U)
    1837. 

  1837. #define CSL_DMM_PAT_STS_READY_RESETVAL                          (0x00000001U)
    1838. 

  1838. #define CSL_DMM_PAT_STS_READY_MAX                               (0x00000001U)
    1839. 

  1839. 

  1840. #define CSL_DMM_PAT_STS_RUN_MASK                                (0x00000004U)
    1841. 

  1841. #define CSL_DMM_PAT_STS_RUN_SHIFT                               (2U)
    1842. 

  1842. #define CSL_DMM_PAT_STS_RUN_RESETVAL                            (0x00000000U)
    1843. 

  1843. #define CSL_DMM_PAT_STS_RUN_MAX                                 (0x00000001U)
    1844. 

  1844. 

  1845. #define CSL_DMM_PAT_STS_VALID_MASK                              (0x00000002U)
    1846. 

  1846. #define CSL_DMM_PAT_STS_VALID_SHIFT                             (1U)
    1847. 

  1847. #define CSL_DMM_PAT_STS_VALID_RESETVAL                          (0x00000000U)
    1848. 

  1848. #define CSL_DMM_PAT_STS_VALID_MAX                               (0x00000001U)
    1849. 

  1849. 

  1850. #define CSL_DMM_PAT_STS_CNT_MASK                                (0x01FF0000U)
    1851. 

  1851. #define CSL_DMM_PAT_STS_CNT_SHIFT                               (16U)
    1852. 

  1852. #define CSL_DMM_PAT_STS_CNT_RESETVAL                            (0x00000000U)
    1853. 

  1853. #define CSL_DMM_PAT_STS_CNT_MAX                                 (0x000001ffU)
    1854. 

  1854. 

  1855. #define CSL_DMM_PAT_STS_ERROR_MASK                              (0x0000FC00U)
    1856. 

  1856. #define CSL_DMM_PAT_STS_ERROR_SHIFT                             (10U)
    1857. 

  1857. #define CSL_DMM_PAT_STS_ERROR_RESETVAL                          (0x00000000U)
    1858. 

  1858. #define CSL_DMM_PAT_STS_ERROR_MAX                               (0x0000003fU)
    1859. 

  1859. 

  1860. #define CSL_DMM_PAT_STS_DONE_MASK                               (0x00000008U)
    1861. 

  1861. #define CSL_DMM_PAT_STS_DONE_SHIFT                              (3U)
    1862. 

  1862. #define CSL_DMM_PAT_STS_DONE_RESETVAL                           (0x00000000U)
    1863. 

  1863. #define CSL_DMM_PAT_STS_DONE_MAX                                (0x00000001U)
    1864. 

  1864. 

  1865. #define CSL_DMM_PAT_STS_LINKED_MASK                             (0x00000010U)
    1866. 

  1866. #define CSL_DMM_PAT_STS_LINKED_SHIFT                            (4U)
    1867. 

  1867. #define CSL_DMM_PAT_STS_LINKED_RESETVAL                         (0x00000000U)
    1868. 

  1868. #define CSL_DMM_PAT_STS_LINKED_MAX                              (0x00000001U)
    1869. 

  1869. 

  1870. #define CSL_DMM_PAT_STS_BYPASSED_MASK                           (0x00000080U)
    1871. 

  1871. #define CSL_DMM_PAT_STS_BYPASSED_SHIFT                          (7U)
    1872. 

  1872. #define CSL_DMM_PAT_STS_BYPASSED_RESETVAL                       (0x00000000U)
    1873. 

  1873. #define CSL_DMM_PAT_STS_BYPASSED_MAX                            (0x00000001U)
    1874. 

  1874. 

  1875. #define CSL_DMM_PAT_STS_RESETVAL                                (0x00000001U)
    1876. 

  1876. 

  1877. /* PAT_DESCR */
    1878. 

  1878. 

  1879. #define CSL_DMM_PAT_DESCR_ADDR_MASK                             (0xFFFFFFF0U)
    1880. 

  1880. #define CSL_DMM_PAT_DESCR_ADDR_SHIFT                            (4U)
    1881. 

  1881. #define CSL_DMM_PAT_DESCR_ADDR_RESETVAL                         (0x00000000U)
    1882. 

  1882. #define CSL_DMM_PAT_DESCR_ADDR_MAX                              (0x0fffffffU)
    1883. 

  1883. 

  1884. #define CSL_DMM_PAT_DESCR_RESETVAL                              (0x00000000U)
    1885. 

  1885. 

  1886. /* PAT_AREA */
    1887. 

  1887. 

  1888. #define CSL_DMM_PAT_AREA_X0_MASK                                (0x000000FFU)
    1889. 

  1889. #define CSL_DMM_PAT_AREA_X0_SHIFT                               (0U)
    1890. 

  1890. #define CSL_DMM_PAT_AREA_X0_RESETVAL                            (0x00000000U)
    1891. 

  1891. #define CSL_DMM_PAT_AREA_X0_MAX                                 (0x000000ffU)
    1892. 

  1892. 

  1893. #define CSL_DMM_PAT_AREA_Y0_MASK                                (0x0000FF00U)
    1894. 

  1894. #define CSL_DMM_PAT_AREA_Y0_SHIFT                               (8U)
    1895. 

  1895. #define CSL_DMM_PAT_AREA_Y0_RESETVAL                            (0x00000000U)
    1896. 

  1896. #define CSL_DMM_PAT_AREA_Y0_MAX                                 (0x000000ffU)
    1897. 

  1897. 

  1898. #define CSL_DMM_PAT_AREA_X1_MASK                                (0x00FF0000U)
    1899. 

  1899. #define CSL_DMM_PAT_AREA_X1_SHIFT                               (16U)
    1900. 

  1900. #define CSL_DMM_PAT_AREA_X1_RESETVAL                            (0x00000000U)
    1901. 

  1901. #define CSL_DMM_PAT_AREA_X1_MAX                                 (0x000000ffU)
    1902. 

  1902. 

  1903. #define CSL_DMM_PAT_AREA_Y1_MASK                                (0xFF000000U)
    1904. 

  1904. #define CSL_DMM_PAT_AREA_Y1_SHIFT                               (24U)
    1905. 

  1905. #define CSL_DMM_PAT_AREA_Y1_RESETVAL                            (0x00000000U)
    1906. 

  1906. #define CSL_DMM_PAT_AREA_Y1_MAX                                 (0x000000ffU)
    1907. 

  1907. 

  1908. #define CSL_DMM_PAT_AREA_RESETVAL                               (0x00000000U)
    1909. 

  1909. 

  1910. /* PAT_CTRL */
    1911. 

  1911. 

  1912. #define CSL_DMM_PAT_CTRL_START_MASK                             (0x00000001U)
    1913. 

  1913. #define CSL_DMM_PAT_CTRL_START_SHIFT                            (0U)
    1914. 

  1914. #define CSL_DMM_PAT_CTRL_START_RESETVAL                         (0x00000000U)
    1915. 

  1915. #define CSL_DMM_PAT_CTRL_START_MAX                              (0x00000001U)
    1916. 

  1916. 

  1917. #define CSL_DMM_PAT_CTRL_DIRECTION_MASK                         (0x00000070U)
    1918. 

  1918. #define CSL_DMM_PAT_CTRL_DIRECTION_SHIFT                        (4U)
    1919. 

  1919. #define CSL_DMM_PAT_CTRL_DIRECTION_RESETVAL                     (0x00000000U)
    1920. 

  1920. #define CSL_DMM_PAT_CTRL_DIRECTION_MAX                          (0x00000007U)
    1921. 

  1921. 

  1922. #define CSL_DMM_PAT_CTRL_SYNC_MASK                              (0x00010000U)
    1923. 

  1923. #define CSL_DMM_PAT_CTRL_SYNC_SHIFT                             (16U)
    1924. 

  1924. #define CSL_DMM_PAT_CTRL_SYNC_RESETVAL                          (0x00000000U)
    1925. 

  1925. #define CSL_DMM_PAT_CTRL_SYNC_OFF                               (0x00000000U)
    1926. 

  1926. #define CSL_DMM_PAT_CTRL_SYNC_ON                                (0x00000001U)
    1927. 

  1927. 

  1928. #define CSL_DMM_PAT_CTRL_INITIATOR_MASK                         (0xF0000000U)
    1929. 

  1929. #define CSL_DMM_PAT_CTRL_INITIATOR_SHIFT                        (28U)
    1930. 

  1930. #define CSL_DMM_PAT_CTRL_INITIATOR_RESETVAL                     (0x00000000U)
    1931. 

  1931. #define CSL_DMM_PAT_CTRL_INITIATOR_MAX                          (0x0000000fU)
    1932. 

  1932. 

  1933. #define CSL_DMM_PAT_CTRL_LUT_ID_MASK                            (0x00000000U)
    1934. 

  1934. #define CSL_DMM_PAT_CTRL_LUT_ID_SHIFT                           (8U)
    1935. 

  1935. #define CSL_DMM_PAT_CTRL_LUT_ID_RESETVAL                        (0x00000000U)
    1936. 

  1936. #define CSL_DMM_PAT_CTRL_LUT_ID_MAX                             (0x00000000U)
    1937. 

  1937. 

  1938. #define CSL_DMM_PAT_CTRL_RESETVAL                               (0x00000000U)
    1939. 

  1939. 

  1940. /* PAT_DATA */
    1941. 

  1941. 

  1942. #define CSL_DMM_PAT_DATA_ADDR_MASK                              (0xFFFFFFF0U)
    1943. 

  1943. #define CSL_DMM_PAT_DATA_ADDR_SHIFT                             (4U)
    1944. 

  1944. #define CSL_DMM_PAT_DATA_ADDR_RESETVAL                          (0x00000000U)
    1945. 

  1945. #define CSL_DMM_PAT_DATA_ADDR_MAX                               (0x0fffffffU)
    1946. 

  1946. 

  1947. #define CSL_DMM_PAT_DATA_RESETVAL                               (0x00000000U)
    1948. 

  1948. 

  1949. /* PEG_HWINFO */
    1950. 

  1950. 

  1951. #define CSL_DMM_PEG_HWINFO_PRIO_CNT_MASK                        (0x0000007FU)
    1952. 

  1952. #define CSL_DMM_PEG_HWINFO_PRIO_CNT_SHIFT                       (0U)
    1953. 

  1953. #define CSL_DMM_PEG_HWINFO_PRIO_CNT_RESETVAL                    (0x00000040U)
    1954. 

  1954. #define CSL_DMM_PEG_HWINFO_PRIO_CNT_MAX                         (0x0000007fU)
    1955. 

  1955. 

  1956. #define CSL_DMM_PEG_HWINFO_RESETVAL                             (0x00000040U)
    1957. 

  1957. 

  1958. /* PEG_PRIO */
    1959. 

  1959. 

  1960. #define CSL_DMM_PEG_PRIO_P0_MASK                                (0x00000007U)
    1961. 

  1961. #define CSL_DMM_PEG_PRIO_P0_SHIFT                               (0U)
    1962. 

  1962. #define CSL_DMM_PEG_PRIO_P0_RESETVAL                            (0x00000004U)
    1963. 

  1963. #define CSL_DMM_PEG_PRIO_P0_MAX                                 (0x00000007U)
    1964. 

  1964. 

  1965. #define CSL_DMM_PEG_PRIO_W0_MASK                                (0x00000008U)
    1966. 

  1966. #define CSL_DMM_PEG_PRIO_W0_SHIFT                               (3U)
    1967. 

  1967. #define CSL_DMM_PEG_PRIO_W0_RESETVAL                            (0x00000000U)
    1968. 

  1968. #define CSL_DMM_PEG_PRIO_W0_UPDATE                              (0x00000001U)
    1969. 

  1969. #define CSL_DMM_PEG_PRIO_W0_KEEP                                (0x00000000U)
    1970. 

  1970. 

  1971. #define CSL_DMM_PEG_PRIO_P1_MASK                                (0x00000070U)
    1972. 

  1972. #define CSL_DMM_PEG_PRIO_P1_SHIFT                               (4U)
    1973. 

  1973. #define CSL_DMM_PEG_PRIO_P1_RESETVAL                            (0x00000004U)
    1974. 

  1974. #define CSL_DMM_PEG_PRIO_P1_MAX                                 (0x00000007U)
    1975. 

  1975. 

  1976. #define CSL_DMM_PEG_PRIO_W1_MASK                                (0x00000080U)
    1977. 

  1977. #define CSL_DMM_PEG_PRIO_W1_SHIFT                               (7U)
    1978. 

  1978. #define CSL_DMM_PEG_PRIO_W1_RESETVAL                            (0x00000000U)
    1979. 

  1979. #define CSL_DMM_PEG_PRIO_W1_UPDATE                              (0x00000001U)
    1980. 

  1980. #define CSL_DMM_PEG_PRIO_W1_KEEP                                (0x00000000U)
    1981. 

  1981. 

  1982. #define CSL_DMM_PEG_PRIO_P2_MASK                                (0x00000700U)
    1983. 

  1983. #define CSL_DMM_PEG_PRIO_P2_SHIFT                               (8U)
    1984. 

  1984. #define CSL_DMM_PEG_PRIO_P2_RESETVAL                            (0x00000004U)
    1985. 

  1985. #define CSL_DMM_PEG_PRIO_P2_MAX                                 (0x00000007U)
    1986. 

  1986. 

  1987. #define CSL_DMM_PEG_PRIO_W2_MASK                                (0x00000800U)
    1988. 

  1988. #define CSL_DMM_PEG_PRIO_W2_SHIFT                               (11U)
    1989. 

  1989. #define CSL_DMM_PEG_PRIO_W2_RESETVAL                            (0x00000000U)
    1990. 

  1990. #define CSL_DMM_PEG_PRIO_W2_UPDATE                              (0x00000001U)
    1991. 

  1991. #define CSL_DMM_PEG_PRIO_W2_KEEP                                (0x00000000U)
    1992. 

  1992. 

  1993. #define CSL_DMM_PEG_PRIO_P3_MASK                                (0x00007000U)
    1994. 

  1994. #define CSL_DMM_PEG_PRIO_P3_SHIFT                               (12U)
    1995. 

  1995. #define CSL_DMM_PEG_PRIO_P3_RESETVAL                            (0x00000004U)
    1996. 

  1996. #define CSL_DMM_PEG_PRIO_P3_MAX                                 (0x00000007U)
    1997. 

  1997. 

  1998. #define CSL_DMM_PEG_PRIO_W3_MASK                                (0x00008000U)
    1999. 

  1999. #define CSL_DMM_PEG_PRIO_W3_SHIFT                               (15U)
    2000. 

  2000. #define CSL_DMM_PEG_PRIO_W3_RESETVAL                            (0x00000000U)
    2001. 

  2001. #define CSL_DMM_PEG_PRIO_W3_UPDATE                              (0x00000001U)
    2002. 

  2002. #define CSL_DMM_PEG_PRIO_W3_KEEP                                (0x00000000U)
    2003. 

  2003. 

  2004. #define CSL_DMM_PEG_PRIO_P4_MASK                                (0x00070000U)
    2005. 

  2005. #define CSL_DMM_PEG_PRIO_P4_SHIFT                               (16U)
    2006. 

  2006. #define CSL_DMM_PEG_PRIO_P4_RESETVAL                            (0x00000004U)
    2007. 

  2007. #define CSL_DMM_PEG_PRIO_P4_MAX                                 (0x00000007U)
    2008. 

  2008. 

  2009. #define CSL_DMM_PEG_PRIO_W4_MASK                                (0x00080000U)
    2010. 

  2010. #define CSL_DMM_PEG_PRIO_W4_SHIFT                               (19U)
    2011. 

  2011. #define CSL_DMM_PEG_PRIO_W4_RESETVAL                            (0x00000000U)
    2012. 

  2012. #define CSL_DMM_PEG_PRIO_W4_UPDATE                              (0x00000001U)
    2013. 

  2013. #define CSL_DMM_PEG_PRIO_W4_KEEP                                (0x00000000U)
    2014. 

  2014. 

  2015. #define CSL_DMM_PEG_PRIO_P5_MASK                                (0x00700000U)
    2016. 

  2016. #define CSL_DMM_PEG_PRIO_P5_SHIFT                               (20U)
    2017. 

  2017. #define CSL_DMM_PEG_PRIO_P5_RESETVAL                            (0x00000004U)
    2018. 

  2018. #define CSL_DMM_PEG_PRIO_P5_MAX                                 (0x00000007U)
    2019. 

  2019. 

  2020. #define CSL_DMM_PEG_PRIO_W5_MASK                                (0x00800000U)
    2021. 

  2021. #define CSL_DMM_PEG_PRIO_W5_SHIFT                               (23U)
    2022. 

  2022. #define CSL_DMM_PEG_PRIO_W5_RESETVAL                            (0x00000000U)
    2023. 

  2023. #define CSL_DMM_PEG_PRIO_W5_UPDATE                              (0x00000001U)
    2024. 

  2024. #define CSL_DMM_PEG_PRIO_W5_KEEP                                (0x00000000U)
    2025. 

  2025. 

  2026. #define CSL_DMM_PEG_PRIO_P6_MASK                                (0x07000000U)
    2027. 

  2027. #define CSL_DMM_PEG_PRIO_P6_SHIFT                               (24U)
    2028. 

  2028. #define CSL_DMM_PEG_PRIO_P6_RESETVAL                            (0x00000004U)
    2029. 

  2029. #define CSL_DMM_PEG_PRIO_P6_MAX                                 (0x00000007U)
    2030. 

  2030. 

  2031. #define CSL_DMM_PEG_PRIO_W6_MASK                                (0x08000000U)
    2032. 

  2032. #define CSL_DMM_PEG_PRIO_W6_SHIFT                               (27U)
    2033. 

  2033. #define CSL_DMM_PEG_PRIO_W6_RESETVAL                            (0x00000000U)
    2034. 

  2034. #define CSL_DMM_PEG_PRIO_W6_UPDATE                              (0x00000001U)
    2035. 

  2035. #define CSL_DMM_PEG_PRIO_W6_KEEP                                (0x00000000U)
    2036. 

  2036. 

  2037. #define CSL_DMM_PEG_PRIO_P7_MASK                                (0x70000000U)
    2038. 

  2038. #define CSL_DMM_PEG_PRIO_P7_SHIFT                               (28U)
    2039. 

  2039. #define CSL_DMM_PEG_PRIO_P7_RESETVAL                            (0x00000004U)
    2040. 

  2040. #define CSL_DMM_PEG_PRIO_P7_MAX                                 (0x00000007U)
    2041. 

  2041. 

  2042. #define CSL_DMM_PEG_PRIO_W7_MASK                                (0x80000000U)
    2043. 

  2043. #define CSL_DMM_PEG_PRIO_W7_SHIFT                               (31U)
    2044. 

  2044. #define CSL_DMM_PEG_PRIO_W7_RESETVAL                            (0x00000000U)
    2045. 

  2045. #define CSL_DMM_PEG_PRIO_W7_UPDATE                              (0x00000001U)
    2046. 

  2046. #define CSL_DMM_PEG_PRIO_W7_KEEP                                (0x00000000U)
    2047. 

  2047. 

  2048. #define CSL_DMM_PEG_PRIO_RESETVAL                               (0x44444444U)
    2049. 

  2049. 

  2050. /* PEG_PRIO_PAT */
    2051. 

  2051. 

  2052. #define CSL_DMM_PEG_PRIO_PAT_P_PAT_MASK                         (0x00000007U)
    2053. 

  2053. #define CSL_DMM_PEG_PRIO_PAT_P_PAT_SHIFT                        (0U)
    2054. 

  2054. #define CSL_DMM_PEG_PRIO_PAT_P_PAT_RESETVAL                     (0x00000004U)
    2055. 

  2055. #define CSL_DMM_PEG_PRIO_PAT_P_PAT_MAX                          (0x00000007U)
    2056. 

  2056. 

  2057. #define CSL_DMM_PEG_PRIO_PAT_W_PAT_MASK                         (0x00000008U)
    2058. 

  2058. #define CSL_DMM_PEG_PRIO_PAT_W_PAT_SHIFT                        (3U)
    2059. 

  2059. #define CSL_DMM_PEG_PRIO_PAT_W_PAT_RESETVAL                     (0x00000000U)
    2060. 

  2060. #define CSL_DMM_PEG_PRIO_PAT_W_PAT_UPDATE                       (0x00000000U)
    2061. 

  2061. #define CSL_DMM_PEG_PRIO_PAT_W_PAT_KEEP                         (0x00000001U)
    2062. 

  2062. 

  2063. #define CSL_DMM_PEG_PRIO_PAT_RESETVAL                           (0x00000004U)
    2064. 

  2064. 

  2065. #ifdef __cplusplus
    2066. 

  2066. }
    2067. 

  2067. #endif
    2068. 

  2068. #endif
    2069.