spartan3.h 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135
  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef _SPARTAN3_H_
  8. #define _SPARTAN3_H_
  9. #include <xilinx.h>
  10. /* Slave Parallel Implementation function table */
  11. typedef struct {
  12. xilinx_pre_fn pre;
  13. xilinx_pgm_fn pgm;
  14. xilinx_init_fn init;
  15. xilinx_err_fn err;
  16. xilinx_done_fn done;
  17. xilinx_clk_fn clk;
  18. xilinx_cs_fn cs;
  19. xilinx_wr_fn wr;
  20. xilinx_rdata_fn rdata;
  21. xilinx_wdata_fn wdata;
  22. xilinx_busy_fn busy;
  23. xilinx_abort_fn abort;
  24. xilinx_post_fn post;
  25. } xilinx_spartan3_slave_parallel_fns;
  26. /* Slave Serial Implementation function table */
  27. typedef struct {
  28. xilinx_pre_fn pre;
  29. xilinx_pgm_fn pgm;
  30. xilinx_clk_fn clk;
  31. xilinx_init_fn init;
  32. xilinx_done_fn done;
  33. xilinx_wr_fn wr;
  34. xilinx_post_fn post;
  35. xilinx_bwr_fn bwr; /* block write function */
  36. xilinx_abort_fn abort;
  37. } xilinx_spartan3_slave_serial_fns;
  38. #if defined(CONFIG_FPGA_SPARTAN3)
  39. extern struct xilinx_fpga_op spartan3_op;
  40. # define FPGA_SPARTAN3_OPS &spartan3_op
  41. #else
  42. # define FPGA_SPARTAN3_OPS NULL
  43. #endif
  44. /* Device Image Sizes
  45. *********************************************************************/
  46. /* Spartan-III (1.2V) */
  47. #define XILINX_XC3S50_SIZE 439264/8
  48. #define XILINX_XC3S200_SIZE 1047616/8
  49. #define XILINX_XC3S400_SIZE 1699136/8
  50. #define XILINX_XC3S1000_SIZE 3223488/8
  51. #define XILINX_XC3S1500_SIZE 5214784/8
  52. #define XILINX_XC3S2000_SIZE 7673024/8
  53. #define XILINX_XC3S4000_SIZE 11316864/8
  54. #define XILINX_XC3S5000_SIZE 13271936/8
  55. /* Spartan-3E (v3.4) */
  56. #define XILINX_XC3S100E_SIZE 581344/8
  57. #define XILINX_XC3S250E_SIZE 1353728/8
  58. #define XILINX_XC3S500E_SIZE 2270208/8
  59. #define XILINX_XC3S1200E_SIZE 3841184/8
  60. #define XILINX_XC3S1600E_SIZE 5969696/8
  61. /*
  62. * Spartan-6 : the Spartan-6 family can be programmed
  63. * exactly as the Spartan-3
  64. */
  65. #define XILINK_XC6SLX4_SIZE (3713568/8)
  66. /* Descriptor Macros
  67. *********************************************************************/
  68. /* Spartan-III devices */
  69. #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
  70. { xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
  71. FPGA_SPARTAN3_OPS }
  72. #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
  73. { xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
  74. FPGA_SPARTAN3_OPS }
  75. #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
  76. { xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
  77. FPGA_SPARTAN3_OPS }
  78. #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
  79. { xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
  80. FPGA_SPARTAN3_OPS }
  81. #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
  82. { xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
  83. FPGA_SPARTAN3_OPS }
  84. #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
  85. { xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
  86. FPGA_SPARTAN3_OPS }
  87. #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
  88. { xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
  89. FPGA_SPARTAN3_OPS }
  90. #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
  91. { xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
  92. FPGA_SPARTAN3_OPS }
  93. /* Spartan-3E devices */
  94. #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
  95. { xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
  96. FPGA_SPARTAN3_OPS }
  97. #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
  98. { xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
  99. FPGA_SPARTAN3_OPS }
  100. #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
  101. { xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
  102. FPGA_SPARTAN3_OPS }
  103. #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
  104. { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
  105. FPGA_SPARTAN3_OPS }
  106. #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
  107. { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
  108. FPGA_SPARTAN3_OPS }
  109. #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
  110. { xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
  111. FPGA_SPARTAN3_OPS }
  112. #endif /* _SPARTAN3_H_ */