nand.h 35 KB

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  1. /*
  2. * linux/include/linux/mtd/nand.h
  3. *
  4. * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  5. * Steven J. Hill <sjhill@realitydiluted.com>
  6. * Thomas Gleixner <tglx@linutronix.de>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. *
  10. * Info:
  11. * Contains standard defines and IDs for NAND flash devices
  12. *
  13. * Changelog:
  14. * See git changelog.
  15. */
  16. #ifndef __LINUX_MTD_NAND_H
  17. #define __LINUX_MTD_NAND_H
  18. #include <config.h>
  19. #include <linux/compat.h>
  20. #include <linux/mtd/mtd.h>
  21. #include <linux/mtd/flashchip.h>
  22. #include <linux/mtd/bbm.h>
  23. struct mtd_info;
  24. struct nand_flash_dev;
  25. struct device_node;
  26. /* Scan and identify a NAND device */
  27. extern int nand_scan(struct mtd_info *mtd, int max_chips);
  28. /*
  29. * Separate phases of nand_scan(), allowing board driver to intervene
  30. * and override command or ECC setup according to flash type.
  31. */
  32. extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  33. struct nand_flash_dev *table);
  34. extern int nand_scan_tail(struct mtd_info *mtd);
  35. /* Free resources held by the NAND device */
  36. extern void nand_release(struct mtd_info *mtd);
  37. /* Internal helper for board drivers which need to override command function */
  38. extern void nand_wait_ready(struct mtd_info *mtd);
  39. /*
  40. * This constant declares the max. oobsize / page, which
  41. * is supported now. If you add a chip with bigger oobsize/page
  42. * adjust this accordingly.
  43. */
  44. #define NAND_MAX_OOBSIZE 1664
  45. #define NAND_MAX_PAGESIZE 16384
  46. /*
  47. * Constants for hardware specific CLE/ALE/NCE function
  48. *
  49. * These are bits which can be or'ed to set/clear multiple
  50. * bits in one go.
  51. */
  52. /* Select the chip by setting nCE to low */
  53. #define NAND_NCE 0x01
  54. /* Select the command latch by setting CLE to high */
  55. #define NAND_CLE 0x02
  56. /* Select the address latch by setting ALE to high */
  57. #define NAND_ALE 0x04
  58. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  59. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  60. #define NAND_CTRL_CHANGE 0x80
  61. /*
  62. * Standard NAND flash commands
  63. */
  64. #define NAND_CMD_READ0 0
  65. #define NAND_CMD_READ1 1
  66. #define NAND_CMD_RNDOUT 5
  67. #define NAND_CMD_PAGEPROG 0x10
  68. #define NAND_CMD_READOOB 0x50
  69. #define NAND_CMD_ERASE1 0x60
  70. #define NAND_CMD_STATUS 0x70
  71. #define NAND_CMD_SEQIN 0x80
  72. #define NAND_CMD_RNDIN 0x85
  73. #define NAND_CMD_READID 0x90
  74. #define NAND_CMD_ERASE2 0xd0
  75. #define NAND_CMD_PARAM 0xec
  76. #define NAND_CMD_GET_FEATURES 0xee
  77. #define NAND_CMD_SET_FEATURES 0xef
  78. #define NAND_CMD_RESET 0xff
  79. #define NAND_CMD_LOCK 0x2a
  80. #define NAND_CMD_UNLOCK1 0x23
  81. #define NAND_CMD_UNLOCK2 0x24
  82. /* Extended commands for large page devices */
  83. #define NAND_CMD_READSTART 0x30
  84. #define NAND_CMD_RNDOUTSTART 0xE0
  85. #define NAND_CMD_CACHEDPROG 0x15
  86. /* Extended commands for AG-AND device */
  87. /*
  88. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  89. * there is no way to distinguish that from NAND_CMD_READ0
  90. * until the remaining sequence of commands has been completed
  91. * so add a high order bit and mask it off in the command.
  92. */
  93. #define NAND_CMD_DEPLETE1 0x100
  94. #define NAND_CMD_DEPLETE2 0x38
  95. #define NAND_CMD_STATUS_MULTI 0x71
  96. #define NAND_CMD_STATUS_ERROR 0x72
  97. /* multi-bank error status (banks 0-3) */
  98. #define NAND_CMD_STATUS_ERROR0 0x73
  99. #define NAND_CMD_STATUS_ERROR1 0x74
  100. #define NAND_CMD_STATUS_ERROR2 0x75
  101. #define NAND_CMD_STATUS_ERROR3 0x76
  102. #define NAND_CMD_STATUS_RESET 0x7f
  103. #define NAND_CMD_STATUS_CLEAR 0xff
  104. #define NAND_CMD_NONE -1
  105. /* Status bits */
  106. #define NAND_STATUS_FAIL 0x01
  107. #define NAND_STATUS_FAIL_N1 0x02
  108. #define NAND_STATUS_TRUE_READY 0x20
  109. #define NAND_STATUS_READY 0x40
  110. #define NAND_STATUS_WP 0x80
  111. /*
  112. * Constants for ECC_MODES
  113. */
  114. typedef enum {
  115. NAND_ECC_NONE,
  116. NAND_ECC_SOFT,
  117. NAND_ECC_HW,
  118. NAND_ECC_HW_SYNDROME,
  119. NAND_ECC_HW_OOB_FIRST,
  120. NAND_ECC_SOFT_BCH,
  121. } nand_ecc_modes_t;
  122. /*
  123. * Constants for Hardware ECC
  124. */
  125. /* Reset Hardware ECC for read */
  126. #define NAND_ECC_READ 0
  127. /* Reset Hardware ECC for write */
  128. #define NAND_ECC_WRITE 1
  129. /* Enable Hardware ECC before syndrome is read back from flash */
  130. #define NAND_ECC_READSYN 2
  131. /*
  132. * Enable generic NAND 'page erased' check. This check is only done when
  133. * ecc.correct() returns -EBADMSG.
  134. * Set this flag if your implementation does not fix bitflips in erased
  135. * pages and you want to rely on the default implementation.
  136. */
  137. #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
  138. /* Bit mask for flags passed to do_nand_read_ecc */
  139. #define NAND_GET_DEVICE 0x80
  140. /*
  141. * Option constants for bizarre disfunctionality and real
  142. * features.
  143. */
  144. /* Buswidth is 16 bit */
  145. #define NAND_BUSWIDTH_16 0x00000002
  146. /* Device supports partial programming without padding */
  147. #define NAND_NO_PADDING 0x00000004
  148. /* Chip has cache program function */
  149. #define NAND_CACHEPRG 0x00000008
  150. /* Chip has copy back function */
  151. #define NAND_COPYBACK 0x00000010
  152. /*
  153. * Chip requires ready check on read (for auto-incremented sequential read).
  154. * True only for small page devices; large page devices do not support
  155. * autoincrement.
  156. */
  157. #define NAND_NEED_READRDY 0x00000100
  158. /* Chip does not allow subpage writes */
  159. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  160. /* Device is one of 'new' xD cards that expose fake nand command set */
  161. #define NAND_BROKEN_XD 0x00000400
  162. /* Device behaves just like nand, but is readonly */
  163. #define NAND_ROM 0x00000800
  164. /* Device supports subpage reads */
  165. #define NAND_SUBPAGE_READ 0x00001000
  166. /*
  167. * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
  168. * patterns.
  169. */
  170. #define NAND_NEED_SCRAMBLING 0x00002000
  171. /* Options valid for Samsung large page devices */
  172. #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
  173. /* Macros to identify the above */
  174. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  175. #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
  176. /* Non chip related options */
  177. /* This option skips the bbt scan during initialization. */
  178. #define NAND_SKIP_BBTSCAN 0x00010000
  179. /*
  180. * This option is defined if the board driver allocates its own buffers
  181. * (e.g. because it needs them DMA-coherent).
  182. */
  183. #define NAND_OWN_BUFFERS 0x00020000
  184. /* Chip may not exist, so silence any errors in scan */
  185. #define NAND_SCAN_SILENT_NODEV 0x00040000
  186. /*
  187. * Autodetect nand buswidth with readid/onfi.
  188. * This suppose the driver will configure the hardware in 8 bits mode
  189. * when calling nand_scan_ident, and update its configuration
  190. * before calling nand_scan_tail.
  191. */
  192. #define NAND_BUSWIDTH_AUTO 0x00080000
  193. /*
  194. * This option could be defined by controller drivers to protect against
  195. * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
  196. */
  197. #define NAND_USE_BOUNCE_BUFFER 0x00100000
  198. /* Options set by nand scan */
  199. /* bbt has already been read */
  200. #define NAND_BBT_SCANNED 0x40000000
  201. /* Nand scan has allocated controller struct */
  202. #define NAND_CONTROLLER_ALLOC 0x80000000
  203. /* Cell info constants */
  204. #define NAND_CI_CHIPNR_MSK 0x03
  205. #define NAND_CI_CELLTYPE_MSK 0x0C
  206. #define NAND_CI_CELLTYPE_SHIFT 2
  207. /* Keep gcc happy */
  208. struct nand_chip;
  209. /* ONFI features */
  210. #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
  211. #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
  212. /* ONFI timing mode, used in both asynchronous and synchronous mode */
  213. #define ONFI_TIMING_MODE_0 (1 << 0)
  214. #define ONFI_TIMING_MODE_1 (1 << 1)
  215. #define ONFI_TIMING_MODE_2 (1 << 2)
  216. #define ONFI_TIMING_MODE_3 (1 << 3)
  217. #define ONFI_TIMING_MODE_4 (1 << 4)
  218. #define ONFI_TIMING_MODE_5 (1 << 5)
  219. #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
  220. /* ONFI feature address */
  221. #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
  222. /* Vendor-specific feature address (Micron) */
  223. #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
  224. /* ONFI subfeature parameters length */
  225. #define ONFI_SUBFEATURE_PARAM_LEN 4
  226. /* ONFI optional commands SET/GET FEATURES supported? */
  227. #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
  228. struct nand_onfi_params {
  229. /* rev info and features block */
  230. /* 'O' 'N' 'F' 'I' */
  231. u8 sig[4];
  232. __le16 revision;
  233. __le16 features;
  234. __le16 opt_cmd;
  235. u8 reserved0[2];
  236. __le16 ext_param_page_length; /* since ONFI 2.1 */
  237. u8 num_of_param_pages; /* since ONFI 2.1 */
  238. u8 reserved1[17];
  239. /* manufacturer information block */
  240. char manufacturer[12];
  241. char model[20];
  242. u8 jedec_id;
  243. __le16 date_code;
  244. u8 reserved2[13];
  245. /* memory organization block */
  246. __le32 byte_per_page;
  247. __le16 spare_bytes_per_page;
  248. __le32 data_bytes_per_ppage;
  249. __le16 spare_bytes_per_ppage;
  250. __le32 pages_per_block;
  251. __le32 blocks_per_lun;
  252. u8 lun_count;
  253. u8 addr_cycles;
  254. u8 bits_per_cell;
  255. __le16 bb_per_lun;
  256. __le16 block_endurance;
  257. u8 guaranteed_good_blocks;
  258. __le16 guaranteed_block_endurance;
  259. u8 programs_per_page;
  260. u8 ppage_attr;
  261. u8 ecc_bits;
  262. u8 interleaved_bits;
  263. u8 interleaved_ops;
  264. u8 reserved3[13];
  265. /* electrical parameter block */
  266. u8 io_pin_capacitance_max;
  267. __le16 async_timing_mode;
  268. __le16 program_cache_timing_mode;
  269. __le16 t_prog;
  270. __le16 t_bers;
  271. __le16 t_r;
  272. __le16 t_ccs;
  273. __le16 src_sync_timing_mode;
  274. u8 src_ssync_features;
  275. __le16 clk_pin_capacitance_typ;
  276. __le16 io_pin_capacitance_typ;
  277. __le16 input_pin_capacitance_typ;
  278. u8 input_pin_capacitance_max;
  279. u8 driver_strength_support;
  280. __le16 t_int_r;
  281. __le16 t_adl;
  282. u8 reserved4[8];
  283. /* vendor */
  284. __le16 vendor_revision;
  285. u8 vendor[88];
  286. __le16 crc;
  287. } __packed;
  288. #define ONFI_CRC_BASE 0x4F4E
  289. /* Extended ECC information Block Definition (since ONFI 2.1) */
  290. struct onfi_ext_ecc_info {
  291. u8 ecc_bits;
  292. u8 codeword_size;
  293. __le16 bb_per_lun;
  294. __le16 block_endurance;
  295. u8 reserved[2];
  296. } __packed;
  297. #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
  298. #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
  299. #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
  300. struct onfi_ext_section {
  301. u8 type;
  302. u8 length;
  303. } __packed;
  304. #define ONFI_EXT_SECTION_MAX 8
  305. /* Extended Parameter Page Definition (since ONFI 2.1) */
  306. struct onfi_ext_param_page {
  307. __le16 crc;
  308. u8 sig[4]; /* 'E' 'P' 'P' 'S' */
  309. u8 reserved0[10];
  310. struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
  311. /*
  312. * The actual size of the Extended Parameter Page is in
  313. * @ext_param_page_length of nand_onfi_params{}.
  314. * The following are the variable length sections.
  315. * So we do not add any fields below. Please see the ONFI spec.
  316. */
  317. } __packed;
  318. struct nand_onfi_vendor_micron {
  319. u8 two_plane_read;
  320. u8 read_cache;
  321. u8 read_unique_id;
  322. u8 dq_imped;
  323. u8 dq_imped_num_settings;
  324. u8 dq_imped_feat_addr;
  325. u8 rb_pulldown_strength;
  326. u8 rb_pulldown_strength_feat_addr;
  327. u8 rb_pulldown_strength_num_settings;
  328. u8 otp_mode;
  329. u8 otp_page_start;
  330. u8 otp_data_prot_addr;
  331. u8 otp_num_pages;
  332. u8 otp_feat_addr;
  333. u8 read_retry_options;
  334. u8 reserved[72];
  335. u8 param_revision;
  336. } __packed;
  337. struct jedec_ecc_info {
  338. u8 ecc_bits;
  339. u8 codeword_size;
  340. __le16 bb_per_lun;
  341. __le16 block_endurance;
  342. u8 reserved[2];
  343. } __packed;
  344. /* JEDEC features */
  345. #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
  346. struct nand_jedec_params {
  347. /* rev info and features block */
  348. /* 'J' 'E' 'S' 'D' */
  349. u8 sig[4];
  350. __le16 revision;
  351. __le16 features;
  352. u8 opt_cmd[3];
  353. __le16 sec_cmd;
  354. u8 num_of_param_pages;
  355. u8 reserved0[18];
  356. /* manufacturer information block */
  357. char manufacturer[12];
  358. char model[20];
  359. u8 jedec_id[6];
  360. u8 reserved1[10];
  361. /* memory organization block */
  362. __le32 byte_per_page;
  363. __le16 spare_bytes_per_page;
  364. u8 reserved2[6];
  365. __le32 pages_per_block;
  366. __le32 blocks_per_lun;
  367. u8 lun_count;
  368. u8 addr_cycles;
  369. u8 bits_per_cell;
  370. u8 programs_per_page;
  371. u8 multi_plane_addr;
  372. u8 multi_plane_op_attr;
  373. u8 reserved3[38];
  374. /* electrical parameter block */
  375. __le16 async_sdr_speed_grade;
  376. __le16 toggle_ddr_speed_grade;
  377. __le16 sync_ddr_speed_grade;
  378. u8 async_sdr_features;
  379. u8 toggle_ddr_features;
  380. u8 sync_ddr_features;
  381. __le16 t_prog;
  382. __le16 t_bers;
  383. __le16 t_r;
  384. __le16 t_r_multi_plane;
  385. __le16 t_ccs;
  386. __le16 io_pin_capacitance_typ;
  387. __le16 input_pin_capacitance_typ;
  388. __le16 clk_pin_capacitance_typ;
  389. u8 driver_strength_support;
  390. __le16 t_adl;
  391. u8 reserved4[36];
  392. /* ECC and endurance block */
  393. u8 guaranteed_good_blocks;
  394. __le16 guaranteed_block_endurance;
  395. struct jedec_ecc_info ecc_info[4];
  396. u8 reserved5[29];
  397. /* reserved */
  398. u8 reserved6[148];
  399. /* vendor */
  400. __le16 vendor_rev_num;
  401. u8 reserved7[88];
  402. /* CRC for Parameter Page */
  403. __le16 crc;
  404. } __packed;
  405. /**
  406. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  407. * @lock: protection lock
  408. * @active: the mtd device which holds the controller currently
  409. * @wq: wait queue to sleep on if a NAND operation is in
  410. * progress used instead of the per chip wait queue
  411. * when a hw controller is available.
  412. */
  413. struct nand_hw_control {
  414. spinlock_t lock;
  415. struct nand_chip *active;
  416. };
  417. /**
  418. * struct nand_ecc_ctrl - Control structure for ECC
  419. * @mode: ECC mode
  420. * @steps: number of ECC steps per page
  421. * @size: data bytes per ECC step
  422. * @bytes: ECC bytes per step
  423. * @strength: max number of correctible bits per ECC step
  424. * @total: total number of ECC bytes per page
  425. * @prepad: padding information for syndrome based ECC generators
  426. * @postpad: padding information for syndrome based ECC generators
  427. * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
  428. * @layout: ECC layout control struct pointer
  429. * @priv: pointer to private ECC control data
  430. * @hwctl: function to control hardware ECC generator. Must only
  431. * be provided if an hardware ECC is available
  432. * @calculate: function for ECC calculation or readback from ECC hardware
  433. * @correct: function for ECC correction, matching to ECC generator (sw/hw).
  434. * Should return a positive number representing the number of
  435. * corrected bitflips, -EBADMSG if the number of bitflips exceed
  436. * ECC strength, or any other error code if the error is not
  437. * directly related to correction.
  438. * If -EBADMSG is returned the input buffers should be left
  439. * untouched.
  440. * @read_page_raw: function to read a raw page without ECC. This function
  441. * should hide the specific layout used by the ECC
  442. * controller and always return contiguous in-band and
  443. * out-of-band data even if they're not stored
  444. * contiguously on the NAND chip (e.g.
  445. * NAND_ECC_HW_SYNDROME interleaves in-band and
  446. * out-of-band data).
  447. * @write_page_raw: function to write a raw page without ECC. This function
  448. * should hide the specific layout used by the ECC
  449. * controller and consider the passed data as contiguous
  450. * in-band and out-of-band data. ECC controller is
  451. * responsible for doing the appropriate transformations
  452. * to adapt to its specific layout (e.g.
  453. * NAND_ECC_HW_SYNDROME interleaves in-band and
  454. * out-of-band data).
  455. * @read_page: function to read a page according to the ECC generator
  456. * requirements; returns maximum number of bitflips corrected in
  457. * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  458. * @read_subpage: function to read parts of the page covered by ECC;
  459. * returns same as read_page()
  460. * @write_subpage: function to write parts of the page covered by ECC.
  461. * @write_page: function to write a page according to the ECC generator
  462. * requirements.
  463. * @write_oob_raw: function to write chip OOB data without ECC
  464. * @read_oob_raw: function to read chip OOB data without ECC
  465. * @read_oob: function to read chip OOB data
  466. * @write_oob: function to write chip OOB data
  467. */
  468. struct nand_ecc_ctrl {
  469. nand_ecc_modes_t mode;
  470. int steps;
  471. int size;
  472. int bytes;
  473. int total;
  474. int strength;
  475. int prepad;
  476. int postpad;
  477. unsigned int options;
  478. struct nand_ecclayout *layout;
  479. void *priv;
  480. void (*hwctl)(struct mtd_info *mtd, int mode);
  481. int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
  482. uint8_t *ecc_code);
  483. int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
  484. uint8_t *calc_ecc);
  485. int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  486. uint8_t *buf, int oob_required, int page);
  487. int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  488. const uint8_t *buf, int oob_required, int page);
  489. int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
  490. uint8_t *buf, int oob_required, int page);
  491. int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  492. uint32_t offs, uint32_t len, uint8_t *buf, int page);
  493. int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  494. uint32_t offset, uint32_t data_len,
  495. const uint8_t *data_buf, int oob_required, int page);
  496. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  497. const uint8_t *buf, int oob_required, int page);
  498. int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  499. int page);
  500. int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  501. int page);
  502. int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
  503. int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
  504. int page);
  505. };
  506. /**
  507. * struct nand_buffers - buffer structure for read/write
  508. * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
  509. * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
  510. * @databuf: buffer pointer for data, size is (page size + oobsize).
  511. *
  512. * Do not change the order of buffers. databuf and oobrbuf must be in
  513. * consecutive order.
  514. */
  515. struct nand_buffers {
  516. uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  517. uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  518. uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
  519. ARCH_DMA_MINALIGN)];
  520. };
  521. /**
  522. * struct nand_chip - NAND Private Flash Chip Data
  523. * @mtd: MTD device registered to the MTD framework
  524. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
  525. * flash device
  526. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
  527. * flash device.
  528. * @flash_node: [BOARDSPECIFIC] device node describing this instance
  529. * @read_byte: [REPLACEABLE] read one byte from the chip
  530. * @read_word: [REPLACEABLE] read one word from the chip
  531. * @write_byte: [REPLACEABLE] write a single byte to the chip on the
  532. * low 8 I/O lines
  533. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  534. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  535. * @select_chip: [REPLACEABLE] select chip nr
  536. * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
  537. * @block_markbad: [REPLACEABLE] mark a block bad
  538. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
  539. * ALE/CLE/nCE. Also used to write command and address
  540. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
  541. * device ready/busy line. If set to NULL no access to
  542. * ready/busy is available and the ready/busy information
  543. * is read from the chip status register.
  544. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
  545. * commands to the chip.
  546. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
  547. * ready.
  548. * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
  549. * setting the read-retry mode. Mostly needed for MLC NAND.
  550. * @ecc: [BOARDSPECIFIC] ECC control structure
  551. * @buffers: buffer structure for read/write
  552. * @hwcontrol: platform-specific hardware control structure
  553. * @erase: [REPLACEABLE] erase function
  554. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  555. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
  556. * data from array to read regs (tR).
  557. * @state: [INTERN] the current state of the NAND device
  558. * @oob_poi: "poison value buffer," used for laying out OOB data
  559. * before writing
  560. * @page_shift: [INTERN] number of address bits in a page (column
  561. * address bits).
  562. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  563. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  564. * @chip_shift: [INTERN] number of address bits in one chip
  565. * @options: [BOARDSPECIFIC] various chip options. They can partly
  566. * be set to inform nand_scan about special functionality.
  567. * See the defines for further explanation.
  568. * @bbt_options: [INTERN] bad block specific options. All options used
  569. * here must come from bbm.h. By default, these options
  570. * will be copied to the appropriate nand_bbt_descr's.
  571. * @badblockpos: [INTERN] position of the bad block marker in the oob
  572. * area.
  573. * @badblockbits: [INTERN] minimum number of set bits in a good block's
  574. * bad block marker position; i.e., BBM == 11110111b is
  575. * not bad when badblockbits == 7
  576. * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
  577. * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
  578. * Minimum amount of bit errors per @ecc_step_ds guaranteed
  579. * to be correctable. If unknown, set to zero.
  580. * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
  581. * also from the datasheet. It is the recommended ECC step
  582. * size, if known; if unknown, set to zero.
  583. * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
  584. * either deduced from the datasheet if the NAND
  585. * chip is not ONFI compliant or set to 0 if it is
  586. * (an ONFI chip is always configured in mode 0
  587. * after a NAND reset)
  588. * @numchips: [INTERN] number of physical chips
  589. * @chipsize: [INTERN] the size of one chip for multichip arrays
  590. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  591. * @pagebuf: [INTERN] holds the pagenumber which is currently in
  592. * data_buf.
  593. * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
  594. * currently in data_buf.
  595. * @subpagesize: [INTERN] holds the subpagesize
  596. * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
  597. * non 0 if ONFI supported.
  598. * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
  599. * non 0 if JEDEC supported.
  600. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
  601. * supported, 0 otherwise.
  602. * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
  603. * supported, 0 otherwise.
  604. * @read_retries: [INTERN] the number of read retry modes supported
  605. * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
  606. * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
  607. * @bbt: [INTERN] bad block table pointer
  608. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
  609. * lookup.
  610. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  611. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
  612. * bad block scan.
  613. * @controller: [REPLACEABLE] a pointer to a hardware controller
  614. * structure which is shared among multiple independent
  615. * devices.
  616. * @priv: [OPTIONAL] pointer to private chip data
  617. * @errstat: [OPTIONAL] hardware specific function to perform
  618. * additional error status checks (determine if errors are
  619. * correctable).
  620. * @write_page: [REPLACEABLE] High-level page write function
  621. */
  622. #ifdef CONFIG_DM_NAND
  623. /**
  624. * DM compatible nand drivers must have struct nand_chip as
  625. * the first part of their private data:
  626. * U_BOOT_DRIVER(...) = {
  627. * ...
  628. * .priv_auto_alloc_size = sizeof(struct nand_chip),
  629. * };
  630. */
  631. #endif
  632. struct nand_chip {
  633. struct mtd_info mtd;
  634. void __iomem *IO_ADDR_R;
  635. void __iomem *IO_ADDR_W;
  636. int flash_node;
  637. uint8_t (*read_byte)(struct mtd_info *mtd);
  638. u16 (*read_word)(struct mtd_info *mtd);
  639. void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
  640. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  641. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  642. void (*select_chip)(struct mtd_info *mtd, int chip);
  643. int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
  644. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  645. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  646. int (*dev_ready)(struct mtd_info *mtd);
  647. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
  648. int page_addr);
  649. int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  650. int (*erase)(struct mtd_info *mtd, int page);
  651. int (*scan_bbt)(struct mtd_info *mtd);
  652. int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
  653. int status, int page);
  654. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  655. uint32_t offset, int data_len, const uint8_t *buf,
  656. int oob_required, int page, int cached, int raw);
  657. int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
  658. int feature_addr, uint8_t *subfeature_para);
  659. int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
  660. int feature_addr, uint8_t *subfeature_para);
  661. int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
  662. int chip_delay;
  663. unsigned int options;
  664. unsigned int bbt_options;
  665. int page_shift;
  666. int phys_erase_shift;
  667. int bbt_erase_shift;
  668. int chip_shift;
  669. int numchips;
  670. uint64_t chipsize;
  671. int pagemask;
  672. int pagebuf;
  673. unsigned int pagebuf_bitflips;
  674. int subpagesize;
  675. uint8_t bits_per_cell;
  676. uint16_t ecc_strength_ds;
  677. uint16_t ecc_step_ds;
  678. int onfi_timing_mode_default;
  679. int badblockpos;
  680. int badblockbits;
  681. int onfi_version;
  682. int jedec_version;
  683. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  684. struct nand_onfi_params onfi_params;
  685. #endif
  686. struct nand_jedec_params jedec_params;
  687. int read_retries;
  688. flstate_t state;
  689. uint8_t *oob_poi;
  690. struct nand_hw_control *controller;
  691. struct nand_ecclayout *ecclayout;
  692. struct nand_ecc_ctrl ecc;
  693. struct nand_buffers *buffers;
  694. struct nand_hw_control hwcontrol;
  695. uint8_t *bbt;
  696. struct nand_bbt_descr *bbt_td;
  697. struct nand_bbt_descr *bbt_md;
  698. struct nand_bbt_descr *badblock_pattern;
  699. void *priv;
  700. };
  701. static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
  702. {
  703. return container_of(mtd, struct nand_chip, mtd);
  704. }
  705. static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
  706. {
  707. return &chip->mtd;
  708. }
  709. static inline void *nand_get_controller_data(struct nand_chip *chip)
  710. {
  711. return chip->priv;
  712. }
  713. static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
  714. {
  715. chip->priv = priv;
  716. }
  717. /*
  718. * NAND Flash Manufacturer ID Codes
  719. */
  720. #define NAND_MFR_TOSHIBA 0x98
  721. #define NAND_MFR_SAMSUNG 0xec
  722. #define NAND_MFR_FUJITSU 0x04
  723. #define NAND_MFR_NATIONAL 0x8f
  724. #define NAND_MFR_RENESAS 0x07
  725. #define NAND_MFR_STMICRO 0x20
  726. #define NAND_MFR_HYNIX 0xad
  727. #define NAND_MFR_MICRON 0x2c
  728. #define NAND_MFR_AMD 0x01
  729. #define NAND_MFR_MACRONIX 0xc2
  730. #define NAND_MFR_EON 0x92
  731. #define NAND_MFR_SANDISK 0x45
  732. #define NAND_MFR_INTEL 0x89
  733. #define NAND_MFR_ATO 0x9b
  734. /* The maximum expected count of bytes in the NAND ID sequence */
  735. #define NAND_MAX_ID_LEN 8
  736. /*
  737. * A helper for defining older NAND chips where the second ID byte fully
  738. * defined the chip, including the geometry (chip size, eraseblock size, page
  739. * size). All these chips have 512 bytes NAND page size.
  740. */
  741. #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
  742. { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
  743. .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
  744. /*
  745. * A helper for defining newer chips which report their page size and
  746. * eraseblock size via the extended ID bytes.
  747. *
  748. * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
  749. * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
  750. * device ID now only represented a particular total chip size (and voltage,
  751. * buswidth), and the page size, eraseblock size, and OOB size could vary while
  752. * using the same device ID.
  753. */
  754. #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
  755. { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
  756. .options = (opts) }
  757. #define NAND_ECC_INFO(_strength, _step) \
  758. { .strength_ds = (_strength), .step_ds = (_step) }
  759. #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
  760. #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
  761. /**
  762. * struct nand_flash_dev - NAND Flash Device ID Structure
  763. * @name: a human-readable name of the NAND chip
  764. * @dev_id: the device ID (the second byte of the full chip ID array)
  765. * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
  766. * memory address as @id[0])
  767. * @dev_id: device ID part of the full chip ID array (refers the same memory
  768. * address as @id[1])
  769. * @id: full device ID array
  770. * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  771. * well as the eraseblock size) is determined from the extended NAND
  772. * chip ID array)
  773. * @chipsize: total chip size in MiB
  774. * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
  775. * @options: stores various chip bit options
  776. * @id_len: The valid length of the @id.
  777. * @oobsize: OOB size
  778. * @ecc: ECC correctability and step information from the datasheet.
  779. * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  780. * @ecc_strength_ds in nand_chip{}.
  781. * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  782. * @ecc_step_ds in nand_chip{}, also from the datasheet.
  783. * For example, the "4bit ECC for each 512Byte" can be set with
  784. * NAND_ECC_INFO(4, 512).
  785. * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  786. * reset. Should be deduced from timings described
  787. * in the datasheet.
  788. *
  789. */
  790. struct nand_flash_dev {
  791. char *name;
  792. union {
  793. struct {
  794. uint8_t mfr_id;
  795. uint8_t dev_id;
  796. };
  797. uint8_t id[NAND_MAX_ID_LEN];
  798. };
  799. unsigned int pagesize;
  800. unsigned int chipsize;
  801. unsigned int erasesize;
  802. unsigned int options;
  803. uint16_t id_len;
  804. uint16_t oobsize;
  805. struct {
  806. uint16_t strength_ds;
  807. uint16_t step_ds;
  808. } ecc;
  809. int onfi_timing_mode_default;
  810. };
  811. /**
  812. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  813. * @name: Manufacturer name
  814. * @id: manufacturer ID code of device.
  815. */
  816. struct nand_manufacturers {
  817. int id;
  818. char *name;
  819. };
  820. extern struct nand_flash_dev nand_flash_ids[];
  821. extern struct nand_manufacturers nand_manuf_ids[];
  822. extern int nand_default_bbt(struct mtd_info *mtd);
  823. extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
  824. extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
  825. extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  826. extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  827. int allowbbt);
  828. extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  829. size_t *retlen, uint8_t *buf);
  830. /*
  831. * Constants for oob configuration
  832. */
  833. #define NAND_SMALL_BADBLOCK_POS 5
  834. #define NAND_LARGE_BADBLOCK_POS 0
  835. /**
  836. * struct platform_nand_chip - chip level device structure
  837. * @nr_chips: max. number of chips to scan for
  838. * @chip_offset: chip number offset
  839. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  840. * @partitions: mtd partition list
  841. * @chip_delay: R/B delay value in us
  842. * @options: Option flags, e.g. 16bit buswidth
  843. * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
  844. * @part_probe_types: NULL-terminated array of probe types
  845. */
  846. struct platform_nand_chip {
  847. int nr_chips;
  848. int chip_offset;
  849. int nr_partitions;
  850. struct mtd_partition *partitions;
  851. int chip_delay;
  852. unsigned int options;
  853. unsigned int bbt_options;
  854. const char **part_probe_types;
  855. };
  856. /* Keep gcc happy */
  857. struct platform_device;
  858. /**
  859. * struct platform_nand_ctrl - controller level device structure
  860. * @probe: platform specific function to probe/setup hardware
  861. * @remove: platform specific function to remove/teardown hardware
  862. * @hwcontrol: platform specific hardware control structure
  863. * @dev_ready: platform specific function to read ready/busy pin
  864. * @select_chip: platform specific chip select function
  865. * @cmd_ctrl: platform specific function for controlling
  866. * ALE/CLE/nCE. Also used to write command and address
  867. * @write_buf: platform specific function for write buffer
  868. * @read_buf: platform specific function for read buffer
  869. * @read_byte: platform specific function to read one byte from chip
  870. * @priv: private data to transport driver specific settings
  871. *
  872. * All fields are optional and depend on the hardware driver requirements
  873. */
  874. struct platform_nand_ctrl {
  875. int (*probe)(struct platform_device *pdev);
  876. void (*remove)(struct platform_device *pdev);
  877. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  878. int (*dev_ready)(struct mtd_info *mtd);
  879. void (*select_chip)(struct mtd_info *mtd, int chip);
  880. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  881. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  882. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  883. unsigned char (*read_byte)(struct mtd_info *mtd);
  884. void *priv;
  885. };
  886. /**
  887. * struct platform_nand_data - container structure for platform-specific data
  888. * @chip: chip level chip structure
  889. * @ctrl: controller level device structure
  890. */
  891. struct platform_nand_data {
  892. struct platform_nand_chip chip;
  893. struct platform_nand_ctrl ctrl;
  894. };
  895. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  896. /* return the supported features. */
  897. static inline int onfi_feature(struct nand_chip *chip)
  898. {
  899. return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
  900. }
  901. /* return the supported asynchronous timing mode. */
  902. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  903. {
  904. if (!chip->onfi_version)
  905. return ONFI_TIMING_MODE_UNKNOWN;
  906. return le16_to_cpu(chip->onfi_params.async_timing_mode);
  907. }
  908. /* return the supported synchronous timing mode. */
  909. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  910. {
  911. if (!chip->onfi_version)
  912. return ONFI_TIMING_MODE_UNKNOWN;
  913. return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
  914. }
  915. #endif
  916. /*
  917. * Check if it is a SLC nand.
  918. * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
  919. * We do not distinguish the MLC and TLC now.
  920. */
  921. static inline bool nand_is_slc(struct nand_chip *chip)
  922. {
  923. return chip->bits_per_cell == 1;
  924. }
  925. /**
  926. * Check if the opcode's address should be sent only on the lower 8 bits
  927. * @command: opcode to check
  928. */
  929. static inline int nand_opcode_8bits(unsigned int command)
  930. {
  931. switch (command) {
  932. case NAND_CMD_READID:
  933. case NAND_CMD_PARAM:
  934. case NAND_CMD_GET_FEATURES:
  935. case NAND_CMD_SET_FEATURES:
  936. return 1;
  937. default:
  938. break;
  939. }
  940. return 0;
  941. }
  942. /* return the supported JEDEC features. */
  943. static inline int jedec_feature(struct nand_chip *chip)
  944. {
  945. return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
  946. : 0;
  947. }
  948. /* Standard NAND functions from nand_base.c */
  949. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
  950. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
  951. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
  952. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
  953. uint8_t nand_read_byte(struct mtd_info *mtd);
  954. /*
  955. * struct nand_sdr_timings - SDR NAND chip timings
  956. *
  957. * This struct defines the timing requirements of a SDR NAND chip.
  958. * These informations can be found in every NAND datasheets and the timings
  959. * meaning are described in the ONFI specifications:
  960. * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  961. * Parameters)
  962. *
  963. * All these timings are expressed in picoseconds.
  964. */
  965. struct nand_sdr_timings {
  966. u32 tALH_min;
  967. u32 tADL_min;
  968. u32 tALS_min;
  969. u32 tAR_min;
  970. u32 tCEA_max;
  971. u32 tCEH_min;
  972. u32 tCH_min;
  973. u32 tCHZ_max;
  974. u32 tCLH_min;
  975. u32 tCLR_min;
  976. u32 tCLS_min;
  977. u32 tCOH_min;
  978. u32 tCS_min;
  979. u32 tDH_min;
  980. u32 tDS_min;
  981. u32 tFEAT_max;
  982. u32 tIR_min;
  983. u32 tITC_max;
  984. u32 tRC_min;
  985. u32 tREA_max;
  986. u32 tREH_min;
  987. u32 tRHOH_min;
  988. u32 tRHW_min;
  989. u32 tRHZ_max;
  990. u32 tRLOH_min;
  991. u32 tRP_min;
  992. u32 tRR_min;
  993. u64 tRST_max;
  994. u32 tWB_max;
  995. u32 tWC_min;
  996. u32 tWH_min;
  997. u32 tWHR_min;
  998. u32 tWP_min;
  999. u32 tWW_min;
  1000. };
  1001. /* get timing characteristics from ONFI timing mode. */
  1002. const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
  1003. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1004. void *ecc, int ecclen,
  1005. void *extraoob, int extraooblen,
  1006. int threshold);
  1007. #endif /* __LINUX_MTD_NAND_H */