ti816x_evm.h 3.9 KB

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  1. /*
  2. * ti816x_evm.h
  3. *
  4. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  5. * Antoine Tenart, <atenart@adeneo-embedded.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __CONFIG_TI816X_EVM_H
  10. #define __CONFIG_TI816X_EVM_H
  11. #define CONFIG_TI81XX
  12. #define CONFIG_TI816X
  13. #define CONFIG_SYS_NO_FLASH
  14. #define CONFIG_OMAP
  15. #define CONFIG_ARCH_CPU_INIT
  16. #include <asm/arch/omap.h>
  17. #define CONFIG_ENV_SIZE 0x2000
  18. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
  19. #define CONFIG_SYS_LONGHELP /* undef save memory */
  20. #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
  21. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  22. #define CONFIG_SETUP_MEMORY_TAGS
  23. #define CONFIG_INITRD_TAG /* required for ramdisk support */
  24. #define CONFIG_EXTRA_ENV_SETTINGS \
  25. "loadaddr=0x81000000\0" \
  26. #define CONFIG_BOOTCOMMAND \
  27. "mmc rescan;" \
  28. "fatload mmc 0 ${loadaddr} uImage;" \
  29. "bootm ${loadaddr}" \
  30. #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
  31. /* Clock Defines */
  32. #define V_OSCK 24000000 /* Clock output from T2 */
  33. #define V_SCLK (V_OSCK >> 1)
  34. #define CONFIG_SYS_MAXARGS 32
  35. #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
  36. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
  37. + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
  38. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
  39. #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
  40. #define CONFIG_CMD_ASKEN
  41. #define CONFIG_OMAP_GPIO
  42. #define CONFIG_GENERIC_MMC
  43. #define CONFIG_OMAP_HSMMC
  44. #define CONFIG_DOS_PARTITION
  45. #define CONFIG_FS_FAT
  46. /*
  47. * Only one of the following two options (DDR3/DDR2) should be enabled
  48. * CONFIG_TI816X_EVM_DDR2
  49. * CONFIG_TI816X_EVM_DDR3
  50. */
  51. #define CONFIG_TI816X_EVM_DDR3
  52. /*
  53. * Supported values: 400, 531, 675 or 796 MHz
  54. */
  55. #define CONFIG_TI816X_DDR_PLL_796
  56. #define CONFIG_TI816X_USE_EMIF0 1
  57. #define CONFIG_TI816X_USE_EMIF1 1
  58. #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
  59. #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
  60. #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
  61. #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
  62. #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
  63. #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
  64. #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
  65. #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
  66. GENERATED_GBL_DATA_SIZE)
  67. /**
  68. * Platform/Board specific defs
  69. */
  70. #define CONFIG_SYS_CLK_FREQ 27000000
  71. #define CONFIG_SYS_TIMERBASE 0x4802E000
  72. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  73. #undef CONFIG_NAND_OMAP_GPMC
  74. /*
  75. * NS16550 Configuration
  76. */
  77. #define CONFIG_SYS_NS16550_SERIAL
  78. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  79. #define CONFIG_SYS_NS16550_CLK (48000000)
  80. #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
  81. #define CONFIG_BAUDRATE 115200
  82. /* allow overwriting serial config and ethaddr */
  83. #define CONFIG_ENV_OVERWRITE
  84. #define CONFIG_SERIAL1
  85. #define CONFIG_SERIAL2
  86. #define CONFIG_SERIAL3
  87. #define CONFIG_CONS_INDEX 1
  88. #define CONFIG_ENV_IS_NOWHERE
  89. /* SPL */
  90. /* Defines for SPL */
  91. #define CONFIG_SPL_FRAMEWORK
  92. #define CONFIG_SPL_TEXT_BASE 0x40400000
  93. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  94. CONFIG_SPL_TEXT_BASE)
  95. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  96. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  97. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  98. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  99. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
  100. #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
  101. #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
  102. #define CONFIG_SPL_BOARD_INIT
  103. #define CONFIG_SYS_TEXT_BASE 0x80800000
  104. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  105. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  106. /* Since SPL did pll and ddr initialization for us,
  107. * we don't need to do it twice.
  108. */
  109. #ifndef CONFIG_SPL_BUILD
  110. #define CONFIG_SKIP_LOWLEVEL_INIT
  111. #endif
  112. /* Unsupported features */
  113. #undef CONFIG_USE_IRQ
  114. #endif