porter.h 2.6 KB

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  1. /*
  2. * include/configs/porter.h
  3. * This file is Porter board configuration.
  4. *
  5. * Copyright (C) 2015 Renesas Electronics Corporation
  6. * Copyright (C) 2015 Cogent Embedded, Inc.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0
  9. */
  10. #ifndef __PORTER_H
  11. #define __PORTER_H
  12. #undef DEBUG
  13. #define CONFIG_R8A7791
  14. #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
  15. #include "rcar-gen2-common.h"
  16. #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  17. #define CONFIG_SYS_TEXT_BASE 0x70000000
  18. #else
  19. #define CONFIG_SYS_TEXT_BASE 0xE6304000
  20. #endif
  21. #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  22. #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
  23. #else
  24. #define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
  25. #endif
  26. #define STACK_AREA_SIZE 0xC000
  27. #define LOW_LEVEL_MERAM_STACK \
  28. (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  29. /* MEMORY */
  30. #define RCAR_GEN2_SDRAM_BASE 0x40000000
  31. #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
  32. #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
  33. /* SCIF */
  34. #define CONFIG_SCIF_CONSOLE
  35. /* FLASH */
  36. #define CONFIG_SPI
  37. #define CONFIG_SH_QSPI
  38. #define CONFIG_SPI_FLASH_QUAD
  39. #define CONFIG_SYS_NO_FLASH
  40. /* SH Ether */
  41. #define CONFIG_SH_ETHER
  42. #define CONFIG_SH_ETHER_USE_PORT 0
  43. #define CONFIG_SH_ETHER_PHY_ADDR 0x1
  44. #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  45. #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  46. #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  47. #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
  48. #define CONFIG_PHYLIB
  49. #define CONFIG_PHY_MICREL
  50. #define CONFIG_BITBANGMII
  51. #define CONFIG_BITBANGMII_MULTI
  52. /* Board Clock */
  53. #define RMOBILE_XTAL_CLK 20000000u
  54. #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
  55. #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
  56. #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
  57. #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
  58. #define CONFIG_SYS_TMU_CLK_DIV 4
  59. /* i2c */
  60. #define CONFIG_SYS_I2C
  61. #define CONFIG_SYS_I2C_SH
  62. #define CONFIG_SYS_I2C_SLAVE 0x7F
  63. #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
  64. #define CONFIG_SYS_I2C_SH_SPEED0 400000
  65. #define CONFIG_SYS_I2C_SH_SPEED1 400000
  66. #define CONFIG_SYS_I2C_SH_SPEED2 400000
  67. #define CONFIG_SH_I2C_DATA_HIGH 4
  68. #define CONFIG_SH_I2C_DATA_LOW 5
  69. #define CONFIG_SH_I2C_CLOCK 10000000
  70. #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
  71. /* USB */
  72. #define CONFIG_USB_EHCI
  73. #define CONFIG_USB_EHCI_RMOBILE
  74. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  75. /* SD */
  76. #define CONFIG_GENERIC_MMC
  77. #define CONFIG_SH_SDHI_FREQ 97500000
  78. /* Module stop status bits */
  79. /* INTC-RT */
  80. #define CONFIG_SMSTP0_ENA 0x00400000
  81. /* MSIF */
  82. #define CONFIG_SMSTP2_ENA 0x00002000
  83. /* INTC-SYS, IRQC */
  84. #define CONFIG_SMSTP4_ENA 0x00000180
  85. /* SCIF0 */
  86. #define CONFIG_SMSTP7_ENA 0x00200000
  87. #endif /* __PORTER_H */