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csu3_am335x
/
board-support
/
u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
/
include
/
configs
/
lager.h

lager.h 2.7 KB
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  1. /*
    2. 

  2.  * include/configs/lager.h
    3. 

  3.  *     This file is lager board configuration.
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
    6. 

  6.  *
    7. 

  7.  * SPDX-License-Identifier: GPL-2.0
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __LAGER_H
    11. 

  11. #define __LAGER_H
    12. 

  12. 

  13. #undef DEBUG
    14. 

  14. #define CONFIG_R8A7790
    15. 

  15. #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
    16. 

  16. 

  17. #include "rcar-gen2-common.h"
    18. 

  18. 

  19. #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
    20. 

  20. #define CONFIG_SYS_TEXT_BASE	0xB0000000
    21. 

  21. #else
    22. 

  22. #define CONFIG_SYS_TEXT_BASE	0xE8080000
    23. 

  23. #endif
    24. 

  24. 

  25. /* STACK */
    26. 

  26. #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
    27. 

  27. #define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
    28. 

  28. #else
    29. 

  29. #define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
    30. 

  30. #endif
    31. 

  31. #define STACK_AREA_SIZE			0xC000
    32. 

  32. #define LOW_LEVEL_MERAM_STACK	\
    33. 

  33. 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
    34. 

  34. 

  35. /* MEMORY */
    36. 

  36. #define RCAR_GEN2_SDRAM_BASE		0x40000000
    37. 

  37. #define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
    38. 

  38. #define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
    39. 

  39. 

  40. /* SCIF */
    41. 

  41. #define CONFIG_SCIF_CONSOLE
    42. 

  42. 

  43. /* SPI */
    44. 

  44. #define CONFIG_SPI
    45. 

  45. #define CONFIG_SH_QSPI
    46. 

  46. #define CONFIG_SYS_NO_FLASH
    47. 

  47. 

  48. /* SH Ether */
    49. 

  49. #define CONFIG_SH_ETHER
    50. 

  50. #define CONFIG_SH_ETHER_USE_PORT	0
    51. 

  51. #define CONFIG_SH_ETHER_PHY_ADDR	0x1
    52. 

  52. #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
    53. 

  53. #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
    54. 

  54. #define CONFIG_SH_ETHER_CACHE_WRITEBACK
    55. 

  55. #define CONFIG_SH_ETHER_CACHE_INVALIDATE
    56. 

  56. #define CONFIG_PHYLIB
    57. 

  57. #define CONFIG_PHY_MICREL
    58. 

  58. #define CONFIG_BITBANGMII
    59. 

  59. #define CONFIG_BITBANGMII_MULTI
    60. 

  60. 

  61. /* I2C */
    62. 

  62. #define CONFIG_SYS_I2C
    63. 

  63. #define CONFIG_SYS_I2C_RCAR
    64. 

  64. #define CONFIG_SYS_RCAR_I2C0_SPEED	400000
    65. 

  65. #define CONFIG_SYS_RCAR_I2C1_SPEED	400000
    66. 

  66. #define CONFIG_SYS_RCAR_I2C2_SPEED	400000
    67. 

  67. #define CONFIG_SYS_RCAR_I2C3_SPEED	400000
    68. 

  68. #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4
    69. 

  69. 

  70. #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
    71. 

  71. 

  72. /* Board Clock */
    73. 

  73. #define RMOBILE_XTAL_CLK	20000000u
    74. 

  74. #define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
    75. 

  75. #define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
    76. 

  76. #define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
    77. 

  77. #define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
    78. 

  78. #define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
    79. 

  79. #define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
    80. 

  80. 

  81. #define CONFIG_SYS_TMU_CLK_DIV	4
    82. 

  82. 

  83. /* USB */
    84. 

  84. #define CONFIG_USB_EHCI
    85. 

  85. #define CONFIG_USB_EHCI_RMOBILE
    86. 

  86. #define CONFIG_USB_MAX_CONTROLLER_COUNT	3
    87. 

  87. 

  88. /* MMC */
    89. 

  89. #define CONFIG_GENERIC_MMC
    90. 

  90. 

  91. #define CONFIG_SH_MMCIF
    92. 

  92. #define CONFIG_SH_MMCIF_ADDR		0xEE220000
    93. 

  93. #define CONFIG_SH_MMCIF_CLK		97500000
    94. 

  94. 

  95. /* Module stop status bits */
    96. 

  96. /* INTC-RT */
    97. 

  97. #define CONFIG_SMSTP0_ENA	0x00400000
    98. 

  98. /* MSIF */
    99. 

  99. #define CONFIG_SMSTP2_ENA	0x00002000
    100. 

  100. /* INTC-SYS, IRQC */
    101. 

  101. #define CONFIG_SMSTP4_ENA	0x00000180
    102. 

  102. /* SCIF0 */
    103. 

  103. #define CONFIG_SMSTP7_ENA	0x00200000
    104. 

  104. 

  105. /* SDHI */
    106. 

  106. #define CONFIG_SH_SDHI_FREQ	97500000
    107. 

  107. 

  108. #endif	/* __LAGER_H */
    109.