T208xQDS.h 30 KB

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  1. /*
  2. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * T2080/T2081 QDS board configuration file
  8. */
  9. #ifndef __T208xQDS_H
  10. #define __T208xQDS_H
  11. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  12. #define CONFIG_USB_EHCI
  13. #if defined(CONFIG_ARCH_T2080)
  14. #define CONFIG_FSL_SATA_V2
  15. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  16. #define CONFIG_SRIO1 /* SRIO port 1 */
  17. #define CONFIG_SRIO2 /* SRIO port 2 */
  18. #elif defined(CONFIG_ARCH_T2081)
  19. #endif
  20. /* High Level Configuration Options */
  21. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  22. #define CONFIG_MP /* support multiple processors */
  23. #define CONFIG_ENABLE_36BIT_PHYS
  24. #ifdef CONFIG_PHYS_64BIT
  25. #define CONFIG_ADDR_MAP 1
  26. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  27. #endif
  28. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  29. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  30. #define CONFIG_FSL_IFC /* Enable IFC Support */
  31. #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
  32. #define CONFIG_ENV_OVERWRITE
  33. #ifdef CONFIG_RAMBOOT_PBL
  34. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  35. #define CONFIG_SPL_FLUSH_IMAGE
  36. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  37. #define CONFIG_SYS_TEXT_BASE 0x00201000
  38. #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  39. #define CONFIG_SPL_PAD_TO 0x40000
  40. #define CONFIG_SPL_MAX_SIZE 0x28000
  41. #define RESET_VECTOR_OFFSET 0x27FFC
  42. #define BOOT_PAGE_OFFSET 0x27000
  43. #ifdef CONFIG_SPL_BUILD
  44. #define CONFIG_SPL_SKIP_RELOCATE
  45. #define CONFIG_SPL_COMMON_INIT_DDR
  46. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  47. #define CONFIG_SYS_NO_FLASH
  48. #endif
  49. #ifdef CONFIG_NAND
  50. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  51. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  52. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  53. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  54. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  55. #if defined(CONFIG_ARCH_T2080)
  56. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
  57. #elif defined(CONFIG_ARCH_T2081)
  58. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
  59. #endif
  60. #define CONFIG_SPL_NAND_BOOT
  61. #endif
  62. #ifdef CONFIG_SPIFLASH
  63. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  64. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  65. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  66. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  67. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  68. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  69. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  70. #ifndef CONFIG_SPL_BUILD
  71. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72. #endif
  73. #if defined(CONFIG_ARCH_T2080)
  74. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
  75. #elif defined(CONFIG_ARCH_T2081)
  76. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
  77. #endif
  78. #define CONFIG_SPL_SPI_BOOT
  79. #endif
  80. #ifdef CONFIG_SDCARD
  81. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  82. #define CONFIG_SPL_MMC_MINIMAL
  83. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  84. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  85. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  86. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  87. #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  88. #ifndef CONFIG_SPL_BUILD
  89. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  90. #endif
  91. #if defined(CONFIG_ARCH_T2080)
  92. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
  93. #elif defined(CONFIG_ARCH_T2081)
  94. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
  95. #endif
  96. #define CONFIG_SPL_MMC_BOOT
  97. #endif
  98. #endif /* CONFIG_RAMBOOT_PBL */
  99. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  100. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  101. /* Set 1M boot space */
  102. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  103. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  104. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  105. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  106. #define CONFIG_SYS_NO_FLASH
  107. #endif
  108. #ifndef CONFIG_SYS_TEXT_BASE
  109. #define CONFIG_SYS_TEXT_BASE 0xeff40000
  110. #endif
  111. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  112. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  113. #endif
  114. /*
  115. * These can be toggled for performance analysis, otherwise use default.
  116. */
  117. #define CONFIG_SYS_CACHE_STASHING
  118. #define CONFIG_BTB /* toggle branch predition */
  119. #define CONFIG_DDR_ECC
  120. #ifdef CONFIG_DDR_ECC
  121. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  122. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  123. #endif
  124. #ifndef CONFIG_SYS_NO_FLASH
  125. #define CONFIG_FLASH_CFI_DRIVER
  126. #define CONFIG_SYS_FLASH_CFI
  127. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  128. #endif
  129. #if defined(CONFIG_SPIFLASH)
  130. #define CONFIG_SYS_EXTRA_ENV_RELOC
  131. #define CONFIG_ENV_IS_IN_SPI_FLASH
  132. #define CONFIG_ENV_SPI_BUS 0
  133. #define CONFIG_ENV_SPI_CS 0
  134. #define CONFIG_ENV_SPI_MAX_HZ 10000000
  135. #define CONFIG_ENV_SPI_MODE 0
  136. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  137. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  138. #define CONFIG_ENV_SECT_SIZE 0x10000
  139. #elif defined(CONFIG_SDCARD)
  140. #define CONFIG_SYS_EXTRA_ENV_RELOC
  141. #define CONFIG_ENV_IS_IN_MMC
  142. #define CONFIG_SYS_MMC_ENV_DEV 0
  143. #define CONFIG_ENV_SIZE 0x2000
  144. #define CONFIG_ENV_OFFSET (512 * 0x800)
  145. #elif defined(CONFIG_NAND)
  146. #define CONFIG_SYS_EXTRA_ENV_RELOC
  147. #define CONFIG_ENV_IS_IN_NAND
  148. #define CONFIG_ENV_SIZE 0x2000
  149. #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  150. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  151. #define CONFIG_ENV_IS_IN_REMOTE
  152. #define CONFIG_ENV_ADDR 0xffe20000
  153. #define CONFIG_ENV_SIZE 0x2000
  154. #elif defined(CONFIG_ENV_IS_NOWHERE)
  155. #define CONFIG_ENV_SIZE 0x2000
  156. #else
  157. #define CONFIG_ENV_IS_IN_FLASH
  158. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  159. #define CONFIG_ENV_SIZE 0x2000
  160. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  161. #endif
  162. #ifndef __ASSEMBLY__
  163. unsigned long get_board_sys_clk(void);
  164. unsigned long get_board_ddr_clk(void);
  165. #endif
  166. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  167. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  168. /*
  169. * Config the L3 Cache as L3 SRAM
  170. */
  171. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  172. #define CONFIG_SYS_L3_SIZE (512 << 10)
  173. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  174. #ifdef CONFIG_RAMBOOT_PBL
  175. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  176. #endif
  177. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  178. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  179. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  180. #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
  181. #define CONFIG_SYS_DCSRBAR 0xf0000000
  182. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  183. /* EEPROM */
  184. #define CONFIG_ID_EEPROM
  185. #define CONFIG_SYS_I2C_EEPROM_NXID
  186. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  187. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  188. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  189. /*
  190. * DDR Setup
  191. */
  192. #define CONFIG_VERY_BIG_RAM
  193. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  194. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  195. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  196. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  197. #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  198. #define CONFIG_DDR_SPD
  199. #define CONFIG_FSL_DDR_INTERACTIVE
  200. #define CONFIG_SYS_SPD_BUS_NUM 0
  201. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  202. #define SPD_EEPROM_ADDRESS1 0x51
  203. #define SPD_EEPROM_ADDRESS2 0x52
  204. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  205. #define CTRL_INTLV_PREFERED cacheline
  206. /*
  207. * IFC Definitions
  208. */
  209. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  210. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  211. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  212. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  213. + 0x8000000) | \
  214. CSPR_PORT_SIZE_16 | \
  215. CSPR_MSEL_NOR | \
  216. CSPR_V)
  217. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  218. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  219. CSPR_PORT_SIZE_16 | \
  220. CSPR_MSEL_NOR | \
  221. CSPR_V)
  222. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  223. /* NOR Flash Timing Params */
  224. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  225. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  226. FTIM0_NOR_TEADC(0x5) | \
  227. FTIM0_NOR_TEAHC(0x5))
  228. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  229. FTIM1_NOR_TRAD_NOR(0x1A) |\
  230. FTIM1_NOR_TSEQRAD_NOR(0x13))
  231. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  232. FTIM2_NOR_TCH(0x4) | \
  233. FTIM2_NOR_TWPH(0x0E) | \
  234. FTIM2_NOR_TWP(0x1c))
  235. #define CONFIG_SYS_NOR_FTIM3 0x0
  236. #define CONFIG_SYS_FLASH_QUIET_TEST
  237. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  238. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  239. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  240. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  241. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  242. #define CONFIG_SYS_FLASH_EMPTY_INFO
  243. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  244. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  245. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  246. #define QIXIS_BASE 0xffdf0000
  247. #define QIXIS_LBMAP_SWITCH 6
  248. #define QIXIS_LBMAP_MASK 0x0f
  249. #define QIXIS_LBMAP_SHIFT 0
  250. #define QIXIS_LBMAP_DFLTBANK 0x00
  251. #define QIXIS_LBMAP_ALTBANK 0x04
  252. #define QIXIS_LBMAP_NAND 0x09
  253. #define QIXIS_LBMAP_SD 0x00
  254. #define QIXIS_RCW_SRC_NAND 0x104
  255. #define QIXIS_RCW_SRC_SD 0x040
  256. #define QIXIS_RST_CTL_RESET 0x83
  257. #define QIXIS_RST_FORCE_MEM 0x1
  258. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  259. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  260. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  261. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  262. #define CONFIG_SYS_CSPR3_EXT (0xf)
  263. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  264. | CSPR_PORT_SIZE_8 \
  265. | CSPR_MSEL_GPCM \
  266. | CSPR_V)
  267. #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
  268. #define CONFIG_SYS_CSOR3 0x0
  269. /* QIXIS Timing parameters for IFC CS3 */
  270. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  271. FTIM0_GPCM_TEADC(0x0e) | \
  272. FTIM0_GPCM_TEAHC(0x0e))
  273. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  274. FTIM1_GPCM_TRAD(0x3f))
  275. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  276. FTIM2_GPCM_TCH(0x8) | \
  277. FTIM2_GPCM_TWP(0x1f))
  278. #define CONFIG_SYS_CS3_FTIM3 0x0
  279. /* NAND Flash on IFC */
  280. #define CONFIG_NAND_FSL_IFC
  281. #define CONFIG_SYS_NAND_BASE 0xff800000
  282. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  283. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  284. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  285. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  286. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  287. | CSPR_V)
  288. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  289. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  290. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  291. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  292. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  293. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  294. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  295. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  296. #define CONFIG_SYS_NAND_ONFI_DETECTION
  297. /* ONFI NAND Flash mode0 Timing Params */
  298. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  299. FTIM0_NAND_TWP(0x18) | \
  300. FTIM0_NAND_TWCHT(0x07) | \
  301. FTIM0_NAND_TWH(0x0a))
  302. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  303. FTIM1_NAND_TWBE(0x39) | \
  304. FTIM1_NAND_TRR(0x0e) | \
  305. FTIM1_NAND_TRP(0x18))
  306. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  307. FTIM2_NAND_TREH(0x0a) | \
  308. FTIM2_NAND_TWHRE(0x1e))
  309. #define CONFIG_SYS_NAND_FTIM3 0x0
  310. #define CONFIG_SYS_NAND_DDR_LAW 11
  311. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  312. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  313. #define CONFIG_CMD_NAND
  314. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  315. #if defined(CONFIG_NAND)
  316. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  317. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  318. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  319. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  320. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  321. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  322. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  323. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  324. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  325. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  326. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  327. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  328. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  329. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  330. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  331. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  332. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  333. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  334. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  335. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  336. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  337. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  338. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  339. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  340. #else
  341. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  342. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  343. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  344. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  345. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  346. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  347. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  348. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  349. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  350. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  351. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  352. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  353. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  354. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  355. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  356. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  357. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  358. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  359. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  360. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  361. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  362. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  363. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  364. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  365. #endif
  366. #if defined(CONFIG_RAMBOOT_PBL)
  367. #define CONFIG_SYS_RAMBOOT
  368. #endif
  369. #ifdef CONFIG_SPL_BUILD
  370. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  371. #else
  372. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  373. #endif
  374. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  375. #define CONFIG_MISC_INIT_R
  376. #define CONFIG_HWCONFIG
  377. /* define to use L1 as initial stack */
  378. #define CONFIG_L1_INIT_RAM
  379. #define CONFIG_SYS_INIT_RAM_LOCK
  380. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  381. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  382. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  383. /* The assembler doesn't like typecast */
  384. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  385. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  386. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  387. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  388. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  389. GENERATED_GBL_DATA_SIZE)
  390. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  391. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  392. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  393. /*
  394. * Serial Port
  395. */
  396. #define CONFIG_CONS_INDEX 1
  397. #define CONFIG_SYS_NS16550_SERIAL
  398. #define CONFIG_SYS_NS16550_REG_SIZE 1
  399. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  400. #define CONFIG_SYS_BAUDRATE_TABLE \
  401. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  402. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  403. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  404. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  405. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  406. /*
  407. * I2C
  408. */
  409. #define CONFIG_SYS_I2C
  410. #define CONFIG_SYS_I2C_FSL
  411. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  412. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  413. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  414. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  415. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  416. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  417. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  418. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  419. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  420. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  421. #define CONFIG_SYS_FSL_I2C3_SPEED 100000
  422. #define CONFIG_SYS_FSL_I2C4_SPEED 100000
  423. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  424. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  425. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  426. #define I2C_MUX_CH_DEFAULT 0x8
  427. #define I2C_MUX_CH_VOL_MONITOR 0xa
  428. /* Voltage monitor on channel 2*/
  429. #define I2C_VOL_MONITOR_ADDR 0x40
  430. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  431. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  432. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  433. #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
  434. #ifndef CONFIG_SPL_BUILD
  435. #define CONFIG_VID
  436. #endif
  437. #define CONFIG_VOL_MONITOR_IR36021_SET
  438. #define CONFIG_VOL_MONITOR_IR36021_READ
  439. /* The lowest and highest voltage allowed for T208xQDS */
  440. #define VDD_MV_MIN 819
  441. #define VDD_MV_MAX 1212
  442. /*
  443. * RapidIO
  444. */
  445. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  446. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  447. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  448. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  449. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  450. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  451. /*
  452. * for slave u-boot IMAGE instored in master memory space,
  453. * PHYS must be aligned based on the SIZE
  454. */
  455. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  456. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  457. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  458. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  459. /*
  460. * for slave UCODE and ENV instored in master memory space,
  461. * PHYS must be aligned based on the SIZE
  462. */
  463. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  464. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  465. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  466. /* slave core release by master*/
  467. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  468. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  469. /*
  470. * SRIO_PCIE_BOOT - SLAVE
  471. */
  472. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  473. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  474. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  475. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  476. #endif
  477. /*
  478. * eSPI - Enhanced SPI
  479. */
  480. #ifdef CONFIG_SPI_FLASH
  481. #ifndef CONFIG_SPL_BUILD
  482. #endif
  483. #define CONFIG_SPI_FLASH_BAR
  484. #define CONFIG_SF_DEFAULT_SPEED 10000000
  485. #define CONFIG_SF_DEFAULT_MODE 0
  486. #endif
  487. /*
  488. * General PCI
  489. * Memory space is mapped 1-1, but I/O space must start from 0.
  490. */
  491. #define CONFIG_PCIE1 /* PCIE controller 1 */
  492. #define CONFIG_PCIE2 /* PCIE controller 2 */
  493. #define CONFIG_PCIE3 /* PCIE controller 3 */
  494. #define CONFIG_PCIE4 /* PCIE controller 4 */
  495. #define CONFIG_FSL_PCIE_RESET
  496. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  497. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  498. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  499. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  500. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  501. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  502. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  503. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  504. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  505. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  506. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  507. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  508. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  509. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  510. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  511. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  512. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  513. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  514. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  515. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  516. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  517. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  518. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  519. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  520. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  521. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  522. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  523. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  524. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  525. /* controller 4, Base address 203000 */
  526. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  527. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  528. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  529. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  530. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  531. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  532. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  533. #ifdef CONFIG_PCI
  534. #define CONFIG_PCI_INDIRECT_BRIDGE
  535. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  536. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  537. #define CONFIG_DOS_PARTITION
  538. #endif
  539. /* Qman/Bman */
  540. #ifndef CONFIG_NOBQFMAN
  541. #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  542. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  543. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  544. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  545. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  546. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  547. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  548. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  549. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  550. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  551. CONFIG_SYS_BMAN_CENA_SIZE)
  552. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  553. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  554. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  555. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  556. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  557. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  558. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  559. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  560. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  561. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  562. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  563. CONFIG_SYS_QMAN_CENA_SIZE)
  564. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  565. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  566. #define CONFIG_SYS_DPAA_FMAN
  567. #define CONFIG_SYS_DPAA_PME
  568. #define CONFIG_SYS_PMAN
  569. #define CONFIG_SYS_DPAA_DCE
  570. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  571. #define CONFIG_SYS_INTERLAKEN
  572. /* Default address of microcode for the Linux Fman driver */
  573. #if defined(CONFIG_SPIFLASH)
  574. /*
  575. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  576. * env, so we got 0x110000.
  577. */
  578. #define CONFIG_SYS_QE_FW_IN_SPIFLASH
  579. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  580. #elif defined(CONFIG_SDCARD)
  581. /*
  582. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  583. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  584. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  585. */
  586. #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  587. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  588. #elif defined(CONFIG_NAND)
  589. #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  590. #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  591. #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  592. /*
  593. * Slave has no ucode locally, it can fetch this from remote. When implementing
  594. * in two corenet boards, slave's ucode could be stored in master's memory
  595. * space, the address can be mapped from slave TLB->slave LAW->
  596. * slave SRIO or PCIE outbound window->master inbound window->
  597. * master LAW->the ucode address in master's memory space.
  598. */
  599. #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  600. #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  601. #else
  602. #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  603. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  604. #endif
  605. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  606. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  607. #endif /* CONFIG_NOBQFMAN */
  608. #ifdef CONFIG_SYS_DPAA_FMAN
  609. #define CONFIG_FMAN_ENET
  610. #define CONFIG_PHYLIB_10G
  611. #define CONFIG_PHY_VITESSE
  612. #define CONFIG_PHY_REALTEK
  613. #define CONFIG_PHY_TERANETICS
  614. #define RGMII_PHY1_ADDR 0x1
  615. #define RGMII_PHY2_ADDR 0x2
  616. #define FM1_10GEC1_PHY_ADDR 0x3
  617. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  618. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  619. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  620. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  621. #endif
  622. #ifdef CONFIG_FMAN_ENET
  623. #define CONFIG_MII /* MII PHY management */
  624. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  625. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  626. #endif
  627. /*
  628. * SATA
  629. */
  630. #ifdef CONFIG_FSL_SATA_V2
  631. #define CONFIG_LIBATA
  632. #define CONFIG_FSL_SATA
  633. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  634. #define CONFIG_SATA1
  635. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  636. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  637. #define CONFIG_SATA2
  638. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  639. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  640. #define CONFIG_LBA48
  641. #define CONFIG_CMD_SATA
  642. #define CONFIG_DOS_PARTITION
  643. #endif
  644. /*
  645. * USB
  646. */
  647. #ifdef CONFIG_USB_EHCI
  648. #define CONFIG_USB_EHCI_FSL
  649. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  650. #define CONFIG_HAS_FSL_DR_USB
  651. #endif
  652. /*
  653. * SDHC
  654. */
  655. #ifdef CONFIG_MMC
  656. #define CONFIG_FSL_ESDHC
  657. #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  658. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  659. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  660. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  661. #define CONFIG_GENERIC_MMC
  662. #define CONFIG_DOS_PARTITION
  663. #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
  664. #endif
  665. /*
  666. * Dynamic MTD Partition support with mtdparts
  667. */
  668. #ifndef CONFIG_SYS_NO_FLASH
  669. #define CONFIG_MTD_DEVICE
  670. #define CONFIG_MTD_PARTITIONS
  671. #define CONFIG_CMD_MTDPARTS
  672. #define CONFIG_FLASH_CFI_MTD
  673. #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
  674. "spi0=spife110000.0"
  675. #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
  676. "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
  677. "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
  678. "1m(uboot),5m(kernel),128k(dtb),-(user)"
  679. #endif
  680. /*
  681. * Environment
  682. */
  683. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  684. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  685. /*
  686. * Command line configuration.
  687. */
  688. #define CONFIG_CMD_ERRATA
  689. #define CONFIG_CMD_IRQ
  690. #define CONFIG_CMD_REGINFO
  691. #ifdef CONFIG_PCI
  692. #define CONFIG_CMD_PCI
  693. #endif
  694. /* Hash command with SHA acceleration supported in hardware */
  695. #ifdef CONFIG_FSL_CAAM
  696. #define CONFIG_CMD_HASH
  697. #define CONFIG_SHA_HW_ACCEL
  698. #endif
  699. /*
  700. * Miscellaneous configurable options
  701. */
  702. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  703. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  704. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  705. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  706. #ifdef CONFIG_CMD_KGDB
  707. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  708. #else
  709. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  710. #endif
  711. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  712. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  713. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  714. /*
  715. * For booting Linux, the board info and command line data
  716. * have to be in the first 64 MB of memory, since this is
  717. * the maximum mapped by the Linux kernel during initialization.
  718. */
  719. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  720. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  721. #ifdef CONFIG_CMD_KGDB
  722. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  723. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  724. #endif
  725. /*
  726. * Environment Configuration
  727. */
  728. #define CONFIG_ROOTPATH "/opt/nfsroot"
  729. #define CONFIG_BOOTFILE "uImage"
  730. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  731. /* default location for tftp and bootm */
  732. #define CONFIG_LOADADDR 1000000
  733. #define CONFIG_BAUDRATE 115200
  734. #define __USB_PHY_TYPE utmi
  735. #define CONFIG_EXTRA_ENV_SETTINGS \
  736. "hwconfig=fsl_ddr:" \
  737. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  738. "bank_intlv=auto;" \
  739. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  740. "netdev=eth0\0" \
  741. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  742. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  743. "tftpflash=tftpboot $loadaddr $uboot && " \
  744. "protect off $ubootaddr +$filesize && " \
  745. "erase $ubootaddr +$filesize && " \
  746. "cp.b $loadaddr $ubootaddr $filesize && " \
  747. "protect on $ubootaddr +$filesize && " \
  748. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  749. "consoledev=ttyS0\0" \
  750. "ramdiskaddr=2000000\0" \
  751. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  752. "fdtaddr=1e00000\0" \
  753. "fdtfile=t2080qds/t2080qds.dtb\0" \
  754. "bdev=sda3\0"
  755. /*
  756. * For emulation this causes u-boot to jump to the start of the
  757. * proof point app code automatically
  758. */
  759. #define CONFIG_PROOF_POINTS \
  760. "setenv bootargs root=/dev/$bdev rw " \
  761. "console=$consoledev,$baudrate $othbootargs;" \
  762. "cpu 1 release 0x29000000 - - -;" \
  763. "cpu 2 release 0x29000000 - - -;" \
  764. "cpu 3 release 0x29000000 - - -;" \
  765. "cpu 4 release 0x29000000 - - -;" \
  766. "cpu 5 release 0x29000000 - - -;" \
  767. "cpu 6 release 0x29000000 - - -;" \
  768. "cpu 7 release 0x29000000 - - -;" \
  769. "go 0x29000000"
  770. #define CONFIG_HVBOOT \
  771. "setenv bootargs config-addr=0x60000000; " \
  772. "bootm 0x01000000 - 0x00f00000"
  773. #define CONFIG_ALU \
  774. "setenv bootargs root=/dev/$bdev rw " \
  775. "console=$consoledev,$baudrate $othbootargs;" \
  776. "cpu 1 release 0x01000000 - - -;" \
  777. "cpu 2 release 0x01000000 - - -;" \
  778. "cpu 3 release 0x01000000 - - -;" \
  779. "cpu 4 release 0x01000000 - - -;" \
  780. "cpu 5 release 0x01000000 - - -;" \
  781. "cpu 6 release 0x01000000 - - -;" \
  782. "cpu 7 release 0x01000000 - - -;" \
  783. "go 0x01000000"
  784. #define CONFIG_LINUX \
  785. "setenv bootargs root=/dev/ram rw " \
  786. "console=$consoledev,$baudrate $othbootargs;" \
  787. "setenv ramdiskaddr 0x02000000;" \
  788. "setenv fdtaddr 0x00c00000;" \
  789. "setenv loadaddr 0x1000000;" \
  790. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  791. #define CONFIG_HDBOOT \
  792. "setenv bootargs root=/dev/$bdev rw " \
  793. "console=$consoledev,$baudrate $othbootargs;" \
  794. "tftp $loadaddr $bootfile;" \
  795. "tftp $fdtaddr $fdtfile;" \
  796. "bootm $loadaddr - $fdtaddr"
  797. #define CONFIG_NFSBOOTCOMMAND \
  798. "setenv bootargs root=/dev/nfs rw " \
  799. "nfsroot=$serverip:$rootpath " \
  800. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  801. "console=$consoledev,$baudrate $othbootargs;" \
  802. "tftp $loadaddr $bootfile;" \
  803. "tftp $fdtaddr $fdtfile;" \
  804. "bootm $loadaddr - $fdtaddr"
  805. #define CONFIG_RAMBOOTCOMMAND \
  806. "setenv bootargs root=/dev/ram rw " \
  807. "console=$consoledev,$baudrate $othbootargs;" \
  808. "tftp $ramdiskaddr $ramdiskfile;" \
  809. "tftp $loadaddr $bootfile;" \
  810. "tftp $fdtaddr $fdtfile;" \
  811. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  812. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  813. #include <asm/fsl_secure_boot.h>
  814. #endif /* __T208xQDS_H */