cyrus.c 2.1 KB

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  1. /*
  2. * Based on corenet_ds.c
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <netdev.h>
  9. #include <linux/compiler.h>
  10. #include <asm/mmu.h>
  11. #include <asm/processor.h>
  12. #include <asm/cache.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_law.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <asm/fsl_portals.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <fm_eth.h>
  19. #include <pci.h>
  20. #include "cyrus.h"
  21. #include "../common/eeprom.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define GPIO_OPENDRAIN 0x30000000
  24. #define GPIO_DIR 0x3c000004
  25. #define GPIO_INITIAL 0x30000000
  26. #define GPIO_VGA_SWITCH 0x00001000
  27. int checkboard(void)
  28. {
  29. printf("Board: CYRUS\n");
  30. return 0;
  31. }
  32. int board_early_init_f(void)
  33. {
  34. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  36. /*
  37. * Only use DDR1_MCK0/3 and DDR2_MCK0/3
  38. * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  39. * the noise introduced by these unterminated and unused clock pairs.
  40. */
  41. setbits_be32(&gur->ddrclkdr, 0x001B001B);
  42. /* Set GPIO reset lines to open-drain, tristate */
  43. setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
  44. setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
  45. /* Set GPIO Direction */
  46. setbits_be32(&pgpio->gpdir, GPIO_DIR);
  47. return 0;
  48. }
  49. int board_early_init_r(void)
  50. {
  51. fsl_lbc_t *lbc = LBC_BASE_ADDR;
  52. out_be32(&lbc->lbcr, 0);
  53. /* 1 clock LALE cycle */
  54. out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
  55. set_liodns();
  56. #ifdef CONFIG_SYS_DPAA_QBMAN
  57. setup_portals();
  58. #endif
  59. print_lbc_regs();
  60. return 0;
  61. }
  62. int misc_init_r(void)
  63. {
  64. return 0;
  65. }
  66. int ft_board_setup(void *blob, bd_t *bd)
  67. {
  68. phys_addr_t base;
  69. phys_size_t size;
  70. ft_cpu_setup(blob, bd);
  71. base = getenv_bootm_low();
  72. size = getenv_bootm_size();
  73. fdt_fixup_memory(blob, (u64)base, (u64)size);
  74. #ifdef CONFIG_PCI
  75. pci_of_setup(blob, bd);
  76. #endif
  77. fdt_fixup_liodn(blob);
  78. fsl_fdt_fixup_dr_usb(blob, bd);
  79. #ifdef CONFIG_SYS_DPAA_FMAN
  80. fdt_fixup_fman_ethernet(blob);
  81. #endif
  82. return 0;
  83. }
  84. int mac_read_from_eeprom(void)
  85. {
  86. init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
  87. CONFIG_SYS_I2C_EEPROM_ADDR,
  88. CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
  89. return mac_read_from_eeprom_common();
  90. }