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csu3_am335x
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board-support
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u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
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board
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timll
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devkit8000
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devkit8000.h

devkit8000.h 21 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2008
    3. 

  3.  * Dirk Behme <dirk.behme@gmail.com>
    4. 

  4.  *
    5. 

  5.  * (C) Copyright 2009
    6. 

  6.  * Frederik Kriewitz <frederik@kriewitz.eu>
    7. 

  7.  *
    8. 

  8.  * SPDX-License-Identifier:	GPL-2.0+
    9. 

  9.  */
    10. 

  10. #ifndef _DEVKIT8000_H_
    11. 

  11. #define _DEVKIT8000_H_
    12. 

  12. 

  13. const omap3_sysinfo sysinfo = {
    14. 

  14. 	DDR_STACKED,
    15. 

  15. 	"OMAP3 DevKit8000",
    16. 

  16. 	"NAND",
    17. 

  17. };
    18. 

  18. 

  19. /* GPIO used to select between U-Boot and kernel */
    20. 

  20. #define SPL_OS_BOOT_KEY	26
    21. 

  21. 

  22. /*
    23. 

  23.  * IEN  - Input Enable
    24. 

  24.  * IDIS - Input Disable
    25. 

  25.  * PTD  - Pull type Down
    26. 

  26.  * PTU  - Pull type Up
    27. 

  27.  * DIS  - Pull type selection is inactive
    28. 

  28.  * EN   - Pull type selection is active
    29. 

  29.  * M0   - Mode 0
    30. 

  30.  * The commented string gives the final mux configuration for that pin
    31. 

  31.  */
    32. 

  32. 

  33. #define MUX_DEVKIT8000() \
    34. 

  34.  /* SDRC */\
    35. 

  35. 	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
    36. 

  36. 	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
    37. 

  37. 	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
    38. 

  38. 	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
    39. 

  39. 	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
    40. 

  40. 	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
    41. 

  41. 	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
    42. 

  42. 	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
    43. 

  43. 	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
    44. 

  44. 	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
    45. 

  45. 	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
    46. 

  46. 	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
    47. 

  47. 	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
    48. 

  48. 	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
    49. 

  49. 	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
    50. 

  50. 	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
    51. 

  51. 	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
    52. 

  52. 	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
    53. 

  53. 	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
    54. 

  54. 	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
    55. 

  55. 	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
    56. 

  56. 	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
    57. 

  57. 	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
    58. 

  58. 	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
    59. 

  59. 	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
    60. 

  60. 	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
    61. 

  61. 	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
    62. 

  62. 	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
    63. 

  63. 	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
    64. 

  64. 	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
    65. 

  65. 	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
    66. 

  66. 	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
    67. 

  67. 	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
    68. 

  68. 	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
    69. 

  69. 	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
    70. 

  70. 	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
    71. 

  71. 	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
    72. 

  72.  /* GPMC */\
    73. 

  73. 	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
    74. 

  74. 	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
    75. 

  75. 	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
    76. 

  76. 	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
    77. 

  77. 	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
    78. 

  78. 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
    79. 

  79. 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
    80. 

  80. 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
    81. 

  81. 	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
    82. 

  82. 	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
    83. 

  83. 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
    84. 

  84. 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
    85. 

  85. 	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
    86. 

  86. 	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
    87. 

  87. 	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
    88. 

  88. 	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
    89. 

  89. 	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
    90. 

  90. 	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
    91. 

  91. 	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
    92. 

  92. 	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
    93. 

  93. 	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
    94. 

  94. 	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
    95. 

  95. 	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
    96. 

  96. 	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
    97. 

  97. 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
    98. 

  98. 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
    99. 

  99. 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
    100. 

  100. 	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
    101. 

  101. 	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
    102. 

  102. 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
    103. 

  103. 	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
    104. 

  104. 	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
    105. 

  105. 	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS6 DM9000*/\
    106. 

  106. 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
    107. 

  107. 	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
    108. 

  108. 	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
    109. 

  109. 	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
    110. 

  110. 	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
    111. 

  111. 	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
    112. 

  112. 	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
    113. 

  113. 	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
    114. 

  114. 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
    115. 

  115. 	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
    116. 

  116. 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
    117. 

  117. 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
    118. 

  118.  /* DSS */\
    119. 

  119. 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
    120. 

  120. 	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
    121. 

  121. 	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
    122. 

  122. 	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
    123. 

  123. 	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
    124. 

  124. 	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
    125. 

  125. 	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
    126. 

  126. 	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
    127. 

  127. 	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
    128. 

  128. 	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
    129. 

  129. 	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
    130. 

  130. 	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
    131. 

  131. 	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
    132. 

  132. 	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
    133. 

  133. 	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
    134. 

  134. 	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
    135. 

  135. 	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
    136. 

  136. 	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
    137. 

  137. 	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
    138. 

  138. 	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
    139. 

  139. 	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
    140. 

  140. 	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
    141. 

  141. 	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
    142. 

  142. 	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
    143. 

  143. 	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
    144. 

  144. 	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
    145. 

  145. 	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
    146. 

  146. 	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
    147. 

  147.  /* CAMERA */\
    148. 

  148. 	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
    149. 

  149. 	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
    150. 

  150. 	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
    151. 

  151. 	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
    152. 

  152. 	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
    153. 

  153. 	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
    154. 

  154. 	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
    155. 

  155. 	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
    156. 

  156. 	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
    157. 

  157. 	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
    158. 

  158. 	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
    159. 

  159. 	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
    160. 

  160. 	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
    161. 

  161. 	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
    162. 

  162. 	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
    163. 

  163. 	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
    164. 

  164. 	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
    165. 

  165. 	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
    166. 

  166. 	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
    167. 

  167. 	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
    168. 

  168. 	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
    169. 

  169. 	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
    170. 

  170. 	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
    171. 

  171. 	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
    172. 

  172.  /* Audio Interface */\
    173. 

  173. 	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
    174. 

  174. 	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
    175. 

  175. 	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
    176. 

  176. 	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
    177. 

  177.  /* MMC Slot */\
    178. 

  178. 	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
    179. 

  179. 	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
    180. 

  180. 	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
    181. 

  181. 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
    182. 

  182. 	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
    183. 

  183. 	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
    184. 

  184. 	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
    185. 

  185. 	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
    186. 

  186. 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
    187. 

  187. 	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
    188. 

  188.  /* Expansion Header */\
    189. 

  189. 	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
    190. 

  190. 	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
    191. 

  191. 	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
    192. 

  192. 	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
    193. 

  193. 	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
    194. 

  194. 	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
    195. 

  195. 	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
    196. 

  196. 	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
    197. 

  197. 	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
    198. 

  198. 	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
    199. 

  199. 	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_140*/\
    200. 

  200. 	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_141*/\
    201. 

  201. 	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_142*/\
    202. 

  202. 	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_143*/\
    203. 

  203. 	MUX_VAL(CP(UART2_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_144*/\
    204. 

  204. 	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_145*/\
    205. 

  205. 	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M4)) /*GPIO_146*/\
    206. 

  206. 	MUX_VAL(CP(UART2_RX),		(IDIS | PTD | DIS | M4)) /*GPIO_147*/\
    207. 

  207. 	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*GPIO_148*/\
    208. 

  208. 	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
    209. 

  209. 	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
    210. 

  210. 	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*GPIO_151*/\
    211. 

  211. 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*GPIO_152*/\
    212. 

  212. 	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*GPIO_153*/\
    213. 

  213. 	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*GPIO_154*/\
    214. 

  214. 	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*GPIO_155*/\
    215. 

  215. 	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
    216. 

  216. 	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
    217. 

  217. 	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
    218. 

  218. 	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
    219. 

  219. 	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*GPIO_160*/\
    220. 

  220. 	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
    221. 

  221. 	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
    222. 

  222.  /* Serial Interface */\
    223. 

  223. 	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
    224. 

  224. 	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
    225. 

  225. 	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
    226. 

  226. 	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
    227. 

  227.  /* Host USB0 */\
    228. 

  228. 	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
    229. 

  229. 	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
    230. 

  230. 	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
    231. 

  231. 	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
    232. 

  232. 	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
    233. 

  233. 	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
    234. 

  234. 	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
    235. 

  235. 	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
    236. 

  236. 	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
    237. 

  237. 	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
    238. 

  238. 	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
    239. 

  239. 	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
    240. 

  240. 	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
    241. 

  241. 	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
    242. 

  242. 	MUX_VAL(CP(I2C2_SCL),		(IDIS | PTU | DIS | M4)) /*GPIO_168*/\
    243. 

  243. 	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
    244. 

  244. 	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
    245. 

  245. 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
    246. 

  246. 	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
    247. 

  247. 	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | DIS | M0)) /*I2C4_SDA*/\
    248. 

  248. 	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTD | DIS | M4)) /*GPIO_170*/\
    249. 

  249. 	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M4)) /*GPIO_171*/\
    250. 

  250. 	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M4)) /*GPIO_172*/\
    251. 

  251. 	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
    252. 

  252. 	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
    253. 

  253. 	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
    254. 

  254. 	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
    255. 

  255.  /* USB EHCI (port 2) */\
    256. 

  256. 	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
    257. 

  257. 	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
    258. 

  258. 	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
    259. 

  259. 	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
    260. 

  260. 	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
    261. 

  261. 	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
    262. 

  262.  /*Control and debug */\
    263. 

  263. 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
    264. 

  264. 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
    265. 

  265. 	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
    266. 

  266. 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
    267. 

  267. 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
    268. 

  268. 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
    269. 

  269. 	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
    270. 

  270. 	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
    271. 

  271. 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
    272. 

  272. 	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
    273. 

  273. 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
    274. 

  274. 	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
    275. 

  275. 	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
    276. 

  276. 	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
    277. 

  277. 	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | EN  | M3)) /*HSUSB1_CLK*/\
    278. 

  278. 	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA0*/\
    279. 

  279. 	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA1*/\
    280. 

  280. 	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA2*/\
    281. 

  281. 	MUX_VAL(CP(ETK_D3_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA7*/\
    282. 

  282. 	MUX_VAL(CP(ETK_D4_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA4*/\
    283. 

  283. 	MUX_VAL(CP(ETK_D5_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA5*/\
    284. 

  284. 	MUX_VAL(CP(ETK_D6_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA6*/\
    285. 

  285. 	MUX_VAL(CP(ETK_D7_ES2),		(IDIS | PTU | EN  | M3)) /*HSUSB1_DATA3*/\
    286. 

  286. 	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_DIR*/\
    287. 

  287. 	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M3)) /*HSUSB1_NXT*/\
    288. 

  288. 	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | EN  | M4)) /*GPIO_24*/\
    289. 

  289. 	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_25*/\
    290. 

  290. 	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_26*/\
    291. 

  291. 	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_27*/\
    292. 

  292. 	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_28*/\
    293. 

  293. 	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | EN  | M4)) /*GPIO_29*/\
    294. 

  294. 	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
    295. 

  295. 	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
    296. 

  296. 	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
    297. 

  297. 	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
    298. 

  298. 	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
    299. 

  299. 	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
    300. 

  300. 	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
    301. 

  301. 	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
    302. 

  302. 	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
    303. 

  303. 	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
    304. 

  304. 	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
    305. 

  305. 	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
    306. 

  306. 	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
    307. 

  307. 	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
    308. 

  308. 	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
    309. 

  309. 	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
    310. 

  310. 	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
    311. 

  311. 	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
    312. 

  312. 	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
    313. 

  313. 	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
    314. 

  314. 	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
    315. 

  315. 	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
    316. 

  316. 	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
    317. 

  317. 	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
    318. 

  318. 	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
    319. 

  319. 	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
    320. 

  320. 	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
    321. 

  321. 	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
    322. 

  322. 	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
    323. 

  323. 	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
    324. 

  324. 	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
    325. 

  325. 	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
    326. 

  326. 	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
    327. 

  327. 	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
    328. 

  328. 	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
    329. 

  329. 	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
    330. 

  330. 	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
    331. 

  331. 	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
    332. 

  332. 	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
    333. 

  333. 	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
    334. 

  334. 	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
    335. 

  335. 	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*D2D_spint*/\
    336. 

  336. 	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*D2D_frint*/\
    337. 

  337. 	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
    338. 

  338. 	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
    339. 

  339. 	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
    340. 

  340. 	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
    341. 

  341. 	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
    342. 

  342. 	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
    343. 

  343. 	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
    344. 

  344. 	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
    345. 

  345. 	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
    346. 

  346. 	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
    347. 

  347. 	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
    348. 

  348. 	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
    349. 

  349. 	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
    350. 

  350. 	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
    351. 

  351. 	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
    352. 

  352. 	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
    353. 

  353. 	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*D2D_mread*/\
    354. 

  354. 	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*D2D_sread*/\
    355. 

  355. 	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
    356. 

  356. 	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
    357. 

  357. 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
    358. 

  358. 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
    359. 

  359. 

  360. #endif
    361.