board.c 3.9 KB

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  1. /*
  2. * Board functions for IGEP COM AQUILA based boards
  3. *
  4. * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <spl.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/omap.h>
  14. #include <asm/arch/ddr_defs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/mmc_host_def.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/io.h>
  20. #include <asm/emif.h>
  21. #include <asm/gpio.h>
  22. #include <i2c.h>
  23. #include <miiphy.h>
  24. #include <cpsw.h>
  25. #include "board.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  28. #ifdef CONFIG_SPL_BUILD
  29. static const struct ddr_data ddr3_data = {
  30. .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  31. .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  32. .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  33. .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  34. };
  35. static const struct cmd_control ddr3_cmd_ctrl_data = {
  36. .cmd0csratio = K4B2G1646EBIH9_RATIO,
  37. .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  38. .cmd1csratio = K4B2G1646EBIH9_RATIO,
  39. .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  40. .cmd2csratio = K4B2G1646EBIH9_RATIO,
  41. .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  42. };
  43. static struct emif_regs ddr3_emif_reg_data = {
  44. .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  45. .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  46. .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  47. .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  48. .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  49. .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  50. .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  51. };
  52. #define OSC (V_OSCK/1000000)
  53. const struct dpll_params dpll_ddr = {
  54. 400, OSC-1, 1, -1, -1, -1, -1};
  55. const struct dpll_params *get_dpll_ddr_params(void)
  56. {
  57. return &dpll_ddr;
  58. }
  59. void set_uart_mux_conf(void)
  60. {
  61. enable_uart0_pin_mux();
  62. }
  63. void set_mux_conf_regs(void)
  64. {
  65. enable_board_pin_mux();
  66. }
  67. const struct ctrl_ioregs ioregs = {
  68. .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  69. .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  70. .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  71. .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  72. .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  73. };
  74. void sdram_init(void)
  75. {
  76. config_ddr(400, &ioregs, &ddr3_data,
  77. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  78. }
  79. #endif
  80. /*
  81. * Basic board specific setup. Pinmux has been handled already.
  82. */
  83. int board_init(void)
  84. {
  85. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  86. gpmc_init();
  87. return 0;
  88. }
  89. #if defined(CONFIG_DRIVER_TI_CPSW)
  90. static void cpsw_control(int enabled)
  91. {
  92. /* VTP can be added here */
  93. return;
  94. }
  95. static struct cpsw_slave_data cpsw_slaves[] = {
  96. {
  97. .slave_reg_ofs = 0x208,
  98. .sliver_reg_ofs = 0xd80,
  99. .phy_addr = 0,
  100. .phy_if = PHY_INTERFACE_MODE_RMII,
  101. },
  102. };
  103. static struct cpsw_platform_data cpsw_data = {
  104. .mdio_base = CPSW_MDIO_BASE,
  105. .cpsw_base = CPSW_BASE,
  106. .mdio_div = 0xff,
  107. .channels = 8,
  108. .cpdma_reg_ofs = 0x800,
  109. .slaves = 1,
  110. .slave_data = cpsw_slaves,
  111. .ale_reg_ofs = 0xd00,
  112. .ale_entries = 1024,
  113. .host_port_reg_ofs = 0x108,
  114. .hw_stats_reg_ofs = 0x900,
  115. .bd_ram_ofs = 0x2000,
  116. .mac_control = (1 << 5),
  117. .control = cpsw_control,
  118. .host_port_num = 0,
  119. .version = CPSW_CTRL_VERSION_2,
  120. };
  121. int board_eth_init(bd_t *bis)
  122. {
  123. int rv, ret = 0;
  124. uint8_t mac_addr[6];
  125. uint32_t mac_hi, mac_lo;
  126. if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
  127. /* try reading mac address from efuse */
  128. mac_lo = readl(&cdev->macid0l);
  129. mac_hi = readl(&cdev->macid0h);
  130. mac_addr[0] = mac_hi & 0xFF;
  131. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  132. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  133. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  134. mac_addr[4] = mac_lo & 0xFF;
  135. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  136. if (is_valid_ethaddr(mac_addr))
  137. eth_setenv_enetaddr("ethaddr", mac_addr);
  138. }
  139. writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
  140. &cdev->miisel);
  141. rv = cpsw_register(&cpsw_data);
  142. if (rv < 0)
  143. printf("Error %d registering CPSW switch\n", rv);
  144. else
  145. ret += rv;
  146. return ret;
  147. }
  148. #endif