ddr.h 2.3 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __DDR_H__
  7. #define __DDR_H__
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. };
  17. /*
  18. * These tables contain all valid speeds we want to override with board
  19. * specific parameters. datarate_mhz_high values need to be in ascending order
  20. * for each n_ranks group.
  21. */
  22. static const struct board_specific_parameters udimm0[] = {
  23. /*
  24. * memory controller 0
  25. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  26. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  27. */
  28. {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
  29. {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
  30. {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
  31. {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
  32. {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
  33. {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
  34. {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
  35. {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
  36. {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
  37. {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
  38. {}
  39. };
  40. static const struct board_specific_parameters rdimm0[] = {
  41. /*
  42. * memory controller 0
  43. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  44. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  45. */
  46. {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  47. {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
  48. {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
  49. {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  50. {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
  51. {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
  52. {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  53. {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
  54. {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
  55. {}
  56. };
  57. /*
  58. * The three slots have slightly different timing. The center values are good
  59. * for all slots. We use identical speed tables for them. In future use, if
  60. * DIMMs require separated tables, make more entries as needed.
  61. */
  62. static const struct board_specific_parameters *udimms[] = {
  63. udimm0,
  64. };
  65. /*
  66. * The three slots have slightly different timing. See comments above.
  67. */
  68. static const struct board_specific_parameters *rdimms[] = {
  69. rdimm0,
  70. };
  71. #endif