diu.c 2.1 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <command.h>
  10. #include <fsl_diu_fb.h>
  11. #include <linux/ctype.h>
  12. #include <video_fb.h>
  13. #include "../common/diu_ch7301.h"
  14. #include "cpld.h"
  15. #include "t104xrdb.h"
  16. /*
  17. * DIU Area Descriptor
  18. *
  19. * Note that we need to byte-swap the value before it's written to the AD
  20. * register. So even though the registers don't look like they're in the same
  21. * bit positions as they are on the MPC8610, the same value is written to the
  22. * AD register on the MPC8610 and on the P1022.
  23. */
  24. #define AD_BYTE_F 0x10000000
  25. #define AD_ALPHA_C_SHIFT 25
  26. #define AD_BLUE_C_SHIFT 23
  27. #define AD_GREEN_C_SHIFT 21
  28. #define AD_RED_C_SHIFT 19
  29. #define AD_PIXEL_S_SHIFT 16
  30. #define AD_COMP_3_SHIFT 12
  31. #define AD_COMP_2_SHIFT 8
  32. #define AD_COMP_1_SHIFT 4
  33. #define AD_COMP_0_SHIFT 0
  34. void diu_set_pixel_clock(unsigned int pixclock)
  35. {
  36. unsigned long speed_ccb, temp;
  37. u32 pixval;
  38. int ret;
  39. speed_ccb = get_bus_freq(0);
  40. temp = 1000000000 / pixclock;
  41. temp *= 1000;
  42. pixval = speed_ccb / temp;
  43. /* Program HDMI encoder */
  44. ret = diu_set_dvi_encoder(temp);
  45. if (ret) {
  46. puts("Failed to set DVI encoder\n");
  47. return;
  48. }
  49. /* Program pixel clock */
  50. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  51. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  52. /* enable clock*/
  53. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  54. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  55. }
  56. int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  57. {
  58. u32 pixel_format;
  59. u8 sw;
  60. /*Configure Display ouput port as HDMI*/
  61. sw = CPLD_READ(sfp_ctl_status);
  62. CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
  63. pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  64. (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  65. (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  66. (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  67. (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  68. printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
  69. return fsl_diu_init(xres, yres, pixel_format, 0);
  70. }