csu3_am335x/board-support/u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04/board/freescale/mx51evk/imximage.cfg

/*
 * (C Copyright 2009
 * Stefano Babic DENX Software Engineering sbabic@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer doc/README.imximage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

/*
 * Boot Device : one of
 * spi, sd (the board has no nand neither onenand)
 */
BOOT_FROM	spi

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
DATA 4 0x73FA883c 0x2
DATA 4 0x73FA8848 0x2
DATA 4 0x73FA84b8 0xe7
DATA 4 0x73FA84bc 0x45
DATA 4 0x73FA84c0 0x45
DATA 4 0x73FA84c4 0x45
DATA 4 0x73FA84c8 0x45
DATA 4 0x73FA8820 0x0
DATA 4 0x73FA84a4 0x3
DATA 4 0x73FA84a8 0x3
DATA 4 0x73FA84ac 0xe3
DATA 4 0x73FA84b0 0xe3
DATA 4 0x73FA84b4 0xe3
DATA 4 0x73FA84cc 0xe3
DATA 4 0x73FA84d0 0xe2

DATA 4 0x73FA882c 0x6
DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6

/*
 * Setting DDR for micron
 * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
 * CAS=3 BL=4
 */
/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa

/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
DATA 4 0x83FD9014 0x00448019
DATA 4 0x83FD9014 0x07328018
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x00008010
DATA 4 0x83FD9014 0x06328018
DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000

/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
DATA 4 0x83FD9014 0x0000801d
DATA 4 0x83FD9014 0x0732801c
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x00008014
DATA 4 0x83FD9014 0x0632801c
DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004

/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000