mx31ads.c 2.7 KB

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  1. /*
  2. * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <netdev.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/sys_proto.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. int dram_init(void)
  14. {
  15. /* dram_init must store complete ramsize in gd->ram_size */
  16. gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  17. PHYS_SDRAM_1_SIZE);
  18. return 0;
  19. }
  20. int board_early_init_f(void)
  21. {
  22. int i;
  23. /* CS0: Nor Flash */
  24. /*
  25. * CS0L and CS0A values are from the RedBoot sources by Freescale
  26. * and are also equal to those used by Sascha Hauer for the Phytec
  27. * i.MX31 board. CS0U is just a slightly optimized hardware default:
  28. * the only non-zero field "Wait State Control" is set to half the
  29. * default value.
  30. */
  31. static const struct mxc_weimcs cs0 = {
  32. /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  33. CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
  34. /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  35. CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
  36. /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  37. CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
  38. };
  39. mxc_setup_weimcs(0, &cs0);
  40. /* setup pins for UART1 */
  41. mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  42. mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  43. mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  44. mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  45. /* SPI2 */
  46. mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
  47. mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
  48. mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
  49. mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
  50. mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
  51. mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
  52. mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
  53. /* start SPI2 clock */
  54. __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
  55. /* PBC setup */
  56. /* Enable UART transceivers also reset the Ethernet/external UART */
  57. readw(CS4_BASE + 4);
  58. writew(0x8023, CS4_BASE + 4);
  59. /* RedBoot also has an empty loop with 100000 iterations here -
  60. * clock doesn't run yet */
  61. for (i = 0; i < 100000; i++)
  62. ;
  63. /* Clear the reset, toggle the LEDs */
  64. writew(0xDF, CS4_BASE + 6);
  65. /* clock still doesn't run */
  66. for (i = 0; i < 100000; i++)
  67. ;
  68. /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
  69. readb(CS4_BASE + 8);
  70. readb(CS4_BASE + 7);
  71. readb(CS4_BASE + 8);
  72. readb(CS4_BASE + 7);
  73. return 0;
  74. }
  75. int board_init(void)
  76. {
  77. gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
  78. return 0;
  79. }
  80. int checkboard(void)
  81. {
  82. printf("Board: MX31ADS\n");
  83. return 0;
  84. }
  85. #ifdef CONFIG_CMD_NET
  86. int board_eth_init(bd_t *bis)
  87. {
  88. int rc = 0;
  89. #ifdef CONFIG_CS8900
  90. rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
  91. #endif
  92. return rc;
  93. }
  94. #endif