ddr.c 1.3 KB

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  1. /*
  2. * Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. void fsl_ddr_board_options(memctl_options_t *popts,
  10. dimm_params_t *pdimm,
  11. unsigned int ctrl_num)
  12. {
  13. /*
  14. * Factors to consider for clock adjust:
  15. * - number of chips on bus
  16. * - position of slot
  17. * - DDR1 vs. DDR2?
  18. * - ???
  19. *
  20. * This needs to be determined on a board-by-board basis.
  21. * 0110 3/4 cycle late
  22. * 0111 7/8 cycle late
  23. */
  24. popts->clk_adjust = 4;
  25. /*
  26. * Factors to consider for CPO:
  27. * - frequency
  28. * - ddr1 vs. ddr2
  29. */
  30. popts->cpo_override = 0xff;
  31. /*
  32. * Factors to consider for write data delay:
  33. * - number of DIMMs
  34. *
  35. * 1 = 1/4 clock delay
  36. * 2 = 1/2 clock delay
  37. * 3 = 3/4 clock delay
  38. * 4 = 1 clock delay
  39. * 5 = 5/4 clock delay
  40. * 6 = 3/2 clock delay
  41. */
  42. popts->write_data_delay = 2;
  43. /*
  44. * Enable half drive strength
  45. */
  46. popts->half_strength_driver_enable = 1;
  47. /* Write leveling override */
  48. popts->wrlvl_en = 1;
  49. popts->wrlvl_override = 1;
  50. popts->wrlvl_sample = 0xa;
  51. popts->wrlvl_start = 0x4;
  52. /* Rtt and Rtt_W override */
  53. popts->rtt_override = 1;
  54. popts->rtt_override_value = DDR3_RTT_60_OHM;
  55. popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
  56. }