README 3.2 KB

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  1. Overview
  2. =========
  3. C29XPCIE board is a series of Freescale PCIe add-in cards to perform
  4. as public key crypto accelerator or secure key management module.
  5. It includes C293PCIE board, C293PCIE board and C291PCIE board.
  6. The Freescale C29x family is a high performance crypto co-processor.
  7. It combines a single e500v2 core with necessary SEC engines.
  8. (maximum core frequency 1000/1200 MHz).
  9. The C29xPCIE board features are as follows:
  10. Memory subsystem:
  11. - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
  12. - 64 Mbyte NOR flash single-chip memory
  13. - 4 Gbyte NAND flash memory
  14. - 1 Mbit AT24C1024 I2C EEPROM
  15. - 16 Mbyte SPI memory
  16. Interfaces:
  17. - 10/100/1000 BaseT Ethernet ports:
  18. - eTSEC1, RGMII: one 10/100/1000 port
  19. - eTSEC2, RGMII: one 10/100/1000 port
  20. - DUART interface:
  21. - DUART interface: supports two UARTs up to 115200 bps for
  22. console display
  23. Board connectors:
  24. - Mini-ITX power supply connector
  25. - JTAG/COP for debugging
  26. Physical Memory Map on C29xPCIE
  27. ===============================
  28. Address Start Address End Memory type
  29. 0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
  30. 0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
  31. 0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
  32. 0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
  33. 0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
  34. 0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
  35. 0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
  36. Serial Port Configuration on C29xPCIE
  37. =====================================
  38. Configure the serial port of the attached computer with the following values:
  39. -Data rate: 115200 bps
  40. -Number of data bits: 8
  41. -Parity: None
  42. -Number of Stop bits: 1
  43. -Flow Control: Hardware/None
  44. Settings of DIP-switch
  45. ======================
  46. SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
  47. SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
  48. Note: 1 stands for 'off', 0 stands for 'on'
  49. Build and program U-Boot to NOR flash
  50. ==================================
  51. 1. Build u-boot.bin image example:
  52. export ARCH=powerpc
  53. export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
  54. make C293PCIE
  55. 2. Program u-boot.bin into NOR flash
  56. => tftp $loadaddr $uboot
  57. => protect off eff40000 +$filesize
  58. => erase eff40000 +$filesize
  59. => cp.b $loadaddr eff40000 $filesize
  60. 3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
  61. Alternate NOR bank
  62. ==================
  63. There are four banks in C29XPCIE board, example to change bank booting:
  64. 1. Program u-boot.bin into alternate NOR bank
  65. => tftp $loadaddr $uboot
  66. => protect off e9f40000 +$filesize
  67. => erase e9f40000 +$filesize
  68. => cp.b $loadaddr e9f40000 $filesize
  69. 2. Switch to alternate NOR bank
  70. => cpld_cmd reset altbank [bank]
  71. - [bank] bank value select 1-4
  72. - bank 1 on the flash 0x0000000~0x0ffffff
  73. - bank 2 on the flash 0x1000000~0x1ffffff
  74. - bank 3 on the flash 0x2000000~0x2ffffff
  75. - bank 4 on the flash 0x3000000~0x3ffffff
  76. or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
  77. Build and program U-Boot to SPI flash
  78. ==================================
  79. 1. Build u-boot-spi.bin image
  80. make C29xPCIE_SPIFLASH_config; make
  81. Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
  82. 2. Program u-boot-spi.bin into SPI flash
  83. => tftp $loadaddr $uboot-spi
  84. => sf erase 0 100000
  85. => sf write $loadaddr 0 $filesize
  86. 3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.