dbau1x00.c 2.9 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Thomas.Lange@corelatus.se
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <mach/au1x00.h>
  10. #include <asm/mipsregs.h>
  11. #include <asm/io.h>
  12. phys_size_t initdram(int board_type)
  13. {
  14. /* Sdram is setup by assembler code */
  15. /* If memory could be changed, we should return the true value here */
  16. return MEM_SIZE*1024*1024;
  17. }
  18. #define BCSR_PCMCIA_PC0DRVEN 0x0010
  19. #define BCSR_PCMCIA_PC0RST 0x0080
  20. /* In arch/mips/cpu/cpu.c */
  21. void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
  22. int checkboard (void)
  23. {
  24. #ifdef CONFIG_IDE_PCMCIA
  25. u16 status;
  26. volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
  27. #endif /* CONFIG_IDE_PCMCIA */
  28. volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
  29. volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
  30. u32 proc_id;
  31. *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
  32. proc_id = read_c0_prid();
  33. switch (proc_id >> 24) {
  34. case 0:
  35. puts ("Board: Merlot (DbAu1000)\n");
  36. printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
  37. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  38. break;
  39. case 1:
  40. puts ("Board: DbAu1500\n");
  41. printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
  42. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  43. break;
  44. case 2:
  45. puts ("Board: DbAu1100\n");
  46. printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
  47. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  48. break;
  49. case 3:
  50. puts ("Board: DbAu1550\n");
  51. printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
  52. (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  53. break;
  54. default:
  55. printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
  56. }
  57. set_io_port_base(0);
  58. #ifdef CONFIG_IDE_PCMCIA
  59. /* Enable 3.3 V on slot 0 ( VCC )
  60. No 5V */
  61. status = 4;
  62. *pcmcia_bcsr = status;
  63. status |= BCSR_PCMCIA_PC0DRVEN;
  64. *pcmcia_bcsr = status;
  65. au_sync();
  66. udelay(300*1000);
  67. status |= BCSR_PCMCIA_PC0RST;
  68. *pcmcia_bcsr = status;
  69. au_sync();
  70. udelay(100*1000);
  71. /* PCMCIA is on a 36 bit physical address.
  72. We need to map it into a 32 bit addresses */
  73. #if 0
  74. /* We dont need theese unless we run whole pcmcia package */
  75. write_one_tlb(20, /* index */
  76. 0x01ffe000, /* Pagemask, 16 MB pages */
  77. CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
  78. 0x3C000017, /* Lo0 */
  79. 0x3C200017); /* Lo1 */
  80. write_one_tlb(21, /* index */
  81. 0x01ffe000, /* Pagemask, 16 MB pages */
  82. CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
  83. 0x3D000017, /* Lo0 */
  84. 0x3D200017); /* Lo1 */
  85. #endif /* 0 */
  86. write_one_tlb(22, /* index */
  87. 0x01ffe000, /* Pagemask, 16 MB pages */
  88. CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
  89. 0x3E000017, /* Lo0 */
  90. 0x3E200017); /* Lo1 */
  91. #endif /* CONFIG_IDE_PCMCIA */
  92. /* Release reset of ethernet PHY chips */
  93. /* Always do this, because linux does not know about it */
  94. *phy = 3;
  95. return 0;
  96. }