123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960 |
- /*
- * Copyright (C) 2013 Boundary Devices
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /* ZQ Calibration */
- DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
- DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
- DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
- DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
- DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
- /*
- * DQS gating, read delay, write delay calibration values
- */
- DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
- DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
- DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
- DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
- DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
- DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
- DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
- DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
- /* read data bit delay */
- DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
- DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
- DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
- DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
- DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
- DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
- DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
- DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
- /* Complete calibration by forced measurment */
- DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
- DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
- /* in DDR3, 64-bit mode, only MMDC0 is initiated */
- DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
- DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
- DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
- DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
- DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
- DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
- DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
- DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
- DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
- DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
- DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
- DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
- DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
- DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
- DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
- DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
- /* final ddr setup */
- DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
- DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
- DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
- DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
- DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
- DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|