a4m072.c 11 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * (C) Copyright 2010
  9. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <mpc5xxx.h>
  15. #include <pci.h>
  16. #include <asm/processor.h>
  17. #include <asm/io.h>
  18. #include <libfdt.h>
  19. #include <netdev.h>
  20. #include <led-display.h>
  21. #include <linux/err.h>
  22. #include "mt46v32m16.h"
  23. #ifndef CONFIG_SYS_RAMBOOT
  24. static void sdram_start (int hi_addr)
  25. {
  26. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  27. long control = SDRAM_CONTROL | hi_addr_bit;
  28. /* unlock mode register */
  29. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  30. __asm__ volatile ("sync");
  31. /* precharge all banks */
  32. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  33. __asm__ volatile ("sync");
  34. #if SDRAM_DDR
  35. /* set mode register: extended mode */
  36. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
  37. __asm__ volatile ("sync");
  38. /* set mode register: reset DLL */
  39. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
  40. __asm__ volatile ("sync");
  41. #endif
  42. /* precharge all banks */
  43. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  44. __asm__ volatile ("sync");
  45. /* auto refresh */
  46. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  47. __asm__ volatile ("sync");
  48. /* set mode register */
  49. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  50. __asm__ volatile ("sync");
  51. /* normal operation */
  52. out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  53. __asm__ volatile ("sync");
  54. }
  55. #endif
  56. /*
  57. * ATTENTION: Although partially referenced initdram does NOT make real use
  58. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  59. * is something else than 0x00000000.
  60. */
  61. phys_size_t initdram (int board_type)
  62. {
  63. ulong dramsize = 0;
  64. uint svr, pvr;
  65. #ifndef CONFIG_SYS_RAMBOOT
  66. ulong test1, test2;
  67. /* setup SDRAM chip selects */
  68. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
  69. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
  70. __asm__ volatile ("sync");
  71. /* setup config registers */
  72. out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  73. out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  74. __asm__ volatile ("sync");
  75. #if SDRAM_DDR
  76. /* set tap delay */
  77. out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
  78. __asm__ volatile ("sync");
  79. #endif
  80. /* find RAM size using SDRAM CS0 only */
  81. sdram_start(0);
  82. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  83. sdram_start(1);
  84. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  85. if (test1 > test2) {
  86. sdram_start(0);
  87. dramsize = test1;
  88. } else {
  89. dramsize = test2;
  90. }
  91. /* memory smaller than 1MB is impossible */
  92. if (dramsize < (1 << 20)) {
  93. dramsize = 0;
  94. }
  95. /* set SDRAM CS0 size according to the amount of RAM found */
  96. if (dramsize > 0) {
  97. out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
  98. 0x13 + __builtin_ffs(dramsize >> 20) - 1);
  99. } else {
  100. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
  101. }
  102. #else /* CONFIG_SYS_RAMBOOT */
  103. /* retrieve size of memory connected to SDRAM CS0 */
  104. dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
  105. if (dramsize >= 0x13) {
  106. dramsize = (1 << (dramsize - 0x13)) << 20;
  107. } else {
  108. dramsize = 0;
  109. }
  110. #endif /* CONFIG_SYS_RAMBOOT */
  111. /*
  112. * On MPC5200B we need to set the special configuration delay in the
  113. * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
  114. * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
  115. *
  116. * "The SDelay should be written to a value of 0x00000004. It is
  117. * required to account for changes caused by normal wafer processing
  118. * parameters."
  119. */
  120. svr = get_svr();
  121. pvr = get_pvr();
  122. if ((SVR_MJREV(svr) >= 2) &&
  123. (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
  124. out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
  125. __asm__ volatile ("sync");
  126. }
  127. return dramsize;
  128. }
  129. int checkboard (void)
  130. {
  131. puts ("Board: A4M072\n");
  132. return 0;
  133. }
  134. #ifdef CONFIG_PCI
  135. static struct pci_controller hose;
  136. extern void pci_mpc5xxx_init(struct pci_controller *);
  137. void pci_init_board(void)
  138. {
  139. pci_mpc5xxx_init(&hose);
  140. }
  141. #endif
  142. #ifdef CONFIG_OF_BOARD_SETUP
  143. int ft_board_setup(void *blob, bd_t *bd)
  144. {
  145. ft_cpu_setup(blob, bd);
  146. return 0;
  147. }
  148. #endif /* CONFIG_OF_BOARD_SETUP */
  149. int board_eth_init(bd_t *bis)
  150. {
  151. int rv, num_if = 0;
  152. /* Initialize TSECs first */
  153. if ((rv = cpu_eth_init(bis)) >= 0)
  154. num_if += rv;
  155. else
  156. printf("ERROR: failed to initialize FEC.\n");
  157. if ((rv = pci_eth_init(bis)) >= 0)
  158. num_if += rv;
  159. else
  160. printf("ERROR: failed to initialize PCI Ethernet.\n");
  161. return num_if;
  162. }
  163. /*
  164. * Miscellaneous late-boot configurations
  165. *
  166. * Initialize EEPROM write-protect GPIO pin.
  167. */
  168. int misc_init_r(void)
  169. {
  170. #if defined(CONFIG_SYS_EEPROM_WREN)
  171. /* Enable GPIO pin */
  172. setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
  173. /* Set direction, output */
  174. setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
  175. /* De-assert write enable */
  176. setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
  177. #endif
  178. return 0;
  179. }
  180. #if defined(CONFIG_SYS_EEPROM_WREN)
  181. /* Input: <dev_addr> I2C address of EEPROM device to enable.
  182. * <state> -1: deliver current state
  183. * 0: disable write
  184. * 1: enable write
  185. * Returns: -1: wrong device address
  186. * 0: dis-/en- able done
  187. * 0/1: current state if <state> was -1.
  188. */
  189. int eeprom_write_enable (unsigned dev_addr, int state)
  190. {
  191. if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
  192. return -1;
  193. } else {
  194. switch (state) {
  195. case 1:
  196. /* Enable write access */
  197. clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
  198. state = 0;
  199. break;
  200. case 0:
  201. /* Disable write access */
  202. setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
  203. state = 0;
  204. break;
  205. default:
  206. /* Read current status back. */
  207. state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
  208. CONFIG_SYS_EEPROM_WP));
  209. break;
  210. }
  211. }
  212. return state;
  213. }
  214. #endif
  215. #ifdef CONFIG_CMD_DISPLAY
  216. #define DISPLAY_BUF_SIZE 2
  217. static u8 display_buf[DISPLAY_BUF_SIZE];
  218. static u8 display_putc_pos;
  219. static u8 display_out_pos;
  220. void display_set(int cmd) {
  221. if (cmd & DISPLAY_CLEAR) {
  222. display_buf[0] = display_buf[1] = 0;
  223. }
  224. if (cmd & DISPLAY_HOME) {
  225. display_putc_pos = 0;
  226. }
  227. }
  228. #define SEG_A (1<<0)
  229. #define SEG_B (1<<1)
  230. #define SEG_C (1<<2)
  231. #define SEG_D (1<<3)
  232. #define SEG_E (1<<4)
  233. #define SEG_F (1<<5)
  234. #define SEG_G (1<<6)
  235. #define SEG_P (1<<7)
  236. #define SEG__ 0
  237. /*
  238. * +- A -+
  239. * | |
  240. * F B
  241. * | |
  242. * +- G -+
  243. * | |
  244. * E C
  245. * | |
  246. * +- D -+ P
  247. *
  248. * 0..9 index 0..9
  249. * A..Z index 10..35
  250. * - index 36
  251. * _ index 37
  252. * . index 38
  253. */
  254. #define SYMBOL_DASH (36)
  255. #define SYMBOL_UNDERLINE (37)
  256. #define SYMBOL_DOT (38)
  257. static u8 display_char2seg7_tbl[]=
  258. {
  259. SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
  260. SEG_B | SEG_C, /* 1 */
  261. SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
  262. SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
  263. SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
  264. SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
  265. SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
  266. SEG_A | SEG_B | SEG_C, /* 7 */
  267. SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
  268. SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
  269. SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
  270. SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
  271. SEG_A | SEG_D | SEG_E | SEG_F, /* C */
  272. SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
  273. SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
  274. SEG_A | SEG_E | SEG_F | SEG_G, /* F */
  275. 0, /* g - not displayed */
  276. SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
  277. SEG_B | SEG_C, /* I */
  278. 0, /* J - not displayed */
  279. 0, /* K - not displayed */
  280. SEG_D | SEG_E | SEG_F, /* L */
  281. 0, /* m - not displayed */
  282. 0, /* n - not displayed */
  283. SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
  284. SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
  285. 0, /* q - not displayed */
  286. 0, /* r - not displayed */
  287. SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
  288. SEG_D | SEG_E | SEG_F | SEG_G, /* t */
  289. SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
  290. 0, /* V - not displayed */
  291. 0, /* w - not displayed */
  292. 0, /* X - not displayed */
  293. SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
  294. 0, /* Z - not displayed */
  295. SEG_G, /* - */
  296. SEG_D, /* _ */
  297. SEG_P /* . */
  298. };
  299. /* Convert char to the LED segments representation */
  300. static u8 display_char2seg7(char c)
  301. {
  302. u8 val = 0;
  303. if (c >= '0' && c <= '9')
  304. c -= '0';
  305. else if (c >= 'a' && c <= 'z')
  306. c -= 'a' - 10;
  307. else if (c >= 'A' && c <= 'Z')
  308. c -= 'A' - 10;
  309. else if (c == '-')
  310. c = SYMBOL_DASH;
  311. else if (c == '_')
  312. c = SYMBOL_UNDERLINE;
  313. else if (c == '.')
  314. c = SYMBOL_DOT;
  315. else
  316. c = ' '; /* display unsupported symbols as space */
  317. if (c != ' ')
  318. val = display_char2seg7_tbl[(int)c];
  319. return val;
  320. }
  321. int display_putc(char c)
  322. {
  323. if (display_putc_pos >= DISPLAY_BUF_SIZE)
  324. return -1;
  325. display_buf[display_putc_pos++] = display_char2seg7(c);
  326. /* one-symbol message should be steady */
  327. if (display_putc_pos == 1)
  328. display_buf[display_putc_pos] = display_char2seg7(c);
  329. return c;
  330. }
  331. /*
  332. * Flush current symbol to the LED display hardware
  333. */
  334. static inline void display_flush(void)
  335. {
  336. u32 val = display_buf[display_out_pos];
  337. val |= (val << 8) | (val << 16) | (val << 24);
  338. out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
  339. }
  340. /*
  341. * Output contents of the software display buffer to the LED display every 0.5s
  342. */
  343. void board_show_activity(ulong timestamp)
  344. {
  345. static ulong last;
  346. static u8 once;
  347. if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
  348. display_flush();
  349. display_out_pos ^= 1;
  350. last = timestamp;
  351. once = 1;
  352. }
  353. }
  354. /*
  355. * Empty fake function
  356. */
  357. void show_activity(int arg)
  358. {
  359. }
  360. #endif
  361. #if defined (CONFIG_SHOW_BOOT_PROGRESS)
  362. static int a4m072_status2code(int status, char *buf)
  363. {
  364. char c = 0;
  365. if (((status > 0) && (status <= 8)) ||
  366. ((status >= 100) && (status <= 108)) ||
  367. ((status < 0) && (status >= -9)) ||
  368. (status == -100) || (status == -101) ||
  369. ((status <= -103) && (status >= -113))) {
  370. c = '5';
  371. } else if (((status >= 9) && (status <= 14)) ||
  372. ((status >= 120) && (status <= 123)) ||
  373. ((status >= 125) && (status <= 129)) ||
  374. ((status >= -13) && (status <= -10)) ||
  375. (status == -120) || (status == -122) ||
  376. ((status <= -124) && (status >= -127)) ||
  377. (status == -129)) {
  378. c = '8';
  379. } else if (status == 15) {
  380. c = '9';
  381. } else if ((status <= -30) && (status >= -32)) {
  382. c = 'A';
  383. } else if (((status <= -35) && (status >= -40)) ||
  384. ((status <= -42) && (status >= -51)) ||
  385. ((status <= -53) && (status >= -58)) ||
  386. (status == -64) ||
  387. ((status <= -80) && (status >= -83)) ||
  388. (status == -130) || (status == -140) ||
  389. (status == -150)) {
  390. c = 'B';
  391. }
  392. if (c == 0)
  393. return -EINVAL;
  394. buf[0] = (status < 0) ? '-' : c;
  395. buf[1] = c;
  396. return 0;
  397. }
  398. void show_boot_progress(int status)
  399. {
  400. char buf[2];
  401. if (a4m072_status2code(status, buf) < 0)
  402. return;
  403. display_putc(buf[0]);
  404. display_putc(buf[1]);
  405. display_set(DISPLAY_HOME);
  406. display_out_pos = 0; /* reset output position */
  407. /* we want to flush status 15 now */
  408. if (status == BOOTSTAGE_ID_RUN_OS)
  409. display_flush();
  410. }
  411. #endif