board.c 8.1 KB

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  1. /*
  2. * board.c
  3. *
  4. * Board functions for B&R BRXRE1 Board
  5. *
  6. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  7. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. *
  11. */
  12. #include <common.h>
  13. #include <errno.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/mem.h>
  23. #include <asm/io.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <i2c.h>
  27. #include <power/tps65217.h>
  28. #include "../common/bur_common.h"
  29. #include <lcd.h>
  30. /* -------------------------------------------------------------------------*/
  31. /* -- defines for used GPIO Hardware -- */
  32. #define ESC_KEY (0+19)
  33. #define LCD_PWR (0+5)
  34. #define PUSH_KEY (0+31)
  35. /* -------------------------------------------------------------------------*/
  36. /* -- PSOC Resetcontroller Register defines -- */
  37. /* I2C Address of controller */
  38. #define RSTCTRL_ADDR 0x75
  39. /* Register for CTRL-word */
  40. #define RSTCTRL_CTRLREG 0x01
  41. /* Register for giving some information to VxWorks OS */
  42. #define RSTCTRL_SCRATCHREG 0x04
  43. /* -- defines for RSTCTRL_CTRLREG -- */
  44. #define RSTCTRL_FORCE_PWR_NEN 0x0404
  45. #define RSTCTRL_CAN_STB 0x4040
  46. DECLARE_GLOBAL_DATA_PTR;
  47. #if defined(CONFIG_SPL_BUILD)
  48. /* TODO: check ram-timing ! */
  49. static const struct ddr_data ddr3_data = {
  50. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  51. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  52. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  53. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  54. };
  55. static const struct cmd_control ddr3_cmd_ctrl_data = {
  56. .cmd0csratio = MT41K256M16HA125E_RATIO,
  57. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  58. .cmd1csratio = MT41K256M16HA125E_RATIO,
  59. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  60. .cmd2csratio = MT41K256M16HA125E_RATIO,
  61. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  62. };
  63. static struct emif_regs ddr3_emif_reg_data = {
  64. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  65. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  66. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  67. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  68. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  69. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  70. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  71. };
  72. static const struct ctrl_ioregs ddr3_ioregs = {
  73. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  75. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  76. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  77. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  78. };
  79. #define OSC (V_OSCK/1000000)
  80. const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  81. void am33xx_spl_board_init(void)
  82. {
  83. unsigned int oldspeed;
  84. unsigned short buf;
  85. struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  86. struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  87. /*
  88. * enable additional clocks of modules which are accessed later from
  89. * VxWorks OS
  90. */
  91. u32 *const clk_domains[] = { 0 };
  92. u32 *const clk_modules_xre1specific[] = {
  93. &cmwkup->wkup_adctscctrl,
  94. &cmper->spi1clkctrl,
  95. &cmper->dcan0clkctrl,
  96. &cmper->dcan1clkctrl,
  97. &cmper->epwmss0clkctrl,
  98. &cmper->epwmss1clkctrl,
  99. &cmper->epwmss2clkctrl,
  100. &cmper->lcdclkctrl,
  101. &cmper->lcdcclkstctrl,
  102. 0
  103. };
  104. do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
  105. /* setup LCD-Pixel Clock */
  106. writel(0x2, CM_DPLL + 0x34);
  107. /* power-OFF LCD-Display */
  108. gpio_direction_output(LCD_PWR, 0);
  109. /* setup I2C */
  110. enable_i2c_pin_mux();
  111. i2c_set_bus_num(0);
  112. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  113. /* power-ON 3V3 via Resetcontroller */
  114. oldspeed = i2c_get_bus_speed();
  115. if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
  116. buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
  117. i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
  118. (uint8_t *)&buf, sizeof(buf));
  119. i2c_set_bus_speed(oldspeed);
  120. } else {
  121. puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
  122. }
  123. pmicsetup(0);
  124. }
  125. const struct dpll_params *get_dpll_ddr_params(void)
  126. {
  127. return &dpll_ddr3;
  128. }
  129. void sdram_init(void)
  130. {
  131. config_ddr(400, &ddr3_ioregs,
  132. &ddr3_data,
  133. &ddr3_cmd_ctrl_data,
  134. &ddr3_emif_reg_data, 0);
  135. }
  136. #endif /* CONFIG_SPL_BUILD */
  137. /*
  138. * Basic board specific setup. Pinmux has been handled already.
  139. */
  140. int board_init(void)
  141. {
  142. gpmc_init();
  143. return 0;
  144. }
  145. #ifdef CONFIG_BOARD_LATE_INIT
  146. int board_late_init(void)
  147. {
  148. const unsigned int toff = 1000;
  149. unsigned int cnt = 3;
  150. unsigned short buf = 0xAAAA;
  151. unsigned char scratchreg = 0;
  152. unsigned int oldspeed;
  153. /* try to read out some boot-instruction from resetcontroller */
  154. oldspeed = i2c_get_bus_speed();
  155. if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
  156. i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
  157. &scratchreg, sizeof(scratchreg));
  158. i2c_set_bus_speed(oldspeed);
  159. } else {
  160. puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
  161. }
  162. if (gpio_get_value(ESC_KEY)) {
  163. do {
  164. lcd_position_cursor(1, 8);
  165. switch (cnt) {
  166. case 3:
  167. lcd_puts(
  168. "release ESC-KEY to enter SERVICE-mode.");
  169. break;
  170. case 2:
  171. lcd_puts(
  172. "release ESC-KEY to enter DIAGNOSE-mode.");
  173. break;
  174. case 1:
  175. lcd_puts(
  176. "release ESC-KEY to enter BOOT-mode. ");
  177. break;
  178. }
  179. mdelay(toff);
  180. cnt--;
  181. if (!gpio_get_value(ESC_KEY) &&
  182. gpio_get_value(PUSH_KEY) && 2 == cnt) {
  183. lcd_position_cursor(1, 8);
  184. lcd_puts(
  185. "switching to network-console ... ");
  186. setenv("bootcmd", "run netconsole");
  187. cnt = 4;
  188. break;
  189. } else if (!gpio_get_value(ESC_KEY) &&
  190. gpio_get_value(PUSH_KEY) && 1 == cnt) {
  191. lcd_position_cursor(1, 8);
  192. lcd_puts(
  193. "starting u-boot script from USB ... ");
  194. setenv("bootcmd", "run usbscript");
  195. cnt = 4;
  196. break;
  197. } else if ((!gpio_get_value(ESC_KEY) &&
  198. gpio_get_value(PUSH_KEY) && cnt == 0) ||
  199. (gpio_get_value(ESC_KEY) &&
  200. gpio_get_value(PUSH_KEY) && cnt == 0)) {
  201. lcd_position_cursor(1, 8);
  202. lcd_puts(
  203. "starting script from network ... ");
  204. setenv("bootcmd", "run netscript");
  205. cnt = 4;
  206. break;
  207. } else if (!gpio_get_value(ESC_KEY)) {
  208. break;
  209. }
  210. } while (cnt);
  211. } else if (scratchreg == 0xCC) {
  212. lcd_position_cursor(1, 8);
  213. lcd_puts(
  214. "starting vxworks from network ... ");
  215. setenv("bootcmd", "run netboot");
  216. cnt = 4;
  217. } else if (scratchreg == 0xCD) {
  218. lcd_position_cursor(1, 8);
  219. lcd_puts(
  220. "starting script from network ... ");
  221. setenv("bootcmd", "run netscript");
  222. cnt = 4;
  223. } else if (scratchreg == 0xCE) {
  224. lcd_position_cursor(1, 8);
  225. lcd_puts(
  226. "starting AR from eMMC ... ");
  227. setenv("bootcmd", "run mmcboot");
  228. cnt = 4;
  229. }
  230. lcd_position_cursor(1, 8);
  231. switch (cnt) {
  232. case 0:
  233. lcd_puts("entering BOOT-mode. ");
  234. setenv("bootcmd", "run defaultAR");
  235. buf = 0x0000;
  236. break;
  237. case 1:
  238. lcd_puts("entering DIAGNOSE-mode. ");
  239. buf = 0x0F0F;
  240. break;
  241. case 2:
  242. lcd_puts("entering SERVICE mode. ");
  243. buf = 0xB4B4;
  244. break;
  245. case 3:
  246. lcd_puts("loading OS... ");
  247. buf = 0x0404;
  248. break;
  249. }
  250. /* write bootinfo into scratchregister of resetcontroller */
  251. oldspeed = i2c_get_bus_speed();
  252. if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
  253. i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
  254. (uint8_t *)&buf, sizeof(buf));
  255. i2c_set_bus_speed(oldspeed);
  256. } else {
  257. puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
  258. }
  259. /* setup othbootargs for bootvx-command (vxWorks bootline) */
  260. char othbootargs[128];
  261. snprintf(othbootargs, sizeof(othbootargs),
  262. "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
  263. (unsigned int) gd->fb_base-0x20,
  264. (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
  265. (u32)getenv_ulong("vx_romfsbase", 16, 0),
  266. (u32)getenv_ulong("vx_romfssize", 16, 0));
  267. setenv("othbootargs", othbootargs);
  268. /*
  269. * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
  270. * expect that vectors are there, original u-boot moves them to _start
  271. */
  272. __asm__("ldr r0,=0x20000");
  273. __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
  274. return 0;
  275. }
  276. #endif /* CONFIG_BOARD_LATE_INIT */