pic32mzda.dtsi 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186
  1. /*
  2. * Copyright 2015 Microchip Technology, Inc.
  3. * Purna Chandra Mandal, <purna.mandal@microchip.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/clock/microchip,clock.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include "skeleton.dtsi"
  11. / {
  12. compatible = "microchip,pic32mzda", "microchip,pic32mz";
  13. aliases {
  14. gpio0 = &gpioA;
  15. gpio1 = &gpioB;
  16. gpio2 = &gpioC;
  17. gpio3 = &gpioD;
  18. gpio4 = &gpioE;
  19. gpio5 = &gpioF;
  20. gpio6 = &gpioG;
  21. gpio7 = &gpioH;
  22. gpio8 = &gpioJ;
  23. gpio9 = &gpioK;
  24. };
  25. cpus {
  26. cpu@0 {
  27. compatible = "mips,mips14kc";
  28. };
  29. };
  30. clock: clk@1f801200 {
  31. compatible = "microchip,pic32mzda-clk";
  32. reg = <0x1f801200 0x1000>;
  33. #clock-cells = <1>;
  34. };
  35. uart1: serial@1f822000 {
  36. compatible = "microchip,pic32mzda-uart";
  37. reg = <0x1f822000 0x50>;
  38. interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
  39. status = "disabled";
  40. clocks = <&clock PB2CLK>;
  41. };
  42. uart2: serial@1f822200 {
  43. compatible = "microchip,pic32mzda-uart";
  44. reg = <0x1f822200 0x50>;
  45. interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
  46. clocks = <&clock PB2CLK>;
  47. status = "disabled";
  48. };
  49. uart6: serial@1f822a00 {
  50. compatible = "microchip,pic32mzda-uart";
  51. reg = <0x1f822a00 0x50>;
  52. interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
  53. clocks = <&clock PB2CLK>;
  54. status = "disabled";
  55. };
  56. evic: interrupt-controller@1f810000 {
  57. compatible = "microchip,pic32mzda-evic";
  58. interrupt-controller;
  59. #interrupt-cells = <2>;
  60. reg = <0x1f810000 0x1000>;
  61. };
  62. pinctrl: pinctrl@1f801400 {
  63. compatible = "microchip,pic32mzda-pinctrl";
  64. reg = <0x1f801400 0x100>, /* in */
  65. <0x1f801500 0x200>, /* out */
  66. <0x1f860000 0xa00>; /* port */
  67. reg-names = "ppsin","ppsout","port";
  68. status = "disabled";
  69. ranges = <0 0x1f860000 0xa00>;
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. gpioA: gpio0@0 {
  73. compatible = "microchip,pic32mzda-gpio";
  74. reg = <0x000 0x48>;
  75. gpio-controller;
  76. #gpio-cells = <2>;
  77. };
  78. gpioB: gpio1@100 {
  79. compatible = "microchip,pic32mzda-gpio";
  80. reg = <0x100 0x48>;
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. };
  84. gpioC: gpio2@200 {
  85. compatible = "microchip,pic32mzda-gpio";
  86. reg = <0x200 0x48>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. };
  90. gpioD: gpio3@300 {
  91. compatible = "microchip,pic32mzda-gpio";
  92. reg = <0x300 0x48>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. };
  96. gpioE: gpio4@400 {
  97. compatible = "microchip,pic32mzda-gpio";
  98. reg = <0x400 0x48>;
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. };
  102. gpioF: gpio5@500 {
  103. compatible = "microchip,pic32mzda-gpio";
  104. reg = <0x500 0x48>;
  105. gpio-controller;
  106. #gpio-cells = <2>;
  107. };
  108. gpioG: gpio6@600 {
  109. compatible = "microchip,pic32mzda-gpio";
  110. reg = <0x600 0x48>;
  111. gpio-controller;
  112. #gpio-cells = <2>;
  113. };
  114. gpioH: gpio7@700 {
  115. compatible = "microchip,pic32mzda-gpio";
  116. reg = <0x700 0x48>;
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. };
  120. gpioJ: gpio8@800 {
  121. compatible = "microchip,pic32mzda-gpio";
  122. reg = <0x800 0x48>;
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. };
  126. gpioK: gpio9@900 {
  127. compatible = "microchip,pic32mzda-gpio";
  128. reg = <0x900 0x48>;
  129. gpio-controller;
  130. #gpio-cells = <2>;
  131. };
  132. };
  133. sdhci: sdhci@1f8ec000 {
  134. compatible = "microchip,pic32mzda-sdhci";
  135. reg = <0x1f8ec000 0x100>;
  136. interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
  137. clocks = <&clock REF4CLK>, <&clock PB5CLK>;
  138. clock-names = "base_clk", "sys_clk";
  139. clock-freq-min-max = <25000000>,<25000000>;
  140. bus-width = <4>;
  141. status = "disabled";
  142. };
  143. ethernet: ethernet@1f882000 {
  144. compatible = "microchip,pic32mzda-eth";
  145. reg = <0x1f882000 0x1000>;
  146. interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
  147. clocks = <&clock PB5CLK>;
  148. status = "disabled";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. };
  152. usb: musb@1f8e3000 {
  153. compatible = "microchip,pic32mzda-usb";
  154. reg = <0x1f8e3000 0x1000>,
  155. <0x1f884000 0x1000>;
  156. reg-names = "mc", "control";
  157. interrupts = <132 IRQ_TYPE_EDGE_RISING>,
  158. <133 IRQ_TYPE_LEVEL_HIGH>;
  159. clocks = <&clock PB5CLK>;
  160. clock-names = "usb_clk";
  161. status = "disabled";
  162. };
  163. };