pfc-r8a7794.c 62 KB

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  1. /*
  2. * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
  3. * This file is r8a7794 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. *
  7. * SPDX-License-Identifier: GPL-2.0
  8. */
  9. #include <common.h>
  10. #include <sh_pfc.h>
  11. #include <asm/gpio.h>
  12. #define CPU_32_PORT(fn, pfx, sfx) \
  13. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  14. PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
  15. PORT_1(fn, pfx##31, sfx)
  16. #define CPU_26_PORT(fn, pfx, sfx) \
  17. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  18. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  19. PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
  20. PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
  21. #define CPU_28_PORT(fn, pfx, sfx) \
  22. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  23. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  24. PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
  25. PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
  26. PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
  27. /*
  28. * GP_0_0_DATA -> GP_6_25_DATA
  29. * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
  30. * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
  31. * GP6[29]),GP6[30],GP6[31])
  32. */
  33. #define CPU_ALL_PORT(fn, pfx, sfx) \
  34. CPU_32_PORT(fn, pfx##_0_, sfx), \
  35. CPU_26_PORT(fn, pfx##_1_, sfx), \
  36. CPU_32_PORT(fn, pfx##_2_, sfx), \
  37. CPU_32_PORT(fn, pfx##_3_, sfx), \
  38. CPU_32_PORT(fn, pfx##_4_, sfx), \
  39. CPU_28_PORT(fn, pfx##_5_, sfx), \
  40. CPU_26_PORT(fn, pfx##_6_, sfx)
  41. #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
  42. #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
  43. GP##pfx##_IN, GP##pfx##_OUT)
  44. #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
  45. #define _GP_INDT(pfx, sfx) GP##pfx##_DATA
  46. #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
  47. #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
  48. #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
  49. #define PORT_10_REV(fn, pfx, sfx) \
  50. PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
  51. PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
  52. PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
  53. PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
  54. PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
  55. #define CPU_32_PORT_REV(fn, pfx, sfx) \
  56. PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
  57. PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
  58. PORT_10_REV(fn, pfx, sfx)
  59. #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
  60. #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
  61. #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  62. #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  63. FN_##ipsr, FN_##fn)
  64. enum {
  65. PINMUX_RESERVED = 0,
  66. PINMUX_DATA_BEGIN,
  67. GP_ALL(DATA),
  68. PINMUX_DATA_END,
  69. PINMUX_INPUT_BEGIN,
  70. GP_ALL(IN),
  71. PINMUX_INPUT_END,
  72. PINMUX_OUTPUT_BEGIN,
  73. GP_ALL(OUT),
  74. PINMUX_OUTPUT_END,
  75. PINMUX_FUNCTION_BEGIN,
  76. GP_ALL(FN),
  77. /* GPSR0 */
  78. FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  79. FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  80. FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  81. FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  82. FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  83. FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  84. FN_IP2_17_16,
  85. /* GPSR1 */
  86. FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  87. FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  88. FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  89. FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  90. FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  91. /* GPSR2 */
  92. FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  93. FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  94. FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  95. FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  96. FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  97. FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  98. FN_IP6_5_4, FN_IP6_7_6,
  99. /* GPSR3 */
  100. FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  101. FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  102. FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  103. FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  104. FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  105. FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  106. FN_IP8_22_20,
  107. /* GPSR4 */
  108. FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  109. FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  110. FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  111. FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  112. FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  113. FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  114. FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  115. /* GPSR5 */
  116. FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  117. FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  118. FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  119. FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  120. FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  121. FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  122. /* GPSR6 */
  123. FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  124. FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  125. FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  126. FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  127. FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  128. /* IPSR0 */
  129. FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  130. FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  131. FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  132. FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
  133. FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
  134. FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
  135. FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
  136. FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
  137. /*
  138. * From IPSR1 to IPSR5 have been removed because they does not use.
  139. */
  140. /* IPSR6 */
  141. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
  142. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
  143. FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
  144. FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
  145. FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
  146. FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
  147. FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
  148. FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
  149. FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
  150. FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
  151. FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
  152. FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
  153. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
  154. FN_ADIDATA, FN_AD_DI,
  155. /* IPSR7 */
  156. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
  157. FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
  158. FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
  159. FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
  160. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
  161. FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
  162. FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
  163. FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
  164. FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
  165. FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
  166. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
  167. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
  168. FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
  169. /* IPSR8 */
  170. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
  171. FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
  172. FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
  173. FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
  174. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  175. FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
  176. FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
  177. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  178. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
  179. FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
  180. FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
  181. FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
  182. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
  183. FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
  184. FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
  185. /*
  186. * From IPSR9 to IPSR10 have been removed because they does not use.
  187. */
  188. /* IPSR11 */
  189. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  190. FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
  191. FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
  192. FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
  193. FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
  194. FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  195. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
  196. FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
  197. FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
  198. FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
  199. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  200. FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
  201. FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
  202. FN_ADICLK_B, FN_AD_CLK_B,
  203. /*
  204. * From IPSR12 to IPSR13 have been removed because they does not use.
  205. */
  206. /* MOD_SEL */
  207. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  208. FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
  209. FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
  210. FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
  211. FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
  212. FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
  213. FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
  214. FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
  215. FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
  216. FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
  217. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  218. FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
  219. FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
  220. FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
  221. /* MOD_SEL2 */
  222. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
  223. FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
  224. FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
  225. FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
  226. FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
  227. FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
  228. FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  229. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
  230. FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
  231. FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
  232. FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
  233. FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
  234. FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
  235. FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
  236. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
  237. FN_SEL_RDS_2, FN_SEL_RDS_3,
  238. /* MOD_SEL3 */
  239. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  240. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
  241. FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  242. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  243. FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
  244. FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
  245. FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
  246. FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
  247. FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
  248. FN_SEL_SSI9_1,
  249. PINMUX_FUNCTION_END,
  250. PINMUX_MARK_BEGIN,
  251. A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
  252. USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
  253. SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
  254. SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
  255. SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
  256. SD1_DATA2_MARK, SD1_DATA3_MARK,
  257. /* IPSR0 */
  258. SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
  259. MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
  260. SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
  261. SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
  262. MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
  263. CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
  264. CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
  265. SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
  266. SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
  267. SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
  268. /*
  269. * From IPSR1 to IPSR5 have been removed because they does not use.
  270. */
  271. /* IPSR6 */
  272. DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
  273. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
  274. DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
  275. CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
  276. AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
  277. VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
  278. AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
  279. VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
  280. AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
  281. I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
  282. VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
  283. AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
  284. IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
  285. I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
  286. VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
  287. ADIDATA_MARK, AD_DI_MARK,
  288. /* IPSR7 */
  289. ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
  290. AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
  291. MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
  292. AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
  293. CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
  294. ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
  295. AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
  296. MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
  297. ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
  298. SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
  299. IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
  300. VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
  301. SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
  302. AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
  303. SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
  304. DREQ0_N_MARK, SCIFB1_RXD_MARK,
  305. /* IPSR8 */
  306. ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
  307. AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
  308. I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
  309. HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
  310. AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
  311. SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
  312. HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
  313. AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
  314. HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
  315. I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
  316. AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
  317. SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
  318. CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
  319. DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
  320. I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
  321. TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
  322. I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
  323. FMCLK_C_MARK, RDS_CLK_MARK,
  324. /*
  325. * From IPSR9 to IPSR10 have been removed because they does not use.
  326. */
  327. /* IPSR11 */
  328. SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
  329. CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
  330. DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
  331. SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
  332. SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
  333. DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
  334. SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  335. CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
  336. DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
  337. DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
  338. AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
  339. MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
  340. PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
  341. ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
  342. PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
  343. /*
  344. * From IPSR12 to IPSR13 have been removed because they does not use.
  345. */
  346. PINMUX_MARK_END,
  347. };
  348. static pinmux_enum_t pinmux_data[] = {
  349. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  350. PINMUX_DATA(A2_MARK, FN_A2),
  351. PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
  352. PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
  353. PINMUX_DATA(DACK0_MARK, FN_DACK0),
  354. PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
  355. PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
  356. PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
  357. PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
  358. PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
  359. PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
  360. PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
  361. PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
  362. PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
  363. PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
  364. PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
  365. PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
  366. PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
  367. PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
  368. PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
  369. PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
  370. PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
  371. PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
  372. /* IPSR0 */
  373. PINMUX_IPSR_DATA(IP0_0, SD1_CD),
  374. PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
  375. PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
  376. PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
  377. PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
  378. PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
  379. PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
  380. PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
  381. PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
  382. PINMUX_IPSR_DATA(IP0_12, MMC_D0),
  383. PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
  384. PINMUX_IPSR_DATA(IP0_13, MMC_D1),
  385. PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
  386. PINMUX_IPSR_DATA(IP0_14, MMC_D2),
  387. PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
  388. PINMUX_IPSR_DATA(IP0_15, MMC_D3),
  389. PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
  390. PINMUX_IPSR_DATA(IP0_16, MMC_D4),
  391. PINMUX_IPSR_DATA(IP0_16, SD2_CD),
  392. PINMUX_IPSR_DATA(IP0_17, MMC_D5),
  393. PINMUX_IPSR_DATA(IP0_17, SD2_WP),
  394. PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
  395. PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
  396. PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
  397. PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
  398. PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
  399. PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
  400. PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
  401. PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
  402. PINMUX_IPSR_DATA(IP0_23_22, D0),
  403. PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
  404. PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
  405. PINMUX_IPSR_DATA(IP0_24, D1),
  406. PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
  407. PINMUX_IPSR_DATA(IP0_25, D2),
  408. PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
  409. PINMUX_IPSR_DATA(IP0_27_26, D3),
  410. PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
  411. PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
  412. PINMUX_IPSR_DATA(IP0_29_28, D4),
  413. PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
  414. PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
  415. PINMUX_IPSR_DATA(IP0_31_30, D5),
  416. PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
  417. PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
  418. /*
  419. * From IPSR1 to IPSR5 have been removed because they does not use.
  420. */
  421. /* IPSR6 */
  422. PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
  423. PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
  424. PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
  425. PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
  426. PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
  427. PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
  428. PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
  429. PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
  430. PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
  431. PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
  432. PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
  433. PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
  434. PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
  435. PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
  436. PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
  437. PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
  438. PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
  439. PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
  440. PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
  441. PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
  442. PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
  443. PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
  444. PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
  445. PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
  446. PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
  447. PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
  448. PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
  449. PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
  450. PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
  451. PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
  452. PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
  453. PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
  454. PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
  455. PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
  456. PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
  457. PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
  458. PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
  459. PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
  460. PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
  461. PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
  462. PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
  463. PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
  464. PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
  465. PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
  466. PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
  467. PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
  468. PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
  469. PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
  470. PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
  471. PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
  472. PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
  473. PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
  474. PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
  475. PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
  476. PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
  477. PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
  478. PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
  479. /* IPSR7 */
  480. PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
  481. PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
  482. PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
  483. PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
  484. PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
  485. PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
  486. PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
  487. PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
  488. PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
  489. PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
  490. PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
  491. PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
  492. PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
  493. PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
  494. PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
  495. PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
  496. PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
  497. PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
  498. PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
  499. PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
  500. PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
  501. PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
  502. PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
  503. PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
  504. PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
  505. PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
  506. PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
  507. PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
  508. PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
  509. PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
  510. PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
  511. PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
  512. PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
  513. PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
  514. PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
  515. PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
  516. PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
  517. PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
  518. PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
  519. PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
  520. PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
  521. PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
  522. PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
  523. PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
  524. PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
  525. PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
  526. PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
  527. PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
  528. PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
  529. PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
  530. PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
  531. PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
  532. PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
  533. PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
  534. PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
  535. PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
  536. PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
  537. PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
  538. PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
  539. PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
  540. PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
  541. PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
  542. PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
  543. /* IPSR8 */
  544. PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
  545. PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
  546. PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
  547. PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
  548. PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
  549. PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
  550. PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
  551. PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
  552. PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
  553. PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
  554. PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
  555. PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
  556. PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
  557. PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
  558. PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
  559. PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
  560. PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
  561. PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
  562. PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
  563. PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
  564. PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
  565. PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
  566. PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
  567. PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
  568. PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
  569. PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
  570. PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
  571. PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
  572. PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
  573. PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
  574. PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
  575. PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
  576. PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
  577. PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
  578. PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
  579. PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
  580. PINMUX_IPSR_DATA(IP8_19_17, PWM5),
  581. PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
  582. PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
  583. PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
  584. PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
  585. PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
  586. PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
  587. PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
  588. PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
  589. PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
  590. PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
  591. PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
  592. PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
  593. PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
  594. PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
  595. PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
  596. PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
  597. PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
  598. PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
  599. PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
  600. PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
  601. PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
  602. PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
  603. PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
  604. PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
  605. PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
  606. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
  607. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
  608. PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
  609. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
  610. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
  611. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
  612. PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
  613. /*
  614. * From IPSR9 to IPSR10 have been removed because they does not use.
  615. */
  616. /* IPSR11 */
  617. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
  618. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
  619. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
  620. PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
  621. PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
  622. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
  623. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
  624. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
  625. PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
  626. PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
  627. PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
  628. PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
  629. PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
  630. PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
  631. PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
  632. PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
  633. PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
  634. PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
  635. PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
  636. PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
  637. PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
  638. PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
  639. PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
  640. PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
  641. PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
  642. PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
  643. PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
  644. PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
  645. PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
  646. PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
  647. PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
  648. PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
  649. PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
  650. PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
  651. PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
  652. PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
  653. PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
  654. PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
  655. PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
  656. PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
  657. PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
  658. PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
  659. PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
  660. PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
  661. PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
  662. PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
  663. PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
  664. PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
  665. PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
  666. PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
  667. PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
  668. PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
  669. PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
  670. PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
  671. /*
  672. * From IPSR12 to IPSR13 have been removed because they does not use.
  673. */
  674. };
  675. static struct pinmux_gpio pinmux_gpios[] = {
  676. PINMUX_GPIO_GP_ALL(),
  677. GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
  678. GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
  679. GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
  680. GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
  681. GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
  682. GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
  683. GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
  684. /* IPSR0 */
  685. GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
  686. GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
  687. GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
  688. GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
  689. GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
  690. GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
  691. GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
  692. GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
  693. GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
  694. GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
  695. GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
  696. GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
  697. GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
  698. /*
  699. * From IPSR1 to IPSR5 have been removed because they does not use.
  700. */
  701. /* IPSR6 */
  702. GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
  703. GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
  704. GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
  705. GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
  706. GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
  707. GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
  708. GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
  709. GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
  710. GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
  711. GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
  712. GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
  713. GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
  714. GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
  715. GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
  716. GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
  717. GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
  718. GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
  719. GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
  720. GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
  721. GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
  722. /* IPSR7 */
  723. GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
  724. GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
  725. GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
  726. GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
  727. GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
  728. GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
  729. GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
  730. GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
  731. GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
  732. GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
  733. GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
  734. GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
  735. GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
  736. GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
  737. GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
  738. GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
  739. GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
  740. GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
  741. GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
  742. GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
  743. GPIO_FN(SCIFB1_RXD),
  744. /* IPSR8 */
  745. GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
  746. GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
  747. GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
  748. GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
  749. GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
  750. GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
  751. GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
  752. GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
  753. GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
  754. GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
  755. GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
  756. GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
  757. GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
  758. GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
  759. GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
  760. GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
  761. GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
  762. GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
  763. GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
  764. GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
  765. GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
  766. GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
  767. GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
  768. /*
  769. * From IPSR9 to IPSR10 have been removed because they does not use.
  770. */
  771. /* IPSR11 */
  772. GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
  773. GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
  774. GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
  775. GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
  776. GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
  777. GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
  778. GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
  779. GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
  780. GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
  781. GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
  782. GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
  783. GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
  784. GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
  785. GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
  786. GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
  787. GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
  788. GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
  789. GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
  790. GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
  791. /*
  792. * From IPSR12 to IPSR13 have been removed because they does not use.
  793. */
  794. };
  795. static struct pinmux_cfg_reg pinmux_config_regs[] = {
  796. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
  797. GP_0_31_FN, FN_IP2_17_16,
  798. GP_0_30_FN, FN_IP2_15_14,
  799. GP_0_29_FN, FN_IP2_13_12,
  800. GP_0_28_FN, FN_IP2_11_10,
  801. GP_0_27_FN, FN_IP2_9_8,
  802. GP_0_26_FN, FN_IP2_7_6,
  803. GP_0_25_FN, FN_IP2_5_4,
  804. GP_0_24_FN, FN_IP2_3_2,
  805. GP_0_23_FN, FN_IP2_1_0,
  806. GP_0_22_FN, FN_IP1_31_30,
  807. GP_0_21_FN, FN_IP1_29_28,
  808. GP_0_20_FN, FN_IP1_27,
  809. GP_0_19_FN, FN_IP1_26,
  810. GP_0_18_FN, FN_A2,
  811. GP_0_17_FN, FN_IP1_24,
  812. GP_0_16_FN, FN_IP1_23_22,
  813. GP_0_15_FN, FN_IP1_21_20,
  814. GP_0_14_FN, FN_IP1_19_18,
  815. GP_0_13_FN, FN_IP1_17_15,
  816. GP_0_12_FN, FN_IP1_14_13,
  817. GP_0_11_FN, FN_IP1_12_11,
  818. GP_0_10_FN, FN_IP1_10_8,
  819. GP_0_9_FN, FN_IP1_7_6,
  820. GP_0_8_FN, FN_IP1_5_4,
  821. GP_0_7_FN, FN_IP1_3_2,
  822. GP_0_6_FN, FN_IP1_1_0,
  823. GP_0_5_FN, FN_IP0_31_30,
  824. GP_0_4_FN, FN_IP0_29_28,
  825. GP_0_3_FN, FN_IP0_27_26,
  826. GP_0_2_FN, FN_IP0_25,
  827. GP_0_1_FN, FN_IP0_24,
  828. GP_0_0_FN, FN_IP0_23_22, }
  829. },
  830. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
  831. 0, 0,
  832. 0, 0,
  833. 0, 0,
  834. 0, 0,
  835. 0, 0,
  836. 0, 0,
  837. GP_1_25_FN, FN_DACK0,
  838. GP_1_24_FN, FN_IP7_31,
  839. GP_1_23_FN, FN_IP4_1_0,
  840. GP_1_22_FN, FN_WE1_N,
  841. GP_1_21_FN, FN_WE0_N,
  842. GP_1_20_FN, FN_IP3_31,
  843. GP_1_19_FN, FN_IP3_30,
  844. GP_1_18_FN, FN_IP3_29_27,
  845. GP_1_17_FN, FN_IP3_26_24,
  846. GP_1_16_FN, FN_IP3_23_21,
  847. GP_1_15_FN, FN_IP3_20_18,
  848. GP_1_14_FN, FN_IP3_17_15,
  849. GP_1_13_FN, FN_IP3_14_13,
  850. GP_1_12_FN, FN_IP3_12,
  851. GP_1_11_FN, FN_IP3_11,
  852. GP_1_10_FN, FN_IP3_10,
  853. GP_1_9_FN, FN_IP3_9_8,
  854. GP_1_8_FN, FN_IP3_7_6,
  855. GP_1_7_FN, FN_IP3_5_4,
  856. GP_1_6_FN, FN_IP3_3_2,
  857. GP_1_5_FN, FN_IP3_1_0,
  858. GP_1_4_FN, FN_IP2_31_30,
  859. GP_1_3_FN, FN_IP2_29_27,
  860. GP_1_2_FN, FN_IP2_26_24,
  861. GP_1_1_FN, FN_IP2_23_21,
  862. GP_1_0_FN, FN_IP2_20_18, }
  863. },
  864. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
  865. GP_2_31_FN, FN_IP6_7_6,
  866. GP_2_30_FN, FN_IP6_5_4,
  867. GP_2_29_FN, FN_IP6_3_2,
  868. GP_2_28_FN, FN_IP6_1_0,
  869. GP_2_27_FN, FN_IP5_31_30,
  870. GP_2_26_FN, FN_IP5_29_28,
  871. GP_2_25_FN, FN_IP5_27_26,
  872. GP_2_24_FN, FN_IP5_25_24,
  873. GP_2_23_FN, FN_IP5_23_22,
  874. GP_2_22_FN, FN_IP5_21_20,
  875. GP_2_21_FN, FN_IP5_19_18,
  876. GP_2_20_FN, FN_IP5_17_16,
  877. GP_2_19_FN, FN_IP5_15_14,
  878. GP_2_18_FN, FN_IP5_13_12,
  879. GP_2_17_FN, FN_IP5_11_9,
  880. GP_2_16_FN, FN_IP5_8_6,
  881. GP_2_15_FN, FN_IP5_5_4,
  882. GP_2_14_FN, FN_IP5_3_2,
  883. GP_2_13_FN, FN_IP5_1_0,
  884. GP_2_12_FN, FN_IP4_31_30,
  885. GP_2_11_FN, FN_IP4_29_28,
  886. GP_2_10_FN, FN_IP4_27_26,
  887. GP_2_9_FN, FN_IP4_25_23,
  888. GP_2_8_FN, FN_IP4_22_20,
  889. GP_2_7_FN, FN_IP4_19_18,
  890. GP_2_6_FN, FN_IP4_17_16,
  891. GP_2_5_FN, FN_IP4_15_14,
  892. GP_2_4_FN, FN_IP4_13_12,
  893. GP_2_3_FN, FN_IP4_11_10,
  894. GP_2_2_FN, FN_IP4_9_8,
  895. GP_2_1_FN, FN_IP4_7_5,
  896. GP_2_0_FN, FN_IP4_4_2 }
  897. },
  898. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
  899. GP_3_31_FN, FN_IP8_22_20,
  900. GP_3_30_FN, FN_IP8_19_17,
  901. GP_3_29_FN, FN_IP8_16_15,
  902. GP_3_28_FN, FN_IP8_14_12,
  903. GP_3_27_FN, FN_IP8_11_9,
  904. GP_3_26_FN, FN_IP8_8_6,
  905. GP_3_25_FN, FN_IP8_5_3,
  906. GP_3_24_FN, FN_IP8_2_0,
  907. GP_3_23_FN, FN_IP7_29_27,
  908. GP_3_22_FN, FN_IP7_26_24,
  909. GP_3_21_FN, FN_IP7_23_21,
  910. GP_3_20_FN, FN_IP7_20_18,
  911. GP_3_19_FN, FN_IP7_17_15,
  912. GP_3_18_FN, FN_IP7_14_12,
  913. GP_3_17_FN, FN_IP7_11_9,
  914. GP_3_16_FN, FN_IP7_8_6,
  915. GP_3_15_FN, FN_IP7_5_3,
  916. GP_3_14_FN, FN_IP7_2_0,
  917. GP_3_13_FN, FN_IP6_31_29,
  918. GP_3_12_FN, FN_IP6_28_26,
  919. GP_3_11_FN, FN_IP6_25_23,
  920. GP_3_10_FN, FN_IP6_22_20,
  921. GP_3_9_FN, FN_IP6_19_17,
  922. GP_3_8_FN, FN_IP6_16,
  923. GP_3_7_FN, FN_IP6_15,
  924. GP_3_6_FN, FN_IP6_14,
  925. GP_3_5_FN, FN_IP6_13,
  926. GP_3_4_FN, FN_IP6_12,
  927. GP_3_3_FN, FN_IP6_11,
  928. GP_3_2_FN, FN_IP6_10,
  929. GP_3_1_FN, FN_IP6_9,
  930. GP_3_0_FN, FN_IP6_8 }
  931. },
  932. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
  933. GP_4_31_FN, FN_IP11_17_16,
  934. GP_4_30_FN, FN_IP11_15_14,
  935. GP_4_29_FN, FN_IP11_13_11,
  936. GP_4_28_FN, FN_IP11_10_8,
  937. GP_4_27_FN, FN_IP11_7_6,
  938. GP_4_26_FN, FN_IP11_5_3,
  939. GP_4_25_FN, FN_IP11_2_0,
  940. GP_4_24_FN, FN_IP10_31_30,
  941. GP_4_23_FN, FN_IP10_29_27,
  942. GP_4_22_FN, FN_IP10_26_24,
  943. GP_4_21_FN, FN_IP10_23_21,
  944. GP_4_20_FN, FN_IP10_20_18,
  945. GP_4_19_FN, FN_IP10_17_15,
  946. GP_4_18_FN, FN_IP10_14_12,
  947. GP_4_17_FN, FN_IP10_11_9,
  948. GP_4_16_FN, FN_IP10_8_6,
  949. GP_4_15_FN, FN_IP10_5_3,
  950. GP_4_14_FN, FN_IP10_2_0,
  951. GP_4_13_FN, FN_IP9_30_28,
  952. GP_4_12_FN, FN_IP9_27_25,
  953. GP_4_11_FN, FN_IP9_24_22,
  954. GP_4_10_FN, FN_IP9_21_19,
  955. GP_4_9_FN, FN_IP9_18_17,
  956. GP_4_8_FN, FN_IP9_16_15,
  957. GP_4_7_FN, FN_IP9_14_12,
  958. GP_4_6_FN, FN_IP9_11_9,
  959. GP_4_5_FN, FN_IP9_8_6,
  960. GP_4_4_FN, FN_IP9_5_3,
  961. GP_4_3_FN, FN_IP9_2_0,
  962. GP_4_2_FN, FN_IP8_31_29,
  963. GP_4_1_FN, FN_IP8_28_26,
  964. GP_4_0_FN, FN_IP8_25_23 }
  965. },
  966. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
  967. 0, 0,
  968. 0, 0,
  969. 0, 0,
  970. 0, 0,
  971. GP_5_27_FN, FN_USB1_OVC,
  972. GP_5_26_FN, FN_USB1_PWEN,
  973. GP_5_25_FN, FN_USB0_OVC,
  974. GP_5_24_FN, FN_USB0_PWEN,
  975. GP_5_23_FN, FN_IP13_26_24,
  976. GP_5_22_FN, FN_IP13_23_21,
  977. GP_5_21_FN, FN_IP13_20_18,
  978. GP_5_20_FN, FN_IP13_17_15,
  979. GP_5_19_FN, FN_IP13_14_12,
  980. GP_5_18_FN, FN_IP13_11_9,
  981. GP_5_17_FN, FN_IP13_8_6,
  982. GP_5_16_FN, FN_IP13_5_3,
  983. GP_5_15_FN, FN_IP13_2_0,
  984. GP_5_14_FN, FN_IP12_29_27,
  985. GP_5_13_FN, FN_IP12_26_24,
  986. GP_5_12_FN, FN_IP12_23_21,
  987. GP_5_11_FN, FN_IP12_20_18,
  988. GP_5_10_FN, FN_IP12_17_15,
  989. GP_5_9_FN, FN_IP12_14_13,
  990. GP_5_8_FN, FN_IP12_12_11,
  991. GP_5_7_FN, FN_IP12_10_9,
  992. GP_5_6_FN, FN_IP12_8_6,
  993. GP_5_5_FN, FN_IP12_5_3,
  994. GP_5_4_FN, FN_IP12_2_0,
  995. GP_5_3_FN, FN_IP11_29_27,
  996. GP_5_2_FN, FN_IP11_26_24,
  997. GP_5_1_FN, FN_IP11_23_21,
  998. GP_5_0_FN, FN_IP11_20_18 }
  999. },
  1000. { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
  1001. 0, 0,
  1002. 0, 0,
  1003. 0, 0,
  1004. 0, 0,
  1005. 0, 0,
  1006. 0, 0,
  1007. GP_6_25_FN, FN_IP0_21_20,
  1008. GP_6_24_FN, FN_IP0_19_18,
  1009. GP_6_23_FN, FN_IP0_17,
  1010. GP_6_22_FN, FN_IP0_16,
  1011. GP_6_21_FN, FN_IP0_15,
  1012. GP_6_20_FN, FN_IP0_14,
  1013. GP_6_19_FN, FN_IP0_13,
  1014. GP_6_18_FN, FN_IP0_12,
  1015. GP_6_17_FN, FN_IP0_11,
  1016. GP_6_16_FN, FN_IP0_10,
  1017. GP_6_15_FN, FN_IP0_9_8,
  1018. GP_6_14_FN, FN_IP0_0,
  1019. GP_6_13_FN, FN_SD1_DATA3,
  1020. GP_6_12_FN, FN_SD1_DATA2,
  1021. GP_6_11_FN, FN_SD1_DATA1,
  1022. GP_6_10_FN, FN_SD1_DATA0,
  1023. GP_6_9_FN, FN_SD1_CMD,
  1024. GP_6_8_FN, FN_SD1_CLK,
  1025. GP_6_7_FN, FN_SD0_WP,
  1026. GP_6_6_FN, FN_SD0_CD,
  1027. GP_6_5_FN, FN_SD0_DATA3,
  1028. GP_6_4_FN, FN_SD0_DATA2,
  1029. GP_6_3_FN, FN_SD0_DATA1,
  1030. GP_6_2_FN, FN_SD0_DATA0,
  1031. GP_6_1_FN, FN_SD0_CMD,
  1032. GP_6_0_FN, FN_SD0_CLK }
  1033. },
  1034. { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
  1035. 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
  1036. 2, 1, 1, 1, 1, 1, 1, 1, 1) {
  1037. /* IP0_31_30 [2] */
  1038. FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
  1039. /* IP0_29_28 [2] */
  1040. FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
  1041. /* IP0_27_26 [2] */
  1042. FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
  1043. /* IP0_25 [1] */
  1044. FN_D2, FN_SCIFA3_TXD_B,
  1045. /* IP0_24 [1] */
  1046. FN_D1, FN_SCIFA3_RXD_B,
  1047. /* IP0_23_22 [2] */
  1048. FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
  1049. /* IP0_21_20 [2] */
  1050. FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
  1051. /* IP0_19_18 [2] */
  1052. FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
  1053. /* IP0_17 [1] */
  1054. FN_MMC_D5, FN_SD2_WP,
  1055. /* IP0_16 [1] */
  1056. FN_MMC_D4, FN_SD2_CD,
  1057. /* IP0_15 [1] */
  1058. FN_MMC_D3, FN_SD2_DATA3,
  1059. /* IP0_14 [1] */
  1060. FN_MMC_D2, FN_SD2_DATA2,
  1061. /* IP0_13 [1] */
  1062. FN_MMC_D1, FN_SD2_DATA1,
  1063. /* IP0_12 [1] */
  1064. FN_MMC_D0, FN_SD2_DATA0,
  1065. /* IP0_11 [1] */
  1066. FN_MMC_CMD, FN_SD2_CMD,
  1067. /* IP0_10 [1] */
  1068. FN_MMC_CLK, FN_SD2_CLK,
  1069. /* IP0_9_8 [2] */
  1070. FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
  1071. /* IP0_7 [1] */
  1072. 0, 0,
  1073. /* IP0_6 [1] */
  1074. 0, 0,
  1075. /* IP0_5 [1] */
  1076. 0, 0,
  1077. /* IP0_4 [1] */
  1078. 0, 0,
  1079. /* IP0_3 [1] */
  1080. 0, 0,
  1081. /* IP0_2 [1] */
  1082. 0, 0,
  1083. /* IP0_1 [1] */
  1084. 0, 0,
  1085. /* IP0_0 [1] */
  1086. FN_SD1_CD, FN_CAN0_RX, }
  1087. },
  1088. /*
  1089. * From IPSR1 to IPSR5 have been removed because they does not use.
  1090. */
  1091. { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
  1092. 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
  1093. 2, 2) {
  1094. /* IP6_31_29 [3] */
  1095. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
  1096. FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
  1097. /* IP6_28_26 [3] */
  1098. FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
  1099. FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
  1100. /* IP6_25_23 [3] */
  1101. FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
  1102. FN_AVB_COL, 0, 0, 0,
  1103. /* IP6_22_20 [3] */
  1104. FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
  1105. FN_AVB_RX_ER, 0, 0, 0,
  1106. /* IP6_19_17 [3] */
  1107. FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
  1108. FN_AVB_RXD7, 0, 0, 0,
  1109. /* IP6_16 [1] */
  1110. FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
  1111. /* IP6_15 [1] */
  1112. FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
  1113. /* IP6_14 [1] */
  1114. FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
  1115. /* IP6_13 [1] */
  1116. FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
  1117. /* IP6_12 [1] */
  1118. FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
  1119. /* IP6_11 [1] */
  1120. FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
  1121. /* IP6_10 [1] */
  1122. FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
  1123. /* IP6_9 [1] */
  1124. FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
  1125. /* IP6_8 [1] */
  1126. FN_VI0_CLK, FN_AVB_RX_CLK,
  1127. /* IP6_7_6 [2] */
  1128. FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
  1129. /* IP6_5_4 [2] */
  1130. FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
  1131. /* IP6_3_2 [2] */
  1132. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
  1133. /* IP6_1_0 [2] */
  1134. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
  1135. },
  1136. { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
  1137. 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
  1138. /* IP7_31 [1] */
  1139. FN_DREQ0_N, FN_SCIFB1_RXD,
  1140. /* IP7_30 [1] */
  1141. 0, 0,
  1142. /* IP7_29_27 [3] */
  1143. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
  1144. FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
  1145. /* IP7_26_24 [3] */
  1146. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
  1147. FN_SSI_SCK6_B, 0, 0, 0,
  1148. /* IP7_23_21 [3] */
  1149. FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
  1150. FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
  1151. /* IP7_20_18 [3] */
  1152. FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
  1153. FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
  1154. /* IP7_17_15 [3] */
  1155. FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
  1156. FN_SSI_SCK5_B, 0, 0, 0,
  1157. /* IP7_14_12 [3] */
  1158. FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
  1159. FN_AVB_TXD4, FN_ADICHS2, 0, 0,
  1160. /* IP7_11_9 [3] */
  1161. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
  1162. FN_AVB_TXD3, FN_ADICHS1, 0, 0,
  1163. /* IP7_8_6 [3] */
  1164. FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
  1165. FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
  1166. /* IP7_5_3 [3] */
  1167. FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
  1168. FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
  1169. /* IP7_2_0 [3] */
  1170. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
  1171. FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
  1172. },
  1173. { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
  1174. 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
  1175. /* IP8_31_29 [3] */
  1176. FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
  1177. FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
  1178. /* IP8_28_26 [3] */
  1179. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
  1180. FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
  1181. /* IP8_25_23 [3] */
  1182. FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
  1183. FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
  1184. /* IP8_22_20 [3] */
  1185. FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
  1186. FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
  1187. /* IP8_19_17 [3] */
  1188. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
  1189. FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
  1190. /* IP8_16_15 [2] */
  1191. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  1192. /* IP8_14_12 [3] */
  1193. FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
  1194. FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
  1195. /* IP8_11_9 [3] */
  1196. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  1197. FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
  1198. /* IP8_8_6 [3] */
  1199. FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
  1200. FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
  1201. /* IP8_5_3 [3] */
  1202. FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
  1203. FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
  1204. /* IP8_2_0 [3] */
  1205. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
  1206. FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
  1207. },
  1208. /*
  1209. * From IPSR9 to IPSR10 have been removed because they does not use.
  1210. */
  1211. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
  1212. 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
  1213. /* IP11_31_30 [2] */
  1214. 0, 0, 0, 0,
  1215. /* IP11_29_27 [3] */
  1216. FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
  1217. FN_AD_CLK_B, 0, 0, 0,
  1218. /* IP11_26_24 [3] */
  1219. FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
  1220. FN_AD_DO_B, 0, 0, 0,
  1221. /* IP11_23_21 [3] */
  1222. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  1223. FN_AD_DI_B, FN_PCMWE_N, 0, 0,
  1224. /* IP11_20_18 [3] */
  1225. FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
  1226. FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
  1227. /* IP11_17_16 [2] */
  1228. FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
  1229. /* IP11_15_14 [2] */
  1230. FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
  1231. /* IP11_13_11 [3] */
  1232. FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  1233. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
  1234. /* IP11_10_8 [3] */
  1235. FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
  1236. FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
  1237. /* IP11_7_6 [2] */
  1238. FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
  1239. FN_CAN_DEBUGOUT13,
  1240. /* IP11_5_3 [3] */
  1241. FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
  1242. FN_CAN_DEBUGOUT12, 0, 0, 0,
  1243. /* IP11_2_0 [3] */
  1244. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  1245. FN_CAN_DEBUGOUT11, 0, 0, 0, }
  1246. },
  1247. /*
  1248. * From IPSR12 to IPSR13 have been removed because they does not use.
  1249. */
  1250. { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
  1251. 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
  1252. 2, 1) {
  1253. /* SEL_ADG [2] */
  1254. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  1255. /* SEL_ADI [1] */
  1256. FN_SEL_ADI_0, FN_SEL_ADI_1,
  1257. /* SEL_CAN [2] */
  1258. FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
  1259. /* SEL_DARC [3] */
  1260. FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
  1261. FN_SEL_DARC_4, 0, 0, 0,
  1262. /* SEL_DR0 [1] */
  1263. FN_SEL_DR0_0, FN_SEL_DR0_1,
  1264. /* SEL_DR1 [1] */
  1265. FN_SEL_DR1_0, FN_SEL_DR1_1,
  1266. /* SEL_DR2 [1] */
  1267. FN_SEL_DR2_0, FN_SEL_DR2_1,
  1268. /* SEL_DR3 [1] */
  1269. FN_SEL_DR3_0, FN_SEL_DR3_1,
  1270. /* SEL_ETH [1] */
  1271. FN_SEL_ETH_0, FN_SEL_ETH_1,
  1272. /* SLE_FSN [1] */
  1273. FN_SEL_FSN_0, FN_SEL_FSN_1,
  1274. /* SEL_IC200 [3] */
  1275. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  1276. FN_SEL_I2C00_4, 0, 0, 0,
  1277. /* SEL_I2C01 [3] */
  1278. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  1279. FN_SEL_I2C01_4, 0, 0, 0,
  1280. /* SEL_I2C02 [3] */
  1281. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  1282. FN_SEL_I2C02_4, 0, 0, 0,
  1283. /* SEL_I2C03 [3] */
  1284. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  1285. FN_SEL_I2C03_4, 0, 0, 0,
  1286. /* SEL_I2C04 [3] */
  1287. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  1288. FN_SEL_I2C04_4, 0, 0, 0,
  1289. /* SEL_IIC00 [2] */
  1290. FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
  1291. /* SEL_AVB [1] */
  1292. FN_SEL_AVB_0, FN_SEL_AVB_1, }
  1293. },
  1294. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
  1295. 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
  1296. 2, 2, 2, 1, 1, 2) {
  1297. /* SEL_IEB [2] */
  1298. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
  1299. /* SEL_IIC0 [2] */
  1300. FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
  1301. /* SEL_LBS [1] */
  1302. FN_SEL_LBS_0, FN_SEL_LBS_1,
  1303. /* SEL_MSI1 [1] */
  1304. FN_SEL_MSI1_0, FN_SEL_MSI1_1,
  1305. /* SEL_MSI2 [1] */
  1306. FN_SEL_MSI2_0, FN_SEL_MSI2_1,
  1307. /* SEL_RAD [1] */
  1308. FN_SEL_RAD_0, FN_SEL_RAD_1,
  1309. /* SEL_RCN [1] */
  1310. FN_SEL_RCN_0, FN_SEL_RCN_1,
  1311. /* SEL_RSP [1] */
  1312. FN_SEL_RSP_0, FN_SEL_RSP_1,
  1313. /* SEL_SCIFA0 [2] */
  1314. FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
  1315. FN_SEL_SCIFA0_3,
  1316. /* SEL_SCIFA1 [2] */
  1317. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
  1318. /* SEL_SCIFA2 [1] */
  1319. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  1320. /* SEL_SCIFA3 [1] */
  1321. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
  1322. /* SEL_SCIFA4 [2] */
  1323. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
  1324. FN_SEL_SCIFA4_3,
  1325. /* SEL_SCIFA5 [2] */
  1326. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
  1327. FN_SEL_SCIFA5_3,
  1328. /* SEL_SPDM [1] */
  1329. FN_SEL_SPDM_0, FN_SEL_SPDM_1,
  1330. /* SEL_TMU [1] */
  1331. FN_SEL_TMU_0, FN_SEL_TMU_1,
  1332. /* SEL_TSIF0 [2] */
  1333. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  1334. /* SEL_CAN0 [2] */
  1335. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  1336. /* SEL_CAN1 [2] */
  1337. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  1338. /* SEL_HSCIF0 [1] */
  1339. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
  1340. /* SEL_HSCIF1 [1] */
  1341. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  1342. /* SEL_RDS [2] */
  1343. FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
  1344. },
  1345. { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
  1346. 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
  1347. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
  1348. /* SEL_SCIF0 [2] */
  1349. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  1350. /* SEL_SCIF1 [2] */
  1351. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
  1352. /* SEL_SCIF2 [2] */
  1353. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
  1354. /* SEL_SCIF3 [1] */
  1355. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  1356. /* SEL_SCIF4 [3] */
  1357. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  1358. FN_SEL_SCIF4_4, 0, 0, 0,
  1359. /* SEL_SCIF5 [2] */
  1360. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  1361. /* SEL_SSI1 [1] */
  1362. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  1363. /* SEL_SSI2 [1] */
  1364. FN_SEL_SSI2_0, FN_SEL_SSI2_1,
  1365. /* SEL_SSI4 [1] */
  1366. FN_SEL_SSI4_0, FN_SEL_SSI4_1,
  1367. /* SEL_SSI5 [1] */
  1368. FN_SEL_SSI5_0, FN_SEL_SSI5_1,
  1369. /* SEL_SSI6 [1] */
  1370. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  1371. /* SEL_SSI7 [1] */
  1372. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  1373. /* SEL_SSI8 [1] */
  1374. FN_SEL_SSI8_0, FN_SEL_SSI8_1,
  1375. /* SEL_SSI9 [1] */
  1376. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  1377. /* RESEVED [1] */
  1378. 0, 0,
  1379. /* RESEVED [1] */
  1380. 0, 0,
  1381. /* RESEVED [1] */
  1382. 0, 0,
  1383. /* RESEVED [1] */
  1384. 0, 0,
  1385. /* RESEVED [1] */
  1386. 0, 0,
  1387. /* RESEVED [1] */
  1388. 0, 0,
  1389. /* RESEVED [1] */
  1390. 0, 0,
  1391. /* RESEVED [1] */
  1392. 0, 0,
  1393. /* RESEVED [1] */
  1394. 0, 0,
  1395. /* RESEVED [1] */
  1396. 0, 0,
  1397. /* RESEVED [1] */
  1398. 0, 0,
  1399. /* RESEVED [1] */
  1400. 0, 0, }
  1401. },
  1402. { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
  1403. { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
  1404. 0, 0,
  1405. 0, 0,
  1406. 0, 0,
  1407. 0, 0,
  1408. 0, 0,
  1409. 0, 0,
  1410. GP_1_25_IN, GP_1_25_OUT,
  1411. GP_1_24_IN, GP_1_24_OUT,
  1412. GP_1_23_IN, GP_1_23_OUT,
  1413. GP_1_22_IN, GP_1_22_OUT,
  1414. GP_1_21_IN, GP_1_21_OUT,
  1415. GP_1_20_IN, GP_1_20_OUT,
  1416. GP_1_19_IN, GP_1_19_OUT,
  1417. GP_1_18_IN, GP_1_18_OUT,
  1418. GP_1_17_IN, GP_1_17_OUT,
  1419. GP_1_16_IN, GP_1_16_OUT,
  1420. GP_1_15_IN, GP_1_15_OUT,
  1421. GP_1_14_IN, GP_1_14_OUT,
  1422. GP_1_13_IN, GP_1_13_OUT,
  1423. GP_1_12_IN, GP_1_12_OUT,
  1424. GP_1_11_IN, GP_1_11_OUT,
  1425. GP_1_10_IN, GP_1_10_OUT,
  1426. GP_1_9_IN, GP_1_9_OUT,
  1427. GP_1_8_IN, GP_1_8_OUT,
  1428. GP_1_7_IN, GP_1_7_OUT,
  1429. GP_1_6_IN, GP_1_6_OUT,
  1430. GP_1_5_IN, GP_1_5_OUT,
  1431. GP_1_4_IN, GP_1_4_OUT,
  1432. GP_1_3_IN, GP_1_3_OUT,
  1433. GP_1_2_IN, GP_1_2_OUT,
  1434. GP_1_1_IN, GP_1_1_OUT,
  1435. GP_1_0_IN, GP_1_0_OUT, }
  1436. },
  1437. { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
  1438. { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
  1439. { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
  1440. { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
  1441. 0, 0,
  1442. 0, 0,
  1443. 0, 0,
  1444. 0, 0,
  1445. GP_5_27_IN, GP_5_27_OUT,
  1446. GP_5_26_IN, GP_5_26_OUT,
  1447. GP_5_25_IN, GP_5_25_OUT,
  1448. GP_5_24_IN, GP_5_24_OUT,
  1449. GP_5_23_IN, GP_5_23_OUT,
  1450. GP_5_22_IN, GP_5_22_OUT,
  1451. GP_5_21_IN, GP_5_21_OUT,
  1452. GP_5_20_IN, GP_5_20_OUT,
  1453. GP_5_19_IN, GP_5_19_OUT,
  1454. GP_5_18_IN, GP_5_18_OUT,
  1455. GP_5_17_IN, GP_5_17_OUT,
  1456. GP_5_16_IN, GP_5_16_OUT,
  1457. GP_5_15_IN, GP_5_15_OUT,
  1458. GP_5_14_IN, GP_5_14_OUT,
  1459. GP_5_13_IN, GP_5_13_OUT,
  1460. GP_5_12_IN, GP_5_12_OUT,
  1461. GP_5_11_IN, GP_5_11_OUT,
  1462. GP_5_10_IN, GP_5_10_OUT,
  1463. GP_5_9_IN, GP_5_9_OUT,
  1464. GP_5_8_IN, GP_5_8_OUT,
  1465. GP_5_7_IN, GP_5_7_OUT,
  1466. GP_5_6_IN, GP_5_6_OUT,
  1467. GP_5_5_IN, GP_5_5_OUT,
  1468. GP_5_4_IN, GP_5_4_OUT,
  1469. GP_5_3_IN, GP_5_3_OUT,
  1470. GP_5_2_IN, GP_5_2_OUT,
  1471. GP_5_1_IN, GP_5_1_OUT,
  1472. GP_5_0_IN, GP_5_0_OUT, }
  1473. },
  1474. { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
  1475. 0, 0,
  1476. 0, 0,
  1477. 0, 0,
  1478. 0, 0,
  1479. 0, 0,
  1480. 0, 0,
  1481. GP_6_25_IN, GP_6_25_OUT,
  1482. GP_6_24_IN, GP_6_24_OUT,
  1483. GP_6_23_IN, GP_6_23_OUT,
  1484. GP_6_22_IN, GP_6_22_OUT,
  1485. GP_6_21_IN, GP_6_21_OUT,
  1486. GP_6_20_IN, GP_6_20_OUT,
  1487. GP_6_19_IN, GP_6_19_OUT,
  1488. GP_6_18_IN, GP_6_18_OUT,
  1489. GP_6_17_IN, GP_6_17_OUT,
  1490. GP_6_16_IN, GP_6_16_OUT,
  1491. GP_6_15_IN, GP_6_15_OUT,
  1492. GP_6_14_IN, GP_6_14_OUT,
  1493. GP_6_13_IN, GP_6_13_OUT,
  1494. GP_6_12_IN, GP_6_12_OUT,
  1495. GP_6_11_IN, GP_6_11_OUT,
  1496. GP_6_10_IN, GP_6_10_OUT,
  1497. GP_6_9_IN, GP_6_9_OUT,
  1498. GP_6_8_IN, GP_6_8_OUT,
  1499. GP_6_7_IN, GP_6_7_OUT,
  1500. GP_6_6_IN, GP_6_6_OUT,
  1501. GP_6_5_IN, GP_6_5_OUT,
  1502. GP_6_4_IN, GP_6_4_OUT,
  1503. GP_6_3_IN, GP_6_3_OUT,
  1504. GP_6_2_IN, GP_6_2_OUT,
  1505. GP_6_1_IN, GP_6_1_OUT,
  1506. GP_6_0_IN, GP_6_0_OUT, }
  1507. },
  1508. { },
  1509. };
  1510. static struct pinmux_data_reg pinmux_data_regs[] = {
  1511. { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
  1512. { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
  1513. 0, 0, 0, 0,
  1514. 0, 0, GP_1_25_DATA, GP_1_24_DATA,
  1515. GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
  1516. GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
  1517. GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
  1518. GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
  1519. GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
  1520. GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
  1521. },
  1522. { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
  1523. { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
  1524. { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
  1525. { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
  1526. 0, 0, 0, 0,
  1527. GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
  1528. GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
  1529. GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
  1530. GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
  1531. GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
  1532. GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
  1533. GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
  1534. },
  1535. { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
  1536. 0, 0, 0, 0,
  1537. 0, 0, GP_6_25_DATA, GP_6_24_DATA,
  1538. GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
  1539. GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
  1540. GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
  1541. GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
  1542. GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
  1543. GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
  1544. },
  1545. { },
  1546. };
  1547. static struct pinmux_info r8a7794_pinmux_info = {
  1548. .name = "r8a7794_pfc",
  1549. .unlock_reg = 0xe6060000, /* PMMR */
  1550. .reserved_id = PINMUX_RESERVED,
  1551. .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
  1552. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  1553. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  1554. .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
  1555. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  1556. .first_gpio = GPIO_GP_0_0,
  1557. .last_gpio = GPIO_FN_AD_CLK_B,
  1558. .gpios = pinmux_gpios,
  1559. .cfg_regs = pinmux_config_regs,
  1560. .data_regs = pinmux_data_regs,
  1561. .gpio_data = pinmux_data,
  1562. .gpio_data_size = ARRAY_SIZE(pinmux_data),
  1563. };
  1564. void r8a7794_pinmux_init(void)
  1565. {
  1566. register_pinmux(&r8a7794_pinmux_info);
  1567. }