cpu.c 7.2 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <bootm.h>
  10. #include <common.h>
  11. #include <netdev.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <imx_thermal.h>
  19. #include <ipu_pixfmt.h>
  20. #include <thermal.h>
  21. #include <sata.h>
  22. #ifdef CONFIG_FSL_ESDHC
  23. #include <fsl_esdhc.h>
  24. #endif
  25. #if defined(CONFIG_DISPLAY_CPUINFO)
  26. static u32 reset_cause = -1;
  27. static char *get_reset_cause(void)
  28. {
  29. u32 cause;
  30. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  31. cause = readl(&src_regs->srsr);
  32. writel(cause, &src_regs->srsr);
  33. reset_cause = cause;
  34. switch (cause) {
  35. case 0x00001:
  36. case 0x00011:
  37. return "POR";
  38. case 0x00004:
  39. return "CSU";
  40. case 0x00008:
  41. return "IPP USER";
  42. case 0x00010:
  43. #ifdef CONFIG_MX7
  44. return "WDOG1";
  45. #else
  46. return "WDOG";
  47. #endif
  48. case 0x00020:
  49. return "JTAG HIGH-Z";
  50. case 0x00040:
  51. return "JTAG SW";
  52. case 0x00080:
  53. return "WDOG3";
  54. #ifdef CONFIG_MX7
  55. case 0x00100:
  56. return "WDOG4";
  57. case 0x00200:
  58. return "TEMPSENSE";
  59. #else
  60. case 0x00100:
  61. return "TEMPSENSE";
  62. case 0x10000:
  63. return "WARM BOOT";
  64. #endif
  65. default:
  66. return "unknown reset";
  67. }
  68. }
  69. u32 get_imx_reset_cause(void)
  70. {
  71. return reset_cause;
  72. }
  73. #endif
  74. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  75. #if defined(CONFIG_MX53)
  76. #define MEMCTL_BASE ESDCTL_BASE_ADDR
  77. #else
  78. #define MEMCTL_BASE MMDC_P0_BASE_ADDR
  79. #endif
  80. static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  81. static const unsigned char bank_lookup[] = {3, 2};
  82. /* these MMDC registers are common to the IMX53 and IMX6 */
  83. struct esd_mmdc_regs {
  84. uint32_t ctl;
  85. uint32_t pdc;
  86. uint32_t otc;
  87. uint32_t cfg0;
  88. uint32_t cfg1;
  89. uint32_t cfg2;
  90. uint32_t misc;
  91. };
  92. #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
  93. #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
  94. #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
  95. #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
  96. #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
  97. /*
  98. * imx_ddr_size - return size in bytes of DRAM according MMDC config
  99. * The MMDC MDCTL register holds the number of bits for row, col, and data
  100. * width and the MMDC MDMISC register holds the number of banks. Combine
  101. * all these bits to determine the meme size the MMDC has been configured for
  102. */
  103. unsigned imx_ddr_size(void)
  104. {
  105. struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
  106. unsigned ctl = readl(&mem->ctl);
  107. unsigned misc = readl(&mem->misc);
  108. int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
  109. bits += ESD_MMDC_CTL_GET_ROW(ctl);
  110. bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
  111. bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
  112. bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
  113. bits += ESD_MMDC_CTL_GET_CS1(ctl);
  114. /* The MX6 can do only 3840 MiB of DRAM */
  115. if (bits == 32)
  116. return 0xf0000000;
  117. return 1 << bits;
  118. }
  119. #endif
  120. #if defined(CONFIG_DISPLAY_CPUINFO)
  121. const char *get_imx_type(u32 imxtype)
  122. {
  123. switch (imxtype) {
  124. case MXC_CPU_MX7S:
  125. return "7S"; /* Single-core version of the mx7 */
  126. case MXC_CPU_MX7D:
  127. return "7D"; /* Dual-core version of the mx7 */
  128. case MXC_CPU_MX6QP:
  129. return "6QP"; /* Quad-Plus version of the mx6 */
  130. case MXC_CPU_MX6DP:
  131. return "6DP"; /* Dual-Plus version of the mx6 */
  132. case MXC_CPU_MX6Q:
  133. return "6Q"; /* Quad-core version of the mx6 */
  134. case MXC_CPU_MX6D:
  135. return "6D"; /* Dual-core version of the mx6 */
  136. case MXC_CPU_MX6DL:
  137. return "6DL"; /* Dual Lite version of the mx6 */
  138. case MXC_CPU_MX6SOLO:
  139. return "6SOLO"; /* Solo version of the mx6 */
  140. case MXC_CPU_MX6SL:
  141. return "6SL"; /* Solo-Lite version of the mx6 */
  142. case MXC_CPU_MX6SLL:
  143. return "6SLL"; /* SLL version of the mx6 */
  144. case MXC_CPU_MX6SX:
  145. return "6SX"; /* SoloX version of the mx6 */
  146. case MXC_CPU_MX6UL:
  147. return "6UL"; /* Ultra-Lite version of the mx6 */
  148. case MXC_CPU_MX6ULL:
  149. return "6ULL"; /* ULL version of the mx6 */
  150. case MXC_CPU_MX51:
  151. return "51";
  152. case MXC_CPU_MX53:
  153. return "53";
  154. default:
  155. return "??";
  156. }
  157. }
  158. int print_cpuinfo(void)
  159. {
  160. u32 cpurev;
  161. __maybe_unused u32 max_freq;
  162. cpurev = get_cpu_rev();
  163. #if defined(CONFIG_IMX_THERMAL)
  164. struct udevice *thermal_dev;
  165. int cpu_tmp, minc, maxc, ret;
  166. printf("CPU: Freescale i.MX%s rev%d.%d",
  167. get_imx_type((cpurev & 0xFF000) >> 12),
  168. (cpurev & 0x000F0) >> 4,
  169. (cpurev & 0x0000F) >> 0);
  170. max_freq = get_cpu_speed_grade_hz();
  171. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  172. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  173. } else {
  174. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  175. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  176. }
  177. #else
  178. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  179. get_imx_type((cpurev & 0xFF000) >> 12),
  180. (cpurev & 0x000F0) >> 4,
  181. (cpurev & 0x0000F) >> 0,
  182. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  183. #endif
  184. #if defined(CONFIG_IMX_THERMAL)
  185. puts("CPU: ");
  186. switch (get_cpu_temp_grade(&minc, &maxc)) {
  187. case TEMP_AUTOMOTIVE:
  188. puts("Automotive temperature grade ");
  189. break;
  190. case TEMP_INDUSTRIAL:
  191. puts("Industrial temperature grade ");
  192. break;
  193. case TEMP_EXTCOMMERCIAL:
  194. puts("Extended Commercial temperature grade ");
  195. break;
  196. default:
  197. puts("Commercial temperature grade ");
  198. break;
  199. }
  200. printf("(%dC to %dC)", minc, maxc);
  201. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  202. if (!ret) {
  203. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  204. if (!ret)
  205. printf(" at %dC\n", cpu_tmp);
  206. else
  207. debug(" - invalid sensor data\n");
  208. } else {
  209. debug(" - invalid sensor device\n");
  210. }
  211. #endif
  212. printf("Reset cause: %s\n", get_reset_cause());
  213. return 0;
  214. }
  215. #endif
  216. int cpu_eth_init(bd_t *bis)
  217. {
  218. int rc = -ENODEV;
  219. #if defined(CONFIG_FEC_MXC)
  220. rc = fecmxc_initialize(bis);
  221. #endif
  222. return rc;
  223. }
  224. #ifdef CONFIG_FSL_ESDHC
  225. /*
  226. * Initializes on-chip MMC controllers.
  227. * to override, implement board_mmc_init()
  228. */
  229. int cpu_mmc_init(bd_t *bis)
  230. {
  231. return fsl_esdhc_mmc_init(bis);
  232. }
  233. #endif
  234. #ifndef CONFIG_MX7
  235. u32 get_ahb_clk(void)
  236. {
  237. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  238. u32 reg, ahb_podf;
  239. reg = __raw_readl(&imx_ccm->cbcdr);
  240. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  241. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  242. return get_periph_clk() / (ahb_podf + 1);
  243. }
  244. #endif
  245. void arch_preboot_os(void)
  246. {
  247. #if defined(CONFIG_CMD_SATA)
  248. sata_stop();
  249. #if defined(CONFIG_MX6)
  250. disable_sata_clock();
  251. #endif
  252. #endif
  253. #if defined(CONFIG_VIDEO_IPUV3)
  254. /* disable video before launching O/S */
  255. ipuv3_fb_shutdown();
  256. #endif
  257. #if defined(CONFIG_VIDEO_MXS)
  258. lcdif_power_down();
  259. #endif
  260. }
  261. void set_chipselect_size(int const cs_size)
  262. {
  263. unsigned int reg;
  264. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  265. reg = readl(&iomuxc_regs->gpr[1]);
  266. switch (cs_size) {
  267. case CS0_128:
  268. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  269. reg |= 0x5;
  270. break;
  271. case CS0_64M_CS1_64M:
  272. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  273. reg |= 0x1B;
  274. break;
  275. case CS0_64M_CS1_32M_CS2_32M:
  276. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  277. reg |= 0x4B;
  278. break;
  279. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  280. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  281. reg |= 0x249;
  282. break;
  283. default:
  284. printf("Unknown chip select size: %d\n", cs_size);
  285. break;
  286. }
  287. writel(reg, &iomuxc_regs->gpr[1]);
  288. }