zynq-zybo.dts 1.0 KB

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  1. /*
  2. * Digilent ZYBO board DTS
  3. *
  4. * Copyright (C) 2011 - 2015 Xilinx
  5. * Copyright (C) 2012 National Instruments Corp.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /dts-v1/;
  10. #include "zynq-7000.dtsi"
  11. / {
  12. model = "Zynq ZYBO Development Board";
  13. compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
  14. aliases {
  15. ethernet0 = &gem0;
  16. serial0 = &uart1;
  17. spi0 = &qspi;
  18. mmc0 = &sdhci0;
  19. };
  20. memory@0 {
  21. device_type = "memory";
  22. reg = <0x0 0x20000000>;
  23. };
  24. chosen {
  25. bootargs = "";
  26. stdout-path = "serial0:115200n8";
  27. };
  28. usb_phy0: phy0 {
  29. compatible = "usb-nop-xceiv";
  30. #phy-cells = <0>;
  31. reset-gpios = <&gpio0 46 1>;
  32. };
  33. };
  34. &clkc {
  35. ps-clk-frequency = <50000000>;
  36. };
  37. &gem0 {
  38. status = "okay";
  39. phy-mode = "rgmii-id";
  40. phy-handle = <&ethernet_phy>;
  41. ethernet_phy: ethernet-phy@0 {
  42. reg = <0>;
  43. };
  44. };
  45. &qspi {
  46. u-boot,dm-pre-reloc;
  47. status = "okay";
  48. };
  49. &sdhci0 {
  50. u-boot,dm-pre-reloc;
  51. status = "okay";
  52. };
  53. &uart1 {
  54. u-boot,dm-pre-reloc;
  55. status = "okay";
  56. };
  57. &usb0 {
  58. status = "okay";
  59. dr_mode = "host";
  60. usb-phy = <&usb_phy0>;
  61. };