zynq-zed.dts 1007 B

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  1. /*
  2. * Xilinx ZED board DTS
  3. *
  4. * Copyright (C) 2011 - 2015 Xilinx
  5. * Copyright (C) 2012 National Instruments Corp.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /dts-v1/;
  10. #include "zynq-7000.dtsi"
  11. / {
  12. model = "Zynq Zed Development Board";
  13. compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
  14. aliases {
  15. ethernet0 = &gem0;
  16. serial0 = &uart1;
  17. spi0 = &qspi;
  18. mmc0 = &sdhci0;
  19. };
  20. memory@0 {
  21. device_type = "memory";
  22. reg = <0x0 0x20000000>;
  23. };
  24. chosen {
  25. bootargs = "";
  26. stdout-path = "serial0:115200n8";
  27. };
  28. usb_phy0: phy0 {
  29. compatible = "usb-nop-xceiv";
  30. #phy-cells = <0>;
  31. };
  32. };
  33. &clkc {
  34. ps-clk-frequency = <33333333>;
  35. };
  36. &gem0 {
  37. status = "okay";
  38. phy-mode = "rgmii-id";
  39. phy-handle = <&ethernet_phy>;
  40. ethernet_phy: ethernet-phy@0 {
  41. reg = <0>;
  42. };
  43. };
  44. &qspi {
  45. u-boot,dm-pre-reloc;
  46. status = "okay";
  47. };
  48. &sdhci0 {
  49. u-boot,dm-pre-reloc;
  50. status = "okay";
  51. };
  52. &uart1 {
  53. u-boot,dm-pre-reloc;
  54. status = "okay";
  55. };
  56. &usb0 {
  57. status = "okay";
  58. dr_mode = "host";
  59. usb-phy = <&usb_phy0>;
  60. };