zynq-zc702.dts 6.6 KB

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  1. /*
  2. * Xilinx ZC702 board DTS
  3. *
  4. * Copyright (C) 2011 - 2015 Xilinx
  5. * Copyright (C) 2012 National Instruments Corp.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /dts-v1/;
  10. #include "zynq-7000.dtsi"
  11. / {
  12. model = "Zynq ZC702 Development Board";
  13. compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  14. aliases {
  15. ethernet0 = &gem0;
  16. i2c0 = &i2c0;
  17. serial0 = &uart1;
  18. spi0 = &qspi;
  19. mmc0 = &sdhci0;
  20. };
  21. memory@0 {
  22. device_type = "memory";
  23. reg = <0x0 0x40000000>;
  24. };
  25. chosen {
  26. bootargs = "";
  27. stdout-path = "serial0:115200n8";
  28. };
  29. gpio-keys {
  30. compatible = "gpio-keys";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. autorepeat;
  34. sw14 {
  35. label = "sw14";
  36. gpios = <&gpio0 12 0>;
  37. linux,code = <108>; /* down */
  38. gpio-key,wakeup;
  39. autorepeat;
  40. };
  41. sw13 {
  42. label = "sw13";
  43. gpios = <&gpio0 14 0>;
  44. linux,code = <103>; /* up */
  45. gpio-key,wakeup;
  46. autorepeat;
  47. };
  48. };
  49. leds {
  50. compatible = "gpio-leds";
  51. ds23 {
  52. label = "ds23";
  53. gpios = <&gpio0 10 0>;
  54. linux,default-trigger = "heartbeat";
  55. };
  56. };
  57. usb_phy0: phy0 {
  58. compatible = "usb-nop-xceiv";
  59. #phy-cells = <0>;
  60. };
  61. };
  62. &amba {
  63. ocm: sram@fffc0000 {
  64. compatible = "mmio-sram";
  65. reg = <0xfffc0000 0x10000>;
  66. };
  67. };
  68. &can0 {
  69. status = "okay";
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pinctrl_can0_default>;
  72. };
  73. &clkc {
  74. ps-clk-frequency = <33333333>;
  75. };
  76. &gem0 {
  77. status = "okay";
  78. phy-mode = "rgmii-id";
  79. phy-handle = <&ethernet_phy>;
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_gem0_default>;
  82. phy-reset-gpio = <&gpio0 11 0>;
  83. phy-reset-active-low;
  84. ethernet_phy: ethernet-phy@7 {
  85. reg = <7>;
  86. };
  87. };
  88. &gpio0 {
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_gpio0_default>;
  91. };
  92. &i2c0 {
  93. status = "okay";
  94. clock-frequency = <400000>;
  95. pinctrl-names = "default";
  96. pinctrl-0 = <&pinctrl_i2c0_default>;
  97. i2cswitch@74 {
  98. compatible = "nxp,pca9548";
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. reg = <0x74>;
  102. i2c@0 {
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. reg = <0>;
  106. si570: clock-generator@5d {
  107. #clock-cells = <0>;
  108. compatible = "silabs,si570";
  109. temperature-stability = <50>;
  110. reg = <0x5d>;
  111. factory-fout = <156250000>;
  112. clock-frequency = <148500000>;
  113. };
  114. };
  115. i2c@1 {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. reg = <1>;
  119. adv7511: hdmi-tx@39 {
  120. compatible = "adi,adv7511";
  121. reg = <0x39>;
  122. adi,input-depth = <8>;
  123. adi,input-colorspace = "yuv422";
  124. adi,input-clock = "1x";
  125. adi,input-style = <3>;
  126. adi,input-justification = "right";
  127. };
  128. };
  129. i2c@2 {
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. reg = <2>;
  133. eeprom@54 {
  134. compatible = "at,24c08";
  135. reg = <0x54>;
  136. };
  137. };
  138. i2c@3 {
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. reg = <3>;
  142. gpio@21 {
  143. compatible = "ti,tca6416";
  144. reg = <0x21>;
  145. gpio-controller;
  146. #gpio-cells = <2>;
  147. };
  148. };
  149. i2c@4 {
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. reg = <4>;
  153. rtc@51 {
  154. compatible = "nxp,pcf8563";
  155. reg = <0x51>;
  156. };
  157. };
  158. i2c@7 {
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. reg = <7>;
  162. hwmon@52 {
  163. compatible = "ti,ucd9248";
  164. reg = <52>;
  165. };
  166. hwmon@53 {
  167. compatible = "ti,ucd9248";
  168. reg = <53>;
  169. };
  170. hwmon@54 {
  171. compatible = "ti,ucd9248";
  172. reg = <54>;
  173. };
  174. };
  175. };
  176. };
  177. &pinctrl0 {
  178. pinctrl_can0_default: can0-default {
  179. mux {
  180. function = "can0";
  181. groups = "can0_9_grp";
  182. };
  183. conf {
  184. groups = "can0_9_grp";
  185. slew-rate = <0>;
  186. io-standard = <1>;
  187. };
  188. conf-rx {
  189. pins = "MIO46";
  190. bias-high-impedance;
  191. };
  192. conf-tx {
  193. pins = "MIO47";
  194. bias-disable;
  195. };
  196. };
  197. pinctrl_gem0_default: gem0-default {
  198. mux {
  199. function = "ethernet0";
  200. groups = "ethernet0_0_grp";
  201. };
  202. conf {
  203. groups = "ethernet0_0_grp";
  204. slew-rate = <0>;
  205. io-standard = <4>;
  206. };
  207. conf-rx {
  208. pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  209. bias-high-impedance;
  210. low-power-disable;
  211. };
  212. conf-tx {
  213. pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  214. bias-disable;
  215. low-power-enable;
  216. };
  217. mux-mdio {
  218. function = "mdio0";
  219. groups = "mdio0_0_grp";
  220. };
  221. conf-mdio {
  222. groups = "mdio0_0_grp";
  223. slew-rate = <0>;
  224. io-standard = <1>;
  225. bias-disable;
  226. };
  227. };
  228. pinctrl_gpio0_default: gpio0-default {
  229. mux {
  230. function = "gpio0";
  231. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  232. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  233. "gpio0_13_grp", "gpio0_14_grp";
  234. };
  235. conf {
  236. groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  237. "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  238. "gpio0_13_grp", "gpio0_14_grp";
  239. slew-rate = <0>;
  240. io-standard = <1>;
  241. };
  242. conf-pull-up {
  243. pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
  244. bias-pull-up;
  245. };
  246. conf-pull-none {
  247. pins = "MIO7", "MIO8";
  248. bias-disable;
  249. };
  250. };
  251. pinctrl_i2c0_default: i2c0-default {
  252. mux {
  253. groups = "i2c0_10_grp";
  254. function = "i2c0";
  255. };
  256. conf {
  257. groups = "i2c0_10_grp";
  258. bias-pull-up;
  259. slew-rate = <0>;
  260. io-standard = <1>;
  261. };
  262. };
  263. pinctrl_sdhci0_default: sdhci0-default {
  264. mux {
  265. groups = "sdio0_2_grp";
  266. function = "sdio0";
  267. };
  268. conf {
  269. groups = "sdio0_2_grp";
  270. slew-rate = <0>;
  271. io-standard = <1>;
  272. bias-disable;
  273. };
  274. mux-cd {
  275. groups = "gpio0_0_grp";
  276. function = "sdio0_cd";
  277. };
  278. conf-cd {
  279. groups = "gpio0_0_grp";
  280. bias-high-impedance;
  281. bias-pull-up;
  282. slew-rate = <0>;
  283. io-standard = <1>;
  284. };
  285. mux-wp {
  286. groups = "gpio0_15_grp";
  287. function = "sdio0_wp";
  288. };
  289. conf-wp {
  290. groups = "gpio0_15_grp";
  291. bias-high-impedance;
  292. bias-pull-up;
  293. slew-rate = <0>;
  294. io-standard = <1>;
  295. };
  296. };
  297. pinctrl_uart1_default: uart1-default {
  298. mux {
  299. groups = "uart1_10_grp";
  300. function = "uart1";
  301. };
  302. conf {
  303. groups = "uart1_10_grp";
  304. slew-rate = <0>;
  305. io-standard = <1>;
  306. };
  307. conf-rx {
  308. pins = "MIO49";
  309. bias-high-impedance;
  310. };
  311. conf-tx {
  312. pins = "MIO48";
  313. bias-disable;
  314. };
  315. };
  316. pinctrl_usb0_default: usb0-default {
  317. mux {
  318. groups = "usb0_0_grp";
  319. function = "usb0";
  320. };
  321. conf {
  322. groups = "usb0_0_grp";
  323. slew-rate = <0>;
  324. io-standard = <1>;
  325. };
  326. conf-rx {
  327. pins = "MIO29", "MIO31", "MIO36";
  328. bias-high-impedance;
  329. };
  330. conf-tx {
  331. pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
  332. "MIO35", "MIO37", "MIO38", "MIO39";
  333. bias-disable;
  334. };
  335. };
  336. };
  337. &qspi {
  338. u-boot,dm-pre-reloc;
  339. status = "okay";
  340. };
  341. &sdhci0 {
  342. u-boot,dm-pre-reloc;
  343. status = "okay";
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_sdhci0_default>;
  346. };
  347. &uart1 {
  348. u-boot,dm-pre-reloc;
  349. status = "okay";
  350. pinctrl-names = "default";
  351. pinctrl-0 = <&pinctrl_uart1_default>;
  352. };
  353. &usb0 {
  354. status = "okay";
  355. dr_mode = "host";
  356. usb-phy = <&usb_phy0>;
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&pinctrl_usb0_default>;
  359. };