vf.dtsi 3.1 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+ or X11
  5. */
  6. /include/ "skeleton.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. / {
  9. aliases {
  10. gpio0 = &gpio0;
  11. gpio1 = &gpio1;
  12. gpio2 = &gpio2;
  13. gpio3 = &gpio3;
  14. gpio4 = &gpio4;
  15. serial0 = &uart0;
  16. serial1 = &uart1;
  17. serial2 = &uart2;
  18. serial3 = &uart3;
  19. serial4 = &uart4;
  20. serial5 = &uart5;
  21. spi0 = &dspi0;
  22. spi1 = &dspi1;
  23. ehci0 = &ehci0;
  24. ehci1 = &ehci1;
  25. };
  26. soc {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. compatible = "simple-bus";
  30. ranges;
  31. aips0: aips-bus@40000000 {
  32. compatible = "fsl,aips-bus", "simple-bus";
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. reg = <0x40000000 0x00070000>;
  36. ranges;
  37. uart0: serial@40027000 {
  38. compatible = "fsl,vf610-lpuart";
  39. reg = <0x40027000 0x1000>;
  40. status = "disabled";
  41. };
  42. uart1: serial@40028000 {
  43. compatible = "fsl,vf610-lpuart";
  44. reg = <0x40028000 0x1000>;
  45. status = "disabled";
  46. };
  47. uart2: serial@40029000 {
  48. compatible = "fsl,vf610-lpuart";
  49. reg = <0x40029000 0x1000>;
  50. status = "disabled";
  51. };
  52. uart3: serial@4002a000 {
  53. compatible = "fsl,vf610-lpuart";
  54. reg = <0x4002a000 0x1000>;
  55. status = "disabled";
  56. };
  57. dspi0: dspi0@4002c000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. compatible = "fsl,vf610-dspi";
  61. reg = <0x4002c000 0x1000>;
  62. num-cs = <5>;
  63. status = "disabled";
  64. };
  65. dspi1: dspi1@4002d000 {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. compatible = "fsl,vf610-dspi";
  69. reg = <0x4002d000 0x1000>;
  70. num-cs = <5>;
  71. status = "disabled";
  72. };
  73. qspi0: quadspi@40044000 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. compatible = "fsl,vf610-qspi";
  77. reg = <0x40044000 0x1000>,
  78. <0x20000000 0x10000000>;
  79. reg-names = "QuadSPI", "QuadSPI-memory";
  80. status = "disabled";
  81. };
  82. gpio0: gpio@40049000 {
  83. compatible = "fsl,vf610-gpio";
  84. reg = <0x400ff000 0x40>;
  85. #gpio-cells = <2>;
  86. };
  87. gpio1: gpio@4004a000 {
  88. compatible = "fsl,vf610-gpio";
  89. reg = <0x400ff040 0x40>;
  90. #gpio-cells = <2>;
  91. };
  92. gpio2: gpio@4004b000 {
  93. compatible = "fsl,vf610-gpio";
  94. reg = <0x400ff080 0x40>;
  95. #gpio-cells = <2>;
  96. };
  97. gpio3: gpio@4004c000 {
  98. compatible = "fsl,vf610-gpio";
  99. reg = <0x400ff0c0 0x40>;
  100. #gpio-cells = <2>;
  101. };
  102. gpio4: gpio@4004d000 {
  103. compatible = "fsl,vf610-gpio";
  104. reg = <0x400ff100 0x40>;
  105. #gpio-cells = <2>;
  106. };
  107. ehci0: ehci@40034000 {
  108. compatible = "fsl,vf610-usb";
  109. reg = <0x40034000 0x800>;
  110. status = "disabled";
  111. };
  112. };
  113. aips1: aips-bus@40080000 {
  114. compatible = "fsl,aips-bus", "simple-bus";
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. reg = <0x40080000 0x0007f000>;
  118. ranges;
  119. uart4: serial@400a9000 {
  120. compatible = "fsl,vf610-lpuart";
  121. reg = <0x400a9000 0x1000>;
  122. status = "disabled";
  123. };
  124. uart5: serial@400aa000 {
  125. compatible = "fsl,vf610-lpuart";
  126. reg = <0x400aa000 0x1000>;
  127. status = "disabled";
  128. };
  129. ehci1: ehci@400b4000 {
  130. compatible = "fsl,vf610-usb";
  131. reg = <0x400b4000 0x800>;
  132. status = "disabled";
  133. };
  134. };
  135. };
  136. };