thunderx-88xx.dtsi 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363
  1. /*
  2. * Cavium Thunder DTS file - Thunder SoC description
  3. *
  4. * Copyright (C) 2014, Cavium Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+ or X11
  7. *
  8. */
  9. / {
  10. compatible = "cavium,thunder-88xx";
  11. interrupt-parent = <&gic0>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. psci {
  15. compatible = "arm,psci-0.2";
  16. method = "smc";
  17. };
  18. cpus {
  19. #address-cells = <2>;
  20. #size-cells = <0>;
  21. cpu@000 {
  22. device_type = "cpu";
  23. compatible = "cavium,thunder", "arm,armv8";
  24. reg = <0x0 0x000>;
  25. enable-method = "psci";
  26. };
  27. cpu@001 {
  28. device_type = "cpu";
  29. compatible = "cavium,thunder", "arm,armv8";
  30. reg = <0x0 0x001>;
  31. enable-method = "psci";
  32. };
  33. cpu@002 {
  34. device_type = "cpu";
  35. compatible = "cavium,thunder", "arm,armv8";
  36. reg = <0x0 0x002>;
  37. enable-method = "psci";
  38. };
  39. cpu@003 {
  40. device_type = "cpu";
  41. compatible = "cavium,thunder", "arm,armv8";
  42. reg = <0x0 0x003>;
  43. enable-method = "psci";
  44. };
  45. cpu@004 {
  46. device_type = "cpu";
  47. compatible = "cavium,thunder", "arm,armv8";
  48. reg = <0x0 0x004>;
  49. enable-method = "psci";
  50. };
  51. cpu@005 {
  52. device_type = "cpu";
  53. compatible = "cavium,thunder", "arm,armv8";
  54. reg = <0x0 0x005>;
  55. enable-method = "psci";
  56. };
  57. cpu@006 {
  58. device_type = "cpu";
  59. compatible = "cavium,thunder", "arm,armv8";
  60. reg = <0x0 0x006>;
  61. enable-method = "psci";
  62. };
  63. cpu@007 {
  64. device_type = "cpu";
  65. compatible = "cavium,thunder", "arm,armv8";
  66. reg = <0x0 0x007>;
  67. enable-method = "psci";
  68. };
  69. cpu@008 {
  70. device_type = "cpu";
  71. compatible = "cavium,thunder", "arm,armv8";
  72. reg = <0x0 0x008>;
  73. enable-method = "psci";
  74. };
  75. cpu@009 {
  76. device_type = "cpu";
  77. compatible = "cavium,thunder", "arm,armv8";
  78. reg = <0x0 0x009>;
  79. enable-method = "psci";
  80. };
  81. cpu@00a {
  82. device_type = "cpu";
  83. compatible = "cavium,thunder", "arm,armv8";
  84. reg = <0x0 0x00a>;
  85. enable-method = "psci";
  86. };
  87. cpu@00b {
  88. device_type = "cpu";
  89. compatible = "cavium,thunder", "arm,armv8";
  90. reg = <0x0 0x00b>;
  91. enable-method = "psci";
  92. };
  93. cpu@00c {
  94. device_type = "cpu";
  95. compatible = "cavium,thunder", "arm,armv8";
  96. reg = <0x0 0x00c>;
  97. enable-method = "psci";
  98. };
  99. cpu@00d {
  100. device_type = "cpu";
  101. compatible = "cavium,thunder", "arm,armv8";
  102. reg = <0x0 0x00d>;
  103. enable-method = "psci";
  104. };
  105. cpu@00e {
  106. device_type = "cpu";
  107. compatible = "cavium,thunder", "arm,armv8";
  108. reg = <0x0 0x00e>;
  109. enable-method = "psci";
  110. };
  111. cpu@00f {
  112. device_type = "cpu";
  113. compatible = "cavium,thunder", "arm,armv8";
  114. reg = <0x0 0x00f>;
  115. enable-method = "psci";
  116. };
  117. cpu@100 {
  118. device_type = "cpu";
  119. compatible = "cavium,thunder", "arm,armv8";
  120. reg = <0x0 0x100>;
  121. enable-method = "psci";
  122. };
  123. cpu@101 {
  124. device_type = "cpu";
  125. compatible = "cavium,thunder", "arm,armv8";
  126. reg = <0x0 0x101>;
  127. enable-method = "psci";
  128. };
  129. cpu@102 {
  130. device_type = "cpu";
  131. compatible = "cavium,thunder", "arm,armv8";
  132. reg = <0x0 0x102>;
  133. enable-method = "psci";
  134. };
  135. cpu@103 {
  136. device_type = "cpu";
  137. compatible = "cavium,thunder", "arm,armv8";
  138. reg = <0x0 0x103>;
  139. enable-method = "psci";
  140. };
  141. cpu@104 {
  142. device_type = "cpu";
  143. compatible = "cavium,thunder", "arm,armv8";
  144. reg = <0x0 0x104>;
  145. enable-method = "psci";
  146. };
  147. cpu@105 {
  148. device_type = "cpu";
  149. compatible = "cavium,thunder", "arm,armv8";
  150. reg = <0x0 0x105>;
  151. enable-method = "psci";
  152. };
  153. cpu@106 {
  154. device_type = "cpu";
  155. compatible = "cavium,thunder", "arm,armv8";
  156. reg = <0x0 0x106>;
  157. enable-method = "psci";
  158. };
  159. cpu@107 {
  160. device_type = "cpu";
  161. compatible = "cavium,thunder", "arm,armv8";
  162. reg = <0x0 0x107>;
  163. enable-method = "psci";
  164. };
  165. cpu@108 {
  166. device_type = "cpu";
  167. compatible = "cavium,thunder", "arm,armv8";
  168. reg = <0x0 0x108>;
  169. enable-method = "psci";
  170. };
  171. cpu@109 {
  172. device_type = "cpu";
  173. compatible = "cavium,thunder", "arm,armv8";
  174. reg = <0x0 0x109>;
  175. enable-method = "psci";
  176. };
  177. cpu@10a {
  178. device_type = "cpu";
  179. compatible = "cavium,thunder", "arm,armv8";
  180. reg = <0x0 0x10a>;
  181. enable-method = "psci";
  182. };
  183. cpu@10b {
  184. device_type = "cpu";
  185. compatible = "cavium,thunder", "arm,armv8";
  186. reg = <0x0 0x10b>;
  187. enable-method = "psci";
  188. };
  189. cpu@10c {
  190. device_type = "cpu";
  191. compatible = "cavium,thunder", "arm,armv8";
  192. reg = <0x0 0x10c>;
  193. enable-method = "psci";
  194. };
  195. cpu@10d {
  196. device_type = "cpu";
  197. compatible = "cavium,thunder", "arm,armv8";
  198. reg = <0x0 0x10d>;
  199. enable-method = "psci";
  200. };
  201. cpu@10e {
  202. device_type = "cpu";
  203. compatible = "cavium,thunder", "arm,armv8";
  204. reg = <0x0 0x10e>;
  205. enable-method = "psci";
  206. };
  207. cpu@10f {
  208. device_type = "cpu";
  209. compatible = "cavium,thunder", "arm,armv8";
  210. reg = <0x0 0x10f>;
  211. enable-method = "psci";
  212. };
  213. cpu@200 {
  214. device_type = "cpu";
  215. compatible = "cavium,thunder", "arm,armv8";
  216. reg = <0x0 0x200>;
  217. enable-method = "psci";
  218. };
  219. cpu@201 {
  220. device_type = "cpu";
  221. compatible = "cavium,thunder", "arm,armv8";
  222. reg = <0x0 0x201>;
  223. enable-method = "psci";
  224. };
  225. cpu@202 {
  226. device_type = "cpu";
  227. compatible = "cavium,thunder", "arm,armv8";
  228. reg = <0x0 0x202>;
  229. enable-method = "psci";
  230. };
  231. cpu@203 {
  232. device_type = "cpu";
  233. compatible = "cavium,thunder", "arm,armv8";
  234. reg = <0x0 0x203>;
  235. enable-method = "psci";
  236. };
  237. cpu@204 {
  238. device_type = "cpu";
  239. compatible = "cavium,thunder", "arm,armv8";
  240. reg = <0x0 0x204>;
  241. enable-method = "psci";
  242. };
  243. cpu@205 {
  244. device_type = "cpu";
  245. compatible = "cavium,thunder", "arm,armv8";
  246. reg = <0x0 0x205>;
  247. enable-method = "psci";
  248. };
  249. cpu@206 {
  250. device_type = "cpu";
  251. compatible = "cavium,thunder", "arm,armv8";
  252. reg = <0x0 0x206>;
  253. enable-method = "psci";
  254. };
  255. cpu@207 {
  256. device_type = "cpu";
  257. compatible = "cavium,thunder", "arm,armv8";
  258. reg = <0x0 0x207>;
  259. enable-method = "psci";
  260. };
  261. cpu@208 {
  262. device_type = "cpu";
  263. compatible = "cavium,thunder", "arm,armv8";
  264. reg = <0x0 0x208>;
  265. enable-method = "psci";
  266. };
  267. cpu@209 {
  268. device_type = "cpu";
  269. compatible = "cavium,thunder", "arm,armv8";
  270. reg = <0x0 0x209>;
  271. enable-method = "psci";
  272. };
  273. cpu@20a {
  274. device_type = "cpu";
  275. compatible = "cavium,thunder", "arm,armv8";
  276. reg = <0x0 0x20a>;
  277. enable-method = "psci";
  278. };
  279. cpu@20b {
  280. device_type = "cpu";
  281. compatible = "cavium,thunder", "arm,armv8";
  282. reg = <0x0 0x20b>;
  283. enable-method = "psci";
  284. };
  285. cpu@20c {
  286. device_type = "cpu";
  287. compatible = "cavium,thunder", "arm,armv8";
  288. reg = <0x0 0x20c>;
  289. enable-method = "psci";
  290. };
  291. cpu@20d {
  292. device_type = "cpu";
  293. compatible = "cavium,thunder", "arm,armv8";
  294. reg = <0x0 0x20d>;
  295. enable-method = "psci";
  296. };
  297. cpu@20e {
  298. device_type = "cpu";
  299. compatible = "cavium,thunder", "arm,armv8";
  300. reg = <0x0 0x20e>;
  301. enable-method = "psci";
  302. };
  303. cpu@20f {
  304. device_type = "cpu";
  305. compatible = "cavium,thunder", "arm,armv8";
  306. reg = <0x0 0x20f>;
  307. enable-method = "psci";
  308. };
  309. };
  310. timer {
  311. compatible = "arm,armv8-timer";
  312. interrupts = <1 13 0xff01>,
  313. <1 14 0xff01>,
  314. <1 11 0xff01>,
  315. <1 10 0xff01>;
  316. };
  317. soc {
  318. compatible = "simple-bus";
  319. #address-cells = <2>;
  320. #size-cells = <2>;
  321. ranges;
  322. refclk50mhz: refclk50mhz {
  323. compatible = "fixed-clock";
  324. #clock-cells = <0>;
  325. clock-frequency = <50000000>;
  326. clock-output-names = "refclk50mhz";
  327. };
  328. gic0: interrupt-controller@8010,00000000 {
  329. compatible = "arm,gic-v3";
  330. #interrupt-cells = <3>;
  331. interrupt-controller;
  332. reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
  333. <0x8010 0x80000000 0x0 0x600000>; /* GICR */
  334. interrupts = <1 9 0xf04>;
  335. };
  336. uaa0: serial@87e0,24000000 {
  337. compatible = "arm,pl011", "arm,primecell";
  338. reg = <0x87e0 0x24000000 0x0 0x1000>;
  339. interrupts = <1 21 4>;
  340. clocks = <&refclk50mhz>;
  341. clock-names = "apb_pclk";
  342. uboot,skip-init;
  343. };
  344. uaa1: serial@87e0,25000000 {
  345. compatible = "arm,pl011", "arm,primecell";
  346. reg = <0x87e0 0x25000000 0x0 0x1000>;
  347. interrupts = <1 22 4>;
  348. clocks = <&refclk50mhz>;
  349. clock-names = "apb_pclk";
  350. uboot,skip-init;
  351. };
  352. };
  353. };