tegra30-apalis.dts 6.9 KB

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  1. /dts-v1/;
  2. #include "tegra30.dtsi"
  3. / {
  4. model = "Toradex Apalis T30";
  5. compatible = "toradex,apalis_t30", "nvidia,tegra30";
  6. chosen {
  7. stdout-path = &uarta;
  8. };
  9. aliases {
  10. i2c0 = "/i2c@7000d000";
  11. i2c1 = "/i2c@7000c000";
  12. i2c2 = "/i2c@7000c500";
  13. i2c3 = "/i2c@7000c700";
  14. mmc0 = "/sdhci@78000600";
  15. mmc1 = "/sdhci@78000400";
  16. mmc2 = "/sdhci@78000000";
  17. spi0 = "/spi@7000d400";
  18. spi1 = "/spi@7000dc00";
  19. spi2 = "/spi@7000de00";
  20. spi3 = "/spi@7000da00";
  21. usb0 = "/usb@7d000000";
  22. usb1 = "/usb@7d004000";
  23. usb2 = "/usb@7d008000";
  24. };
  25. memory {
  26. device_type = "memory";
  27. reg = <0x80000000 0x40000000>;
  28. };
  29. pcie-controller@00003000 {
  30. status = "okay";
  31. avdd-pexa-supply = <&vdd2_reg>;
  32. vdd-pexa-supply = <&vdd2_reg>;
  33. avdd-pexb-supply = <&vdd2_reg>;
  34. vdd-pexb-supply = <&vdd2_reg>;
  35. avdd-pex-pll-supply = <&vdd2_reg>;
  36. avdd-plle-supply = <&ldo6_reg>;
  37. vddio-pex-ctl-supply = <&sys_3v3_reg>;
  38. hvdd-pex-supply = <&sys_3v3_reg>;
  39. pci@1,0 {
  40. /* TS_DIFF1/2/3/4 left disabled */
  41. nvidia,num-lanes = <4>;
  42. };
  43. pci@2,0 {
  44. /* PCIE1_RX/TX left disabled */
  45. nvidia,num-lanes = <1>;
  46. };
  47. pci@3,0 {
  48. status = "okay";
  49. nvidia,num-lanes = <1>;
  50. };
  51. };
  52. /*
  53. * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
  54. * board)
  55. */
  56. i2c@7000c000 {
  57. status = "okay";
  58. clock-frequency = <100000>;
  59. };
  60. /* GEN2_I2C: unused */
  61. /*
  62. * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
  63. * carrier board)
  64. */
  65. i2c@7000c500 {
  66. status = "okay";
  67. clock-frequency = <100000>;
  68. };
  69. /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
  70. i2c@7000c700 {
  71. status = "okay";
  72. clock-frequency = <100000>;
  73. };
  74. /*
  75. * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
  76. * touch screen controller
  77. */
  78. i2c@7000d000 {
  79. status = "okay";
  80. clock-frequency = <100000>;
  81. pmic: tps65911@2d {
  82. compatible = "ti,tps65911";
  83. reg = <0x2d>;
  84. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  85. #interrupt-cells = <2>;
  86. interrupt-controller;
  87. ti,system-power-controller;
  88. #gpio-cells = <2>;
  89. gpio-controller;
  90. vcc1-supply = <&sys_3v3_reg>;
  91. vcc2-supply = <&sys_3v3_reg>;
  92. vcc3-supply = <&vio_reg>;
  93. vcc4-supply = <&sys_3v3_reg>;
  94. vcc5-supply = <&sys_3v3_reg>;
  95. vcc6-supply = <&vio_reg>;
  96. vcc7-supply = <&charge_pump_5v0_reg>;
  97. vccio-supply = <&sys_3v3_reg>;
  98. regulators {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. /* SW1: +V1.35_VDDIO_DDR */
  102. vdd1_reg: vdd1 {
  103. regulator-name = "vddio_ddr_1v35";
  104. regulator-min-microvolt = <1350000>;
  105. regulator-max-microvolt = <1350000>;
  106. regulator-always-on;
  107. };
  108. /* SW2: +V1.05 */
  109. vdd2_reg: vdd2 {
  110. regulator-name =
  111. "vdd_pexa,vdd_pexb,vdd_sata";
  112. regulator-min-microvolt = <1050000>;
  113. regulator-max-microvolt = <1050000>;
  114. };
  115. /* SW CTRL: +V1.0_VDD_CPU */
  116. vddctrl_reg: vddctrl {
  117. regulator-name = "vdd_cpu,vdd_sys";
  118. regulator-min-microvolt = <1150000>;
  119. regulator-max-microvolt = <1150000>;
  120. regulator-always-on;
  121. };
  122. /* SWIO: +V1.8 */
  123. vio_reg: vio {
  124. regulator-name = "vdd_1v8_gen";
  125. regulator-min-microvolt = <1800000>;
  126. regulator-max-microvolt = <1800000>;
  127. regulator-always-on;
  128. };
  129. /* LDO1: unused */
  130. /*
  131. * EN_+V3.3 switching via FET:
  132. * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
  133. * see also v3_3 fixed supply
  134. */
  135. ldo2_reg: ldo2 {
  136. regulator-name = "en_3v3";
  137. regulator-min-microvolt = <3300000>;
  138. regulator-max-microvolt = <3300000>;
  139. regulator-always-on;
  140. };
  141. /* +V1.2_CSI */
  142. ldo3_reg: ldo3 {
  143. regulator-name =
  144. "avdd_dsi_csi,pwrdet_mipi";
  145. regulator-min-microvolt = <1200000>;
  146. regulator-max-microvolt = <1200000>;
  147. };
  148. /* +V1.2_VDD_RTC */
  149. ldo4_reg: ldo4 {
  150. regulator-name = "vdd_rtc";
  151. regulator-min-microvolt = <1200000>;
  152. regulator-max-microvolt = <1200000>;
  153. regulator-always-on;
  154. };
  155. /*
  156. * +V2.8_AVDD_VDAC:
  157. * only required for analog RGB
  158. */
  159. ldo5_reg: ldo5 {
  160. regulator-name = "avdd_vdac";
  161. regulator-min-microvolt = <2800000>;
  162. regulator-max-microvolt = <2800000>;
  163. regulator-always-on;
  164. };
  165. /*
  166. * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
  167. * but LDO6 can't set voltage in 50mV
  168. * granularity
  169. */
  170. ldo6_reg: ldo6 {
  171. regulator-name = "avdd_plle";
  172. regulator-min-microvolt = <1100000>;
  173. regulator-max-microvolt = <1100000>;
  174. };
  175. /* +V1.2_AVDD_PLL */
  176. ldo7_reg: ldo7 {
  177. regulator-name = "avdd_pll";
  178. regulator-min-microvolt = <1200000>;
  179. regulator-max-microvolt = <1200000>;
  180. regulator-always-on;
  181. };
  182. /* +V1.0_VDD_DDR_HS */
  183. ldo8_reg: ldo8 {
  184. regulator-name = "vdd_ddr_hs";
  185. regulator-min-microvolt = <1000000>;
  186. regulator-max-microvolt = <1000000>;
  187. regulator-always-on;
  188. };
  189. };
  190. };
  191. };
  192. /* SPI1: Apalis SPI1 */
  193. spi@7000d400 {
  194. status = "okay";
  195. spi-max-frequency = <25000000>;
  196. };
  197. /* SPI4: CAN2 */
  198. spi@7000da00 {
  199. status = "okay";
  200. spi-max-frequency = <25000000>;
  201. };
  202. /* SPI5: Apalis SPI2 */
  203. spi@7000dc00 {
  204. status = "okay";
  205. spi-max-frequency = <25000000>;
  206. };
  207. /* SPI6: CAN1 */
  208. spi@7000de00 {
  209. status = "okay";
  210. spi-max-frequency = <25000000>;
  211. };
  212. sdhci@78000000 {
  213. status = "okay";
  214. bus-width = <4>;
  215. /* SD1_CD# */
  216. cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
  217. };
  218. sdhci@78000400 {
  219. status = "okay";
  220. bus-width = <8>;
  221. /* MMC1_CD# */
  222. cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
  223. };
  224. sdhci@78000600 {
  225. status = "okay";
  226. bus-width = <8>;
  227. non-removable;
  228. };
  229. /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
  230. usb@7d000000 {
  231. status = "okay";
  232. dr_mode = "otg";
  233. /* USBO1_EN */
  234. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
  235. };
  236. /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
  237. usb@7d004000 {
  238. status = "okay";
  239. /* USBH_EN */
  240. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
  241. };
  242. /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
  243. usb@7d008000 {
  244. status = "okay";
  245. /* USBH_EN */
  246. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
  247. };
  248. clocks {
  249. compatible = "simple-bus";
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. clk32k_in: clk@0 {
  253. compatible = "fixed-clock";
  254. reg=<0>;
  255. #clock-cells = <0>;
  256. clock-frequency = <32768>;
  257. };
  258. clk16m: clk@1 {
  259. compatible = "fixed-clock";
  260. reg=<1>;
  261. #clock-cells = <0>;
  262. clock-frequency = <16000000>;
  263. clock-output-names = "clk16m";
  264. };
  265. };
  266. regulators {
  267. compatible = "simple-bus";
  268. #address-cells = <1>;
  269. #size-cells = <0>;
  270. sys_3v3_reg: regulator@100 {
  271. compatible = "regulator-fixed";
  272. reg = <100>;
  273. regulator-name = "3v3";
  274. regulator-min-microvolt = <3300000>;
  275. regulator-max-microvolt = <3300000>;
  276. regulator-always-on;
  277. };
  278. charge_pump_5v0_reg: regulator@101 {
  279. compatible = "regulator-fixed";
  280. reg = <101>;
  281. regulator-name = "5v0";
  282. regulator-min-microvolt = <5000000>;
  283. regulator-max-microvolt = <5000000>;
  284. regulator-always-on;
  285. };
  286. };
  287. };