tegra20-ventana.dts 16 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Tegra20 Ventana evaluation board";
  6. compatible = "nvidia,ventana", "nvidia,tegra20";
  7. chosen {
  8. stdout-path = &uartd;
  9. };
  10. aliases {
  11. rtc0 = "/i2c@7000d000/tps6586x@34";
  12. rtc1 = "/rtc@7000e000";
  13. serial0 = &uartd;
  14. usb0 = "/usb@c5000000";
  15. usb1 = "/usb@c5004000";
  16. usb2 = "/usb@c5008000";
  17. mmc0 = "/sdhci@c8000600";
  18. mmc1 = "/sdhci@c8000400";
  19. };
  20. memory {
  21. reg = <0x00000000 0x40000000>;
  22. };
  23. host1x@50000000 {
  24. status = "okay";
  25. dc@54200000 {
  26. status = "okay";
  27. rgb {
  28. status = "okay";
  29. nvidia,panel = <&panel>;
  30. display-timings {
  31. timing@0 {
  32. /* Seaboard has 1366x768 */
  33. clock-frequency = <70600000>;
  34. hactive = <1366>;
  35. vactive = <768>;
  36. hback-porch = <58>;
  37. hfront-porch = <58>;
  38. hsync-len = <58>;
  39. vback-porch = <4>;
  40. vfront-porch = <4>;
  41. vsync-len = <4>;
  42. hsync-active = <1>;
  43. };
  44. };
  45. };
  46. };
  47. hdmi@54280000 {
  48. status = "okay";
  49. vdd-supply = <&hdmi_vdd_reg>;
  50. pll-supply = <&hdmi_pll_reg>;
  51. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  52. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  53. GPIO_ACTIVE_HIGH>;
  54. };
  55. };
  56. pinmux@70000014 {
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&state_default>;
  59. state_default: pinmux {
  60. ata {
  61. nvidia,pins = "ata";
  62. nvidia,function = "ide";
  63. };
  64. atb {
  65. nvidia,pins = "atb", "gma", "gme";
  66. nvidia,function = "sdio4";
  67. };
  68. atc {
  69. nvidia,pins = "atc";
  70. nvidia,function = "nand";
  71. };
  72. atd {
  73. nvidia,pins = "atd", "ate", "gmb", "spia",
  74. "spib", "spic";
  75. nvidia,function = "gmi";
  76. };
  77. cdev1 {
  78. nvidia,pins = "cdev1";
  79. nvidia,function = "plla_out";
  80. };
  81. cdev2 {
  82. nvidia,pins = "cdev2";
  83. nvidia,function = "pllp_out4";
  84. };
  85. crtp {
  86. nvidia,pins = "crtp", "lm1";
  87. nvidia,function = "crt";
  88. };
  89. csus {
  90. nvidia,pins = "csus";
  91. nvidia,function = "vi_sensor_clk";
  92. };
  93. dap1 {
  94. nvidia,pins = "dap1";
  95. nvidia,function = "dap1";
  96. };
  97. dap2 {
  98. nvidia,pins = "dap2";
  99. nvidia,function = "dap2";
  100. };
  101. dap3 {
  102. nvidia,pins = "dap3";
  103. nvidia,function = "dap3";
  104. };
  105. dap4 {
  106. nvidia,pins = "dap4";
  107. nvidia,function = "dap4";
  108. };
  109. dta {
  110. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  111. nvidia,function = "vi";
  112. };
  113. dtf {
  114. nvidia,pins = "dtf";
  115. nvidia,function = "i2c3";
  116. };
  117. gmc {
  118. nvidia,pins = "gmc";
  119. nvidia,function = "uartd";
  120. };
  121. gmd {
  122. nvidia,pins = "gmd";
  123. nvidia,function = "sflash";
  124. };
  125. gpu {
  126. nvidia,pins = "gpu";
  127. nvidia,function = "pwm";
  128. };
  129. gpu7 {
  130. nvidia,pins = "gpu7";
  131. nvidia,function = "rtck";
  132. };
  133. gpv {
  134. nvidia,pins = "gpv", "slxa", "slxk";
  135. nvidia,function = "pcie";
  136. };
  137. hdint {
  138. nvidia,pins = "hdint";
  139. nvidia,function = "hdmi";
  140. };
  141. i2cp {
  142. nvidia,pins = "i2cp";
  143. nvidia,function = "i2cp";
  144. };
  145. irrx {
  146. nvidia,pins = "irrx", "irtx";
  147. nvidia,function = "uartb";
  148. };
  149. kbca {
  150. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  151. "kbce", "kbcf";
  152. nvidia,function = "kbc";
  153. };
  154. lcsn {
  155. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  156. "lsdi", "lvp0";
  157. nvidia,function = "rsvd4";
  158. };
  159. ld0 {
  160. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  161. "ld5", "ld6", "ld7", "ld8", "ld9",
  162. "ld10", "ld11", "ld12", "ld13", "ld14",
  163. "ld15", "ld16", "ld17", "ldi", "lhp0",
  164. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  165. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  166. "lspi", "lvp1", "lvs";
  167. nvidia,function = "displaya";
  168. };
  169. owc {
  170. nvidia,pins = "owc", "spdi", "spdo", "uac";
  171. nvidia,function = "rsvd2";
  172. };
  173. pmc {
  174. nvidia,pins = "pmc";
  175. nvidia,function = "pwr_on";
  176. };
  177. rm {
  178. nvidia,pins = "rm";
  179. nvidia,function = "i2c1";
  180. };
  181. sdb {
  182. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  183. nvidia,function = "sdio3";
  184. };
  185. sdio1 {
  186. nvidia,pins = "sdio1";
  187. nvidia,function = "sdio1";
  188. };
  189. slxd {
  190. nvidia,pins = "slxd";
  191. nvidia,function = "spdif";
  192. };
  193. spid {
  194. nvidia,pins = "spid", "spie", "spif";
  195. nvidia,function = "spi1";
  196. };
  197. spig {
  198. nvidia,pins = "spig", "spih";
  199. nvidia,function = "spi2_alt";
  200. };
  201. uaa {
  202. nvidia,pins = "uaa", "uab", "uda";
  203. nvidia,function = "ulpi";
  204. };
  205. uad {
  206. nvidia,pins = "uad";
  207. nvidia,function = "irda";
  208. };
  209. uca {
  210. nvidia,pins = "uca", "ucb";
  211. nvidia,function = "uartc";
  212. };
  213. conf_ata {
  214. nvidia,pins = "ata", "atb", "atc", "atd",
  215. "cdev1", "cdev2", "dap1", "dap2",
  216. "dap4", "ddc", "dtf", "gma", "gmc",
  217. "gme", "gpu", "gpu7", "i2cp", "irrx",
  218. "irtx", "pta", "rm", "sdc", "sdd",
  219. "slxc", "slxd", "slxk", "spdi", "spdo",
  220. "uac", "uad", "uca", "ucb", "uda";
  221. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  222. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  223. };
  224. conf_ate {
  225. nvidia,pins = "ate", "csus", "dap3", "gmd",
  226. "gpv", "owc", "spia", "spib", "spic",
  227. "spid", "spie", "spig";
  228. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. };
  231. conf_ck32 {
  232. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  233. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  234. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  235. };
  236. conf_crtp {
  237. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  238. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  239. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  240. };
  241. conf_dta {
  242. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  243. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  244. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  245. };
  246. conf_dte {
  247. nvidia,pins = "dte", "spif";
  248. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  249. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  250. };
  251. conf_hdint {
  252. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  253. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  254. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  255. };
  256. conf_kbca {
  257. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  258. "kbce", "kbcf", "sdio1", "uaa", "uab";
  259. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  261. };
  262. conf_lc {
  263. nvidia,pins = "lc", "ls";
  264. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  265. };
  266. conf_ld0 {
  267. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  268. "ld5", "ld6", "ld7", "ld8", "ld9",
  269. "ld10", "ld11", "ld12", "ld13", "ld14",
  270. "ld15", "ld16", "ld17", "ldi", "lhp0",
  271. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  272. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  273. "lvp1", "lvs", "pmc", "sdb";
  274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  275. };
  276. conf_ld17_0 {
  277. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  278. "ld23_22";
  279. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  280. };
  281. drive_sdio1 {
  282. nvidia,pins = "drive_sdio1";
  283. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  284. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  285. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  286. nvidia,pull-down-strength = <31>;
  287. nvidia,pull-up-strength = <31>;
  288. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  289. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  290. };
  291. };
  292. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  293. ddc {
  294. nvidia,pins = "ddc";
  295. nvidia,function = "i2c2";
  296. };
  297. pta {
  298. nvidia,pins = "pta";
  299. nvidia,function = "rsvd4";
  300. };
  301. };
  302. state_i2cmux_pta: pinmux_i2cmux_pta {
  303. ddc {
  304. nvidia,pins = "ddc";
  305. nvidia,function = "rsvd4";
  306. };
  307. pta {
  308. nvidia,pins = "pta";
  309. nvidia,function = "i2c2";
  310. };
  311. };
  312. state_i2cmux_idle: pinmux_i2cmux_idle {
  313. ddc {
  314. nvidia,pins = "ddc";
  315. nvidia,function = "rsvd4";
  316. };
  317. pta {
  318. nvidia,pins = "pta";
  319. nvidia,function = "rsvd4";
  320. };
  321. };
  322. };
  323. i2s@70002800 {
  324. status = "okay";
  325. };
  326. serial@70006300 {
  327. status = "okay";
  328. clock-frequency = < 216000000 >; };
  329. pwm: pwm@7000a000 {
  330. status = "okay";
  331. };
  332. i2c@7000c000 {
  333. status = "okay";
  334. clock-frequency = <400000>;
  335. wm8903: wm8903@1a {
  336. compatible = "wlf,wm8903";
  337. reg = <0x1a>;
  338. interrupt-parent = <&gpio>;
  339. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  340. gpio-controller;
  341. #gpio-cells = <2>;
  342. micdet-cfg = <0>;
  343. micdet-delay = <100>;
  344. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  345. };
  346. /* ALS and proximity sensor */
  347. isl29018@44 {
  348. compatible = "isil,isl29018";
  349. reg = <0x44>;
  350. interrupt-parent = <&gpio>;
  351. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  352. };
  353. };
  354. i2c@7000c400 {
  355. status = "okay";
  356. clock-frequency = <100000>;
  357. };
  358. i2cmux {
  359. compatible = "i2c-mux-pinctrl";
  360. #address-cells = <1>;
  361. #size-cells = <0>;
  362. i2c-parent = <&{/i2c@7000c400}>;
  363. pinctrl-names = "ddc", "pta", "idle";
  364. pinctrl-0 = <&state_i2cmux_ddc>;
  365. pinctrl-1 = <&state_i2cmux_pta>;
  366. pinctrl-2 = <&state_i2cmux_idle>;
  367. hdmi_ddc: i2c@0 {
  368. reg = <0>;
  369. #address-cells = <1>;
  370. #size-cells = <0>;
  371. };
  372. lvds_ddc: i2c@1 {
  373. reg = <1>;
  374. #address-cells = <1>;
  375. #size-cells = <0>;
  376. };
  377. };
  378. i2c@7000c500 {
  379. status = "okay";
  380. clock-frequency = <400000>;
  381. };
  382. i2c@7000d000 {
  383. status = "okay";
  384. clock-frequency = <400000>;
  385. pmic: tps6586x@34 {
  386. compatible = "ti,tps6586x";
  387. reg = <0x34>;
  388. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  389. ti,system-power-controller;
  390. #gpio-cells = <2>;
  391. gpio-controller;
  392. sys-supply = <&vdd_5v0_reg>;
  393. vin-sm0-supply = <&sys_reg>;
  394. vin-sm1-supply = <&sys_reg>;
  395. vin-sm2-supply = <&sys_reg>;
  396. vinldo01-supply = <&sm2_reg>;
  397. vinldo23-supply = <&sm2_reg>;
  398. vinldo4-supply = <&sm2_reg>;
  399. vinldo678-supply = <&sm2_reg>;
  400. vinldo9-supply = <&sm2_reg>;
  401. regulators {
  402. sys_reg: sys {
  403. regulator-name = "vdd_sys";
  404. regulator-always-on;
  405. };
  406. sm0 {
  407. regulator-name = "vdd_sm0,vdd_core";
  408. regulator-min-microvolt = <1200000>;
  409. regulator-max-microvolt = <1200000>;
  410. regulator-always-on;
  411. };
  412. sm1 {
  413. regulator-name = "vdd_sm1,vdd_cpu";
  414. regulator-min-microvolt = <1000000>;
  415. regulator-max-microvolt = <1000000>;
  416. regulator-always-on;
  417. };
  418. sm2_reg: sm2 {
  419. regulator-name = "vdd_sm2,vin_ldo*";
  420. regulator-min-microvolt = <3700000>;
  421. regulator-max-microvolt = <3700000>;
  422. regulator-always-on;
  423. };
  424. /* LDO0 is not connected to anything */
  425. ldo1 {
  426. regulator-name = "vdd_ldo1,avdd_pll*";
  427. regulator-min-microvolt = <1100000>;
  428. regulator-max-microvolt = <1100000>;
  429. regulator-always-on;
  430. };
  431. ldo2 {
  432. regulator-name = "vdd_ldo2,vdd_rtc";
  433. regulator-min-microvolt = <1200000>;
  434. regulator-max-microvolt = <1200000>;
  435. };
  436. ldo3 {
  437. regulator-name = "vdd_ldo3,avdd_usb*";
  438. regulator-min-microvolt = <3300000>;
  439. regulator-max-microvolt = <3300000>;
  440. regulator-always-on;
  441. };
  442. ldo4 {
  443. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  444. regulator-min-microvolt = <1800000>;
  445. regulator-max-microvolt = <1800000>;
  446. regulator-always-on;
  447. };
  448. ldo5 {
  449. regulator-name = "vdd_ldo5,vcore_mmc";
  450. regulator-min-microvolt = <2850000>;
  451. regulator-max-microvolt = <2850000>;
  452. regulator-always-on;
  453. };
  454. ldo6 {
  455. regulator-name = "vdd_ldo6,avdd_vdac";
  456. regulator-min-microvolt = <1800000>;
  457. regulator-max-microvolt = <1800000>;
  458. };
  459. hdmi_vdd_reg: ldo7 {
  460. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  461. regulator-min-microvolt = <3300000>;
  462. regulator-max-microvolt = <3300000>;
  463. };
  464. hdmi_pll_reg: ldo8 {
  465. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  466. regulator-min-microvolt = <1800000>;
  467. regulator-max-microvolt = <1800000>;
  468. };
  469. ldo9 {
  470. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  471. regulator-min-microvolt = <2850000>;
  472. regulator-max-microvolt = <2850000>;
  473. regulator-always-on;
  474. };
  475. ldo_rtc {
  476. regulator-name = "vdd_rtc_out,vdd_cell";
  477. regulator-min-microvolt = <3300000>;
  478. regulator-max-microvolt = <3300000>;
  479. regulator-always-on;
  480. };
  481. };
  482. };
  483. temperature-sensor@4c {
  484. compatible = "onnn,nct1008";
  485. reg = <0x4c>;
  486. };
  487. };
  488. pmc@7000e400 {
  489. nvidia,invert-interrupt;
  490. nvidia,suspend-mode = <1>;
  491. nvidia,cpu-pwr-good-time = <2000>;
  492. nvidia,cpu-pwr-off-time = <100>;
  493. nvidia,core-pwr-good-time = <3845 3845>;
  494. nvidia,core-pwr-off-time = <458>;
  495. nvidia,sys-clock-req-active-high;
  496. };
  497. usb@c5000000 {
  498. status = "okay";
  499. };
  500. usb-phy@c5000000 {
  501. status = "okay";
  502. };
  503. usb@c5004000 {
  504. status = "okay";
  505. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  506. GPIO_ACTIVE_LOW>;
  507. };
  508. usb-phy@c5004000 {
  509. status = "okay";
  510. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  511. GPIO_ACTIVE_LOW>;
  512. };
  513. usb@c5008000 {
  514. status = "okay";
  515. };
  516. usb-phy@c5008000 {
  517. status = "okay";
  518. };
  519. sdhci@c8000000 {
  520. status = "okay";
  521. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  522. bus-width = <4>;
  523. keep-power-in-suspend;
  524. };
  525. sdhci@c8000400 {
  526. status = "okay";
  527. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  528. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  529. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  530. bus-width = <4>;
  531. };
  532. sdhci@c8000600 {
  533. status = "okay";
  534. bus-width = <8>;
  535. non-removable;
  536. };
  537. backlight: backlight {
  538. compatible = "pwm-backlight";
  539. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  540. power-supply = <&vdd_bl_reg>;
  541. pwms = <&pwm 2 5000000>;
  542. brightness-levels = <0 4 8 16 32 64 128 255>;
  543. default-brightness-level = <6>;
  544. };
  545. clocks {
  546. compatible = "simple-bus";
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. clk32k_in: clock@0 {
  550. compatible = "fixed-clock";
  551. reg=<0>;
  552. #clock-cells = <0>;
  553. clock-frequency = <32768>;
  554. };
  555. };
  556. gpio-keys {
  557. compatible = "gpio-keys";
  558. power {
  559. label = "Power";
  560. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  561. linux,code = <KEY_POWER>;
  562. gpio-key,wakeup;
  563. };
  564. };
  565. panel: panel {
  566. compatible = "chunghwa,claa101wa01a", "simple-panel";
  567. power-supply = <&vdd_pnl_reg>;
  568. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  569. backlight = <&backlight>;
  570. ddc-i2c-bus = <&lvds_ddc>;
  571. };
  572. regulators {
  573. compatible = "simple-bus";
  574. #address-cells = <1>;
  575. #size-cells = <0>;
  576. vdd_5v0_reg: regulator@0 {
  577. compatible = "regulator-fixed";
  578. reg = <0>;
  579. regulator-name = "vdd_5v0";
  580. regulator-min-microvolt = <5000000>;
  581. regulator-max-microvolt = <5000000>;
  582. regulator-always-on;
  583. };
  584. regulator@1 {
  585. compatible = "regulator-fixed";
  586. reg = <1>;
  587. regulator-name = "vdd_1v5";
  588. regulator-min-microvolt = <1500000>;
  589. regulator-max-microvolt = <1500000>;
  590. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  591. };
  592. regulator@2 {
  593. compatible = "regulator-fixed";
  594. reg = <2>;
  595. regulator-name = "vdd_1v2";
  596. regulator-min-microvolt = <1200000>;
  597. regulator-max-microvolt = <1200000>;
  598. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  599. enable-active-high;
  600. };
  601. vdd_pnl_reg: regulator@3 {
  602. compatible = "regulator-fixed";
  603. reg = <3>;
  604. regulator-name = "vdd_pnl";
  605. regulator-min-microvolt = <2800000>;
  606. regulator-max-microvolt = <2800000>;
  607. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  608. enable-active-high;
  609. };
  610. vdd_bl_reg: regulator@4 {
  611. compatible = "regulator-fixed";
  612. reg = <4>;
  613. regulator-name = "vdd_bl";
  614. regulator-min-microvolt = <2800000>;
  615. regulator-max-microvolt = <2800000>;
  616. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  617. enable-active-high;
  618. };
  619. };
  620. sound {
  621. compatible = "nvidia,tegra-audio-wm8903-ventana",
  622. "nvidia,tegra-audio-wm8903";
  623. nvidia,model = "NVIDIA Tegra Ventana";
  624. nvidia,audio-routing =
  625. "Headphone Jack", "HPOUTR",
  626. "Headphone Jack", "HPOUTL",
  627. "Int Spk", "ROP",
  628. "Int Spk", "RON",
  629. "Int Spk", "LOP",
  630. "Int Spk", "LON",
  631. "Mic Jack", "MICBIAS",
  632. "IN1L", "Mic Jack";
  633. nvidia,i2s-controller = <&tegra_i2s1>;
  634. nvidia,audio-codec = <&wm8903>;
  635. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  636. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
  637. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  638. GPIO_ACTIVE_HIGH>;
  639. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  640. GPIO_ACTIVE_HIGH>;
  641. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  642. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  643. <&tegra_car TEGRA20_CLK_CDEV1>;
  644. clock-names = "pll_a", "pll_a_out0", "mclk";
  645. };
  646. };