tegra20-seaboard.dts 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984
  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Seaboard";
  6. compatible = "nvidia,seaboard", "nvidia,tegra20";
  7. aliases {
  8. /* This defines the order of our ports */
  9. usb0 = "/usb@c5000000";
  10. usb1 = "/usb@c5004000";
  11. usb2 = "/usb@c5008000";
  12. i2c0 = "/i2c@7000d000";
  13. i2c1 = "/i2c@7000c000";
  14. i2c2 = "/i2c@7000c400";
  15. i2c3 = "/i2c@7000c500";
  16. rtc0 = "/i2c@7000d000/tps6586x@34";
  17. rtc1 = "/rtc@7000e000";
  18. serial0 = &uartd;
  19. mmc0 = "/sdhci@c8000600";
  20. mmc1 = "/sdhci@c8000400";
  21. };
  22. chosen {
  23. bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
  24. };
  25. chosen {
  26. stdout-path = &uartd;
  27. };
  28. memory {
  29. reg = <0x00000000 0x40000000>;
  30. };
  31. host1x@50000000 {
  32. status = "okay";
  33. dc@54200000 {
  34. status = "okay";
  35. rgb {
  36. status = "okay";
  37. nvidia,panel = <&panel>;
  38. display-timings {
  39. timing@0 {
  40. /* Seaboard has 1366x768 */
  41. clock-frequency = <70600000>;
  42. hactive = <1366>;
  43. vactive = <768>;
  44. hback-porch = <58>;
  45. hfront-porch = <58>;
  46. hsync-len = <58>;
  47. vback-porch = <4>;
  48. vfront-porch = <4>;
  49. vsync-len = <4>;
  50. hsync-active = <1>;
  51. };
  52. };
  53. };
  54. };
  55. hdmi@54280000 {
  56. status = "okay";
  57. vdd-supply = <&hdmi_vdd_reg>;
  58. pll-supply = <&hdmi_pll_reg>;
  59. hdmi-supply = <&vdd_hdmi>;
  60. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  61. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  62. GPIO_ACTIVE_HIGH>;
  63. };
  64. };
  65. pinmux@70000014 {
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&state_default>;
  68. state_default: pinmux {
  69. ata {
  70. nvidia,pins = "ata";
  71. nvidia,function = "ide";
  72. };
  73. atb {
  74. nvidia,pins = "atb", "gma", "gme";
  75. nvidia,function = "sdio4";
  76. };
  77. atc {
  78. nvidia,pins = "atc";
  79. nvidia,function = "nand";
  80. };
  81. atd {
  82. nvidia,pins = "atd", "ate", "gmb", "spia",
  83. "spib", "spic";
  84. nvidia,function = "gmi";
  85. };
  86. cdev1 {
  87. nvidia,pins = "cdev1";
  88. nvidia,function = "plla_out";
  89. };
  90. cdev2 {
  91. nvidia,pins = "cdev2";
  92. nvidia,function = "pllp_out4";
  93. };
  94. crtp {
  95. nvidia,pins = "crtp", "lm1";
  96. nvidia,function = "crt";
  97. };
  98. csus {
  99. nvidia,pins = "csus";
  100. nvidia,function = "vi_sensor_clk";
  101. };
  102. dap1 {
  103. nvidia,pins = "dap1";
  104. nvidia,function = "dap1";
  105. };
  106. dap2 {
  107. nvidia,pins = "dap2";
  108. nvidia,function = "dap2";
  109. };
  110. dap3 {
  111. nvidia,pins = "dap3";
  112. nvidia,function = "dap3";
  113. };
  114. dap4 {
  115. nvidia,pins = "dap4";
  116. nvidia,function = "dap4";
  117. };
  118. dta {
  119. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  120. nvidia,function = "vi";
  121. };
  122. dtf {
  123. nvidia,pins = "dtf";
  124. nvidia,function = "i2c3";
  125. };
  126. gmc {
  127. nvidia,pins = "gmc";
  128. nvidia,function = "uartd";
  129. };
  130. gmd {
  131. nvidia,pins = "gmd";
  132. nvidia,function = "sflash";
  133. };
  134. gpu {
  135. nvidia,pins = "gpu";
  136. nvidia,function = "pwm";
  137. };
  138. gpu7 {
  139. nvidia,pins = "gpu7";
  140. nvidia,function = "rtck";
  141. };
  142. gpv {
  143. nvidia,pins = "gpv", "slxa", "slxk";
  144. nvidia,function = "pcie";
  145. };
  146. hdint {
  147. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  148. "lsck", "lsda";
  149. nvidia,function = "hdmi";
  150. };
  151. i2cp {
  152. nvidia,pins = "i2cp";
  153. nvidia,function = "i2cp";
  154. };
  155. irrx {
  156. nvidia,pins = "irrx", "irtx";
  157. nvidia,function = "uartb";
  158. };
  159. kbca {
  160. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  161. "kbce", "kbcf";
  162. nvidia,function = "kbc";
  163. };
  164. lcsn {
  165. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  166. "lsdi", "lvp0";
  167. nvidia,function = "rsvd4";
  168. };
  169. ld0 {
  170. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  171. "ld5", "ld6", "ld7", "ld8", "ld9",
  172. "ld10", "ld11", "ld12", "ld13", "ld14",
  173. "ld15", "ld16", "ld17", "ldi", "lhp0",
  174. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  175. "lspi", "lvp1", "lvs";
  176. nvidia,function = "displaya";
  177. };
  178. owc {
  179. nvidia,pins = "owc", "spdi", "spdo", "uac";
  180. nvidia,function = "rsvd2";
  181. };
  182. pmc {
  183. nvidia,pins = "pmc";
  184. nvidia,function = "pwr_on";
  185. };
  186. rm {
  187. nvidia,pins = "rm";
  188. nvidia,function = "i2c1";
  189. };
  190. sdb {
  191. nvidia,pins = "sdb", "sdc", "sdd";
  192. nvidia,function = "sdio3";
  193. };
  194. sdio1 {
  195. nvidia,pins = "sdio1";
  196. nvidia,function = "sdio1";
  197. };
  198. slxc {
  199. nvidia,pins = "slxc", "slxd";
  200. nvidia,function = "spdif";
  201. };
  202. spid {
  203. nvidia,pins = "spid", "spie", "spif";
  204. nvidia,function = "spi1";
  205. };
  206. spig {
  207. nvidia,pins = "spig", "spih";
  208. nvidia,function = "spi2_alt";
  209. };
  210. uaa {
  211. nvidia,pins = "uaa", "uab", "uda";
  212. nvidia,function = "ulpi";
  213. };
  214. uad {
  215. nvidia,pins = "uad";
  216. nvidia,function = "irda";
  217. };
  218. uca {
  219. nvidia,pins = "uca", "ucb";
  220. nvidia,function = "uartc";
  221. };
  222. conf_ata {
  223. nvidia,pins = "ata", "atb", "atc", "atd",
  224. "cdev1", "cdev2", "dap1", "dap2",
  225. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  226. "gme", "gpu", "gpu7", "i2cp", "irrx",
  227. "irtx", "pta", "rm", "sdc", "sdd",
  228. "slxd", "slxk", "spdi", "spdo", "uac",
  229. "uad", "uca", "ucb", "uda";
  230. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. };
  233. conf_ate {
  234. nvidia,pins = "ate", "csus", "dap3",
  235. "gpv", "owc", "slxc", "spib", "spid",
  236. "spie";
  237. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  238. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  239. };
  240. conf_ck32 {
  241. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  242. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  243. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  244. };
  245. conf_crtp {
  246. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  247. "spig", "spih";
  248. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  249. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  250. };
  251. conf_dta {
  252. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  253. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  254. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  255. };
  256. conf_dte {
  257. nvidia,pins = "dte", "spif";
  258. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  259. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  260. };
  261. conf_hdint {
  262. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  263. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  264. "lvp0";
  265. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  266. };
  267. conf_kbca {
  268. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  269. "kbce", "kbcf", "sdio1", "spic", "uaa",
  270. "uab";
  271. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. };
  274. conf_lc {
  275. nvidia,pins = "lc", "ls";
  276. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  277. };
  278. conf_ld0 {
  279. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  280. "ld5", "ld6", "ld7", "ld8", "ld9",
  281. "ld10", "ld11", "ld12", "ld13", "ld14",
  282. "ld15", "ld16", "ld17", "ldi", "lhp0",
  283. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  284. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  285. "lvs", "pmc", "sdb";
  286. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  287. };
  288. conf_ld17_0 {
  289. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  290. "ld23_22";
  291. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  292. };
  293. drive_sdio1 {
  294. nvidia,pins = "drive_sdio1";
  295. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  296. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  297. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
  298. nvidia,pull-down-strength = <31>;
  299. nvidia,pull-up-strength = <31>;
  300. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  301. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
  302. };
  303. };
  304. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  305. ddc {
  306. nvidia,pins = "ddc";
  307. nvidia,function = "i2c2";
  308. };
  309. pta {
  310. nvidia,pins = "pta";
  311. nvidia,function = "rsvd4";
  312. };
  313. };
  314. state_i2cmux_pta: pinmux_i2cmux_pta {
  315. ddc {
  316. nvidia,pins = "ddc";
  317. nvidia,function = "rsvd4";
  318. };
  319. pta {
  320. nvidia,pins = "pta";
  321. nvidia,function = "i2c2";
  322. };
  323. };
  324. state_i2cmux_idle: pinmux_i2cmux_idle {
  325. ddc {
  326. nvidia,pins = "ddc";
  327. nvidia,function = "rsvd4";
  328. };
  329. pta {
  330. nvidia,pins = "pta";
  331. nvidia,function = "rsvd4";
  332. };
  333. };
  334. };
  335. i2s@70002800 {
  336. status = "okay";
  337. };
  338. serial@70006300 {
  339. status = "okay";
  340. clock-frequency = < 216000000 >;
  341. };
  342. nand-controller@70008000 {
  343. nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  344. nvidia,width = <8>;
  345. nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  346. nand@0 {
  347. reg = <0>;
  348. compatible = "hynix,hy27uf4g2b", "nand-flash";
  349. };
  350. };
  351. pwm: pwm@7000a000 {
  352. status = "okay";
  353. };
  354. i2c@7000c000 {
  355. status = "okay";
  356. clock-frequency = <400000>;
  357. wm8903: wm8903@1a {
  358. compatible = "wlf,wm8903";
  359. reg = <0x1a>;
  360. interrupt-parent = <&gpio>;
  361. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  362. gpio-controller;
  363. #gpio-cells = <2>;
  364. micdet-cfg = <0>;
  365. micdet-delay = <100>;
  366. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  367. };
  368. /* ALS and proximity sensor */
  369. isl29018@44 {
  370. compatible = "isil,isl29018";
  371. reg = <0x44>;
  372. interrupt-parent = <&gpio>;
  373. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  374. };
  375. gyrometer@68 {
  376. compatible = "invn,mpu3050";
  377. reg = <0x68>;
  378. interrupt-parent = <&gpio>;
  379. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
  380. };
  381. };
  382. i2c@7000c400 {
  383. status = "okay";
  384. clock-frequency = <100000>;
  385. };
  386. i2cmux {
  387. compatible = "i2c-mux-pinctrl";
  388. #address-cells = <1>;
  389. #size-cells = <0>;
  390. i2c-parent = <&{/i2c@7000c400}>;
  391. pinctrl-names = "ddc", "pta", "idle";
  392. pinctrl-0 = <&state_i2cmux_ddc>;
  393. pinctrl-1 = <&state_i2cmux_pta>;
  394. pinctrl-2 = <&state_i2cmux_idle>;
  395. hdmi_ddc: i2c@0 {
  396. reg = <0>;
  397. #address-cells = <1>;
  398. #size-cells = <0>;
  399. };
  400. lvds_ddc: i2c@1 {
  401. reg = <1>;
  402. #address-cells = <1>;
  403. #size-cells = <0>;
  404. smart-battery@b {
  405. compatible = "ti,bq20z75", "smart-battery-1.1";
  406. reg = <0xb>;
  407. ti,i2c-retry-count = <2>;
  408. ti,poll-retry-count = <10>;
  409. };
  410. };
  411. };
  412. i2c@7000c500 {
  413. status = "okay";
  414. clock-frequency = <400000>;
  415. };
  416. i2c@7000d000 {
  417. status = "okay";
  418. clock-frequency = <400000>;
  419. magnetometer@c {
  420. compatible = "asahi-kasei,ak8975";
  421. reg = <0xc>;
  422. interrupt-parent = <&gpio>;
  423. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
  424. };
  425. pmic: tps6586x@34 {
  426. compatible = "ti,tps6586x";
  427. reg = <0x34>;
  428. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  429. ti,system-power-controller;
  430. #gpio-cells = <2>;
  431. gpio-controller;
  432. sys-supply = <&vdd_5v0_reg>;
  433. vin-sm0-supply = <&sys_reg>;
  434. vin-sm1-supply = <&sys_reg>;
  435. vin-sm2-supply = <&sys_reg>;
  436. vinldo01-supply = <&sm2_reg>;
  437. vinldo23-supply = <&sm2_reg>;
  438. vinldo4-supply = <&sm2_reg>;
  439. vinldo678-supply = <&sm2_reg>;
  440. vinldo9-supply = <&sm2_reg>;
  441. regulators {
  442. sys_reg: sys {
  443. regulator-name = "vdd_sys";
  444. regulator-always-on;
  445. };
  446. sm0 {
  447. regulator-name = "vdd_sm0,vdd_core";
  448. regulator-min-microvolt = <1300000>;
  449. regulator-max-microvolt = <1300000>;
  450. regulator-always-on;
  451. };
  452. sm1 {
  453. regulator-name = "vdd_sm1,vdd_cpu";
  454. regulator-min-microvolt = <1125000>;
  455. regulator-max-microvolt = <1125000>;
  456. regulator-always-on;
  457. };
  458. sm2_reg: sm2 {
  459. regulator-name = "vdd_sm2,vin_ldo*";
  460. regulator-min-microvolt = <3700000>;
  461. regulator-max-microvolt = <3700000>;
  462. regulator-always-on;
  463. };
  464. /* LDO0 is not connected to anything */
  465. ldo1 {
  466. regulator-name = "vdd_ldo1,avdd_pll*";
  467. regulator-min-microvolt = <1100000>;
  468. regulator-max-microvolt = <1100000>;
  469. regulator-always-on;
  470. };
  471. ldo2 {
  472. regulator-name = "vdd_ldo2,vdd_rtc";
  473. regulator-min-microvolt = <1200000>;
  474. regulator-max-microvolt = <1200000>;
  475. };
  476. ldo3 {
  477. regulator-name = "vdd_ldo3,avdd_usb*";
  478. regulator-min-microvolt = <3300000>;
  479. regulator-max-microvolt = <3300000>;
  480. regulator-always-on;
  481. };
  482. ldo4 {
  483. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  484. regulator-min-microvolt = <1800000>;
  485. regulator-max-microvolt = <1800000>;
  486. regulator-always-on;
  487. };
  488. ldo5 {
  489. regulator-name = "vdd_ldo5,vcore_mmc";
  490. regulator-min-microvolt = <2850000>;
  491. regulator-max-microvolt = <2850000>;
  492. regulator-always-on;
  493. };
  494. ldo6 {
  495. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  496. regulator-min-microvolt = <1800000>;
  497. regulator-max-microvolt = <1800000>;
  498. };
  499. hdmi_vdd_reg: ldo7 {
  500. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  501. regulator-min-microvolt = <3300000>;
  502. regulator-max-microvolt = <3300000>;
  503. };
  504. hdmi_pll_reg: ldo8 {
  505. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  506. regulator-min-microvolt = <1800000>;
  507. regulator-max-microvolt = <1800000>;
  508. };
  509. ldo9 {
  510. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  511. regulator-min-microvolt = <2850000>;
  512. regulator-max-microvolt = <2850000>;
  513. regulator-always-on;
  514. };
  515. ldo_rtc {
  516. regulator-name = "vdd_rtc_out,vdd_cell";
  517. regulator-min-microvolt = <3300000>;
  518. regulator-max-microvolt = <3300000>;
  519. regulator-always-on;
  520. };
  521. };
  522. };
  523. temperature-sensor@4c {
  524. compatible = "onnn,nct1008";
  525. reg = <0x4c>;
  526. };
  527. };
  528. kbc@7000e200 {
  529. status = "okay";
  530. nvidia,debounce-delay-ms = <32>;
  531. nvidia,repeat-delay-ms = <160>;
  532. nvidia,ghost-filter;
  533. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  534. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  535. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  536. MATRIX_KEY(0x00, 0x03, KEY_S)
  537. MATRIX_KEY(0x00, 0x04, KEY_A)
  538. MATRIX_KEY(0x00, 0x05, KEY_Z)
  539. MATRIX_KEY(0x00, 0x07, KEY_FN)
  540. MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
  541. MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
  542. MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
  543. MATRIX_KEY(0x03, 0x00, KEY_5)
  544. MATRIX_KEY(0x03, 0x01, KEY_4)
  545. MATRIX_KEY(0x03, 0x02, KEY_R)
  546. MATRIX_KEY(0x03, 0x03, KEY_E)
  547. MATRIX_KEY(0x03, 0x04, KEY_F)
  548. MATRIX_KEY(0x03, 0x05, KEY_D)
  549. MATRIX_KEY(0x03, 0x06, KEY_X)
  550. MATRIX_KEY(0x04, 0x00, KEY_7)
  551. MATRIX_KEY(0x04, 0x01, KEY_6)
  552. MATRIX_KEY(0x04, 0x02, KEY_T)
  553. MATRIX_KEY(0x04, 0x03, KEY_H)
  554. MATRIX_KEY(0x04, 0x04, KEY_G)
  555. MATRIX_KEY(0x04, 0x05, KEY_V)
  556. MATRIX_KEY(0x04, 0x06, KEY_C)
  557. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  558. MATRIX_KEY(0x05, 0x00, KEY_9)
  559. MATRIX_KEY(0x05, 0x01, KEY_8)
  560. MATRIX_KEY(0x05, 0x02, KEY_U)
  561. MATRIX_KEY(0x05, 0x03, KEY_Y)
  562. MATRIX_KEY(0x05, 0x04, KEY_J)
  563. MATRIX_KEY(0x05, 0x05, KEY_N)
  564. MATRIX_KEY(0x05, 0x06, KEY_B)
  565. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  566. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  567. MATRIX_KEY(0x06, 0x01, KEY_0)
  568. MATRIX_KEY(0x06, 0x02, KEY_O)
  569. MATRIX_KEY(0x06, 0x03, KEY_I)
  570. MATRIX_KEY(0x06, 0x04, KEY_L)
  571. MATRIX_KEY(0x06, 0x05, KEY_K)
  572. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  573. MATRIX_KEY(0x06, 0x07, KEY_M)
  574. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  575. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  576. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  577. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  578. MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
  579. MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
  580. MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
  581. MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
  582. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  583. MATRIX_KEY(0x0B, 0x01, KEY_P)
  584. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  585. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  586. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  587. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  588. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  589. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  590. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  591. MATRIX_KEY(0x0C, 0x03, KEY_3)
  592. MATRIX_KEY(0x0C, 0x04, KEY_2)
  593. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  594. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  595. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  596. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  597. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  598. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  599. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  600. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  601. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  602. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  603. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  604. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  605. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  606. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  607. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  608. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  609. MATRIX_KEY(0x0E, 0x06, KEY_1)
  610. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  611. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  612. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  613. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  614. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  615. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  616. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  617. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  618. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  619. /* Software Handled Function Keys */
  620. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  621. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  622. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  623. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  624. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  625. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  626. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  627. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  628. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  629. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  630. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  631. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  632. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  633. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  634. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  635. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  636. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  637. MATRIX_KEY(0x1D, 0x04, KEY_END)
  638. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
  639. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  640. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
  641. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  642. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  643. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  644. MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
  645. };
  646. pmc@7000e400 {
  647. nvidia,invert-interrupt;
  648. nvidia,suspend-mode = <1>;
  649. nvidia,cpu-pwr-good-time = <5000>;
  650. nvidia,cpu-pwr-off-time = <5000>;
  651. nvidia,core-pwr-good-time = <3845 3845>;
  652. nvidia,core-pwr-off-time = <3875>;
  653. nvidia,sys-clock-req-active-high;
  654. };
  655. memory-controller@7000f400 {
  656. emc-table@190000 {
  657. reg = <190000>;
  658. compatible = "nvidia,tegra20-emc-table";
  659. clock-frequency = <190000>;
  660. nvidia,emc-registers = <0x0000000c 0x00000026
  661. 0x00000009 0x00000003 0x00000004 0x00000004
  662. 0x00000002 0x0000000c 0x00000003 0x00000003
  663. 0x00000002 0x00000001 0x00000004 0x00000005
  664. 0x00000004 0x00000009 0x0000000d 0x0000059f
  665. 0x00000000 0x00000003 0x00000003 0x00000003
  666. 0x00000003 0x00000001 0x0000000b 0x000000c8
  667. 0x00000003 0x00000007 0x00000004 0x0000000f
  668. 0x00000002 0x00000000 0x00000000 0x00000002
  669. 0x00000000 0x00000000 0x00000083 0xa06204ae
  670. 0x007dc010 0x00000000 0x00000000 0x00000000
  671. 0x00000000 0x00000000 0x00000000 0x00000000>;
  672. };
  673. emc-table@380000 {
  674. reg = <380000>;
  675. compatible = "nvidia,tegra20-emc-table";
  676. clock-frequency = <380000>;
  677. nvidia,emc-registers = <0x00000017 0x0000004b
  678. 0x00000012 0x00000006 0x00000004 0x00000005
  679. 0x00000003 0x0000000c 0x00000006 0x00000006
  680. 0x00000003 0x00000001 0x00000004 0x00000005
  681. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  682. 0x00000000 0x00000003 0x00000003 0x00000006
  683. 0x00000006 0x00000001 0x00000011 0x000000c8
  684. 0x00000003 0x0000000e 0x00000007 0x0000000f
  685. 0x00000002 0x00000000 0x00000000 0x00000002
  686. 0x00000000 0x00000000 0x00000083 0xe044048b
  687. 0x007d8010 0x00000000 0x00000000 0x00000000
  688. 0x00000000 0x00000000 0x00000000 0x00000000>;
  689. };
  690. };
  691. usb@c5000000 {
  692. status = "okay";
  693. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  694. dr_mode = "otg";
  695. };
  696. usb-phy@c5000000 {
  697. status = "okay";
  698. vbus-supply = <&vbus_reg>;
  699. dr_mode = "otg";
  700. };
  701. usb@c5004000 {
  702. status = "okay";
  703. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  704. GPIO_ACTIVE_LOW>;
  705. };
  706. usb-phy@c5004000 {
  707. status = "okay";
  708. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  709. GPIO_ACTIVE_LOW>;
  710. };
  711. usb@c5008000 {
  712. status = "okay";
  713. };
  714. usb-phy@c5008000 {
  715. status = "okay";
  716. };
  717. sdhci@c8000000 {
  718. status = "okay";
  719. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  720. bus-width = <4>;
  721. keep-power-in-suspend;
  722. };
  723. sdhci@c8000400 {
  724. status = "okay";
  725. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  726. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  727. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  728. bus-width = <4>;
  729. };
  730. sdhci@c8000600 {
  731. status = "okay";
  732. bus-width = <8>;
  733. non-removable;
  734. };
  735. backlight: backlight {
  736. compatible = "pwm-backlight";
  737. enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
  738. power-supply = <&vdd_bl_reg>;
  739. pwms = <&pwm 2 5000000>;
  740. brightness-levels = <0 4 8 16 32 64 128 255>;
  741. default-brightness-level = <6>;
  742. };
  743. clocks {
  744. compatible = "simple-bus";
  745. #address-cells = <1>;
  746. #size-cells = <0>;
  747. clk32k_in: clock@0 {
  748. compatible = "fixed-clock";
  749. reg=<0>;
  750. #clock-cells = <0>;
  751. clock-frequency = <32768>;
  752. };
  753. };
  754. gpio-keys {
  755. compatible = "gpio-keys";
  756. power {
  757. label = "Power";
  758. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  759. linux,code = <KEY_POWER>;
  760. gpio-key,wakeup;
  761. };
  762. lid {
  763. label = "Lid";
  764. gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  765. linux,input-type = <5>; /* EV_SW */
  766. linux,code = <0>; /* SW_LID */
  767. debounce-interval = <1>;
  768. gpio-key,wakeup;
  769. };
  770. };
  771. panel: panel {
  772. compatible = "chunghwa,claa101wa01a", "simple-panel";
  773. power-supply = <&vdd_pnl_reg>;
  774. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  775. backlight = <&backlight>;
  776. ddc-i2c-bus = <&lvds_ddc>;
  777. };
  778. regulators {
  779. compatible = "simple-bus";
  780. #address-cells = <1>;
  781. #size-cells = <0>;
  782. vdd_5v0_reg: regulator@0 {
  783. compatible = "regulator-fixed";
  784. reg = <0>;
  785. regulator-name = "vdd_5v0";
  786. regulator-min-microvolt = <5000000>;
  787. regulator-max-microvolt = <5000000>;
  788. regulator-always-on;
  789. };
  790. regulator@1 {
  791. compatible = "regulator-fixed";
  792. reg = <1>;
  793. regulator-name = "vdd_1v5";
  794. regulator-min-microvolt = <1500000>;
  795. regulator-max-microvolt = <1500000>;
  796. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  797. };
  798. regulator@2 {
  799. compatible = "regulator-fixed";
  800. reg = <2>;
  801. regulator-name = "vdd_1v2";
  802. regulator-min-microvolt = <1200000>;
  803. regulator-max-microvolt = <1200000>;
  804. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  805. enable-active-high;
  806. };
  807. vbus_reg: regulator@3 {
  808. compatible = "regulator-fixed";
  809. reg = <3>;
  810. regulator-name = "vdd_vbus_wup1";
  811. regulator-min-microvolt = <5000000>;
  812. regulator-max-microvolt = <5000000>;
  813. enable-active-high;
  814. gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
  815. regulator-always-on;
  816. regulator-boot-on;
  817. };
  818. vdd_pnl_reg: regulator@4 {
  819. compatible = "regulator-fixed";
  820. reg = <4>;
  821. regulator-name = "vdd_pnl";
  822. regulator-min-microvolt = <2800000>;
  823. regulator-max-microvolt = <2800000>;
  824. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  825. enable-active-high;
  826. };
  827. vdd_bl_reg: regulator@5 {
  828. compatible = "regulator-fixed";
  829. reg = <5>;
  830. regulator-name = "vdd_bl";
  831. regulator-min-microvolt = <2800000>;
  832. regulator-max-microvolt = <2800000>;
  833. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  834. enable-active-high;
  835. };
  836. vdd_hdmi: regulator@6 {
  837. compatible = "regulator-fixed";
  838. reg = <6>;
  839. regulator-name = "VDDIO_HDMI";
  840. regulator-min-microvolt = <5000000>;
  841. regulator-max-microvolt = <5000000>;
  842. gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  843. enable-active-high;
  844. vin-supply = <&vdd_5v0_reg>;
  845. };
  846. };
  847. sound {
  848. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  849. "nvidia,tegra-audio-wm8903";
  850. nvidia,model = "NVIDIA Tegra Seaboard";
  851. nvidia,audio-routing =
  852. "Headphone Jack", "HPOUTR",
  853. "Headphone Jack", "HPOUTL",
  854. "Int Spk", "ROP",
  855. "Int Spk", "RON",
  856. "Int Spk", "LOP",
  857. "Int Spk", "LON",
  858. "Mic Jack", "MICBIAS",
  859. "IN1R", "Mic Jack";
  860. nvidia,i2s-controller = <&tegra_i2s1>;
  861. nvidia,audio-codec = <&wm8903>;
  862. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  863. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  864. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  865. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  866. <&tegra_car TEGRA20_CLK_CDEV1>;
  867. clock-names = "pll_a", "pll_a_out0", "mclk";
  868. };
  869. };