tegra20-paz00.dts 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636
  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "Toshiba AC100 / Dynabook AZ";
  6. compatible = "compal,paz00", "nvidia,tegra20";
  7. chosen {
  8. stdout-path = &uarta;
  9. };
  10. aliases {
  11. rtc0 = "/i2c@7000d000/tps6586x@34";
  12. rtc1 = "/rtc@7000e000";
  13. serial0 = &uarta;
  14. serial1 = &uartc;
  15. usb0 = "/usb@c5000000";
  16. usb1 = "/usb@c5004000";
  17. usb2 = "/usb@c5008000";
  18. mmc0 = "/sdhci@c8000600";
  19. mmc1 = "/sdhci@c8000000";
  20. };
  21. memory {
  22. reg = <0x00000000 0x20000000>;
  23. };
  24. host1x@50000000 {
  25. status = "okay";
  26. dc@54200000 {
  27. status = "okay";
  28. rgb {
  29. status = "okay";
  30. nvidia,panel = <&panel>;
  31. display-timings {
  32. timing@0 {
  33. /* PAZ00 has 1024x600 */
  34. clock-frequency = <54030000>;
  35. hactive = <1024>;
  36. vactive = <600>;
  37. hback-porch = <160>;
  38. hfront-porch = <24>;
  39. hsync-len = <136>;
  40. vback-porch = <3>;
  41. vfront-porch = <61>;
  42. vsync-len = <6>;
  43. hsync-active = <1>;
  44. };
  45. };
  46. };
  47. };
  48. hdmi@54280000 {
  49. status = "okay";
  50. vdd-supply = <&hdmi_vdd_reg>;
  51. pll-supply = <&hdmi_pll_reg>;
  52. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  53. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  54. GPIO_ACTIVE_HIGH>;
  55. };
  56. };
  57. pinmux@70000014 {
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&state_default>;
  60. state_default: pinmux {
  61. ata {
  62. nvidia,pins = "ata", "atc", "atd", "ate",
  63. "dap2", "gmb", "gmc", "gmd", "spia",
  64. "spib", "spic", "spid", "spie";
  65. nvidia,function = "gmi";
  66. };
  67. atb {
  68. nvidia,pins = "atb", "gma", "gme";
  69. nvidia,function = "sdio4";
  70. };
  71. cdev1 {
  72. nvidia,pins = "cdev1";
  73. nvidia,function = "plla_out";
  74. };
  75. cdev2 {
  76. nvidia,pins = "cdev2";
  77. nvidia,function = "pllp_out4";
  78. };
  79. crtp {
  80. nvidia,pins = "crtp";
  81. nvidia,function = "crt";
  82. };
  83. csus {
  84. nvidia,pins = "csus";
  85. nvidia,function = "pllc_out1";
  86. };
  87. dap1 {
  88. nvidia,pins = "dap1";
  89. nvidia,function = "dap1";
  90. };
  91. dap3 {
  92. nvidia,pins = "dap3";
  93. nvidia,function = "dap3";
  94. };
  95. dap4 {
  96. nvidia,pins = "dap4";
  97. nvidia,function = "dap4";
  98. };
  99. ddc {
  100. nvidia,pins = "ddc";
  101. nvidia,function = "i2c2";
  102. };
  103. dta {
  104. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  105. nvidia,function = "rsvd1";
  106. };
  107. dtf {
  108. nvidia,pins = "dtf";
  109. nvidia,function = "i2c3";
  110. };
  111. gpu {
  112. nvidia,pins = "gpu", "sdb", "sdd";
  113. nvidia,function = "pwm";
  114. };
  115. gpu7 {
  116. nvidia,pins = "gpu7";
  117. nvidia,function = "rtck";
  118. };
  119. gpv {
  120. nvidia,pins = "gpv", "slxa", "slxk";
  121. nvidia,function = "pcie";
  122. };
  123. hdint {
  124. nvidia,pins = "hdint", "pta";
  125. nvidia,function = "hdmi";
  126. };
  127. i2cp {
  128. nvidia,pins = "i2cp";
  129. nvidia,function = "i2cp";
  130. };
  131. irrx {
  132. nvidia,pins = "irrx", "irtx";
  133. nvidia,function = "uarta";
  134. };
  135. kbca {
  136. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  137. nvidia,function = "kbc";
  138. };
  139. kbcb {
  140. nvidia,pins = "kbcb", "kbcd";
  141. nvidia,function = "sdio2";
  142. };
  143. lcsn {
  144. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  145. "ld3", "ld4", "ld5", "ld6", "ld7",
  146. "ld8", "ld9", "ld10", "ld11", "ld12",
  147. "ld13", "ld14", "ld15", "ld16", "ld17",
  148. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  149. "lhs", "lm0", "lm1", "lpp", "lpw0",
  150. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  151. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  152. "lvs";
  153. nvidia,function = "displaya";
  154. };
  155. owc {
  156. nvidia,pins = "owc";
  157. nvidia,function = "owr";
  158. };
  159. pmc {
  160. nvidia,pins = "pmc";
  161. nvidia,function = "pwr_on";
  162. };
  163. rm {
  164. nvidia,pins = "rm";
  165. nvidia,function = "i2c1";
  166. };
  167. sdc {
  168. nvidia,pins = "sdc";
  169. nvidia,function = "twc";
  170. };
  171. sdio1 {
  172. nvidia,pins = "sdio1";
  173. nvidia,function = "sdio1";
  174. };
  175. slxc {
  176. nvidia,pins = "slxc", "slxd";
  177. nvidia,function = "spi4";
  178. };
  179. spdi {
  180. nvidia,pins = "spdi", "spdo";
  181. nvidia,function = "rsvd2";
  182. };
  183. spif {
  184. nvidia,pins = "spif", "uac";
  185. nvidia,function = "rsvd4";
  186. };
  187. spig {
  188. nvidia,pins = "spig", "spih";
  189. nvidia,function = "spi2_alt";
  190. };
  191. uaa {
  192. nvidia,pins = "uaa", "uab", "uda";
  193. nvidia,function = "ulpi";
  194. };
  195. uad {
  196. nvidia,pins = "uad";
  197. nvidia,function = "spdif";
  198. };
  199. uca {
  200. nvidia,pins = "uca", "ucb";
  201. nvidia,function = "uartc";
  202. };
  203. conf_ata {
  204. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  205. "cdev1", "cdev2", "dap1", "dap2", "dtf",
  206. "gma", "gmb", "gmc", "gmd", "gme",
  207. "gpu", "gpu7", "gpv", "i2cp", "pta",
  208. "rm", "sdio1", "slxk", "spdo", "uac",
  209. "uda";
  210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  212. };
  213. conf_ck32 {
  214. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  215. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. };
  218. conf_crtp {
  219. nvidia,pins = "crtp", "dap3", "dap4", "dtb",
  220. "dtc", "dte", "slxa", "slxc", "slxd",
  221. "spdi";
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  224. };
  225. conf_csus {
  226. nvidia,pins = "csus", "spia", "spib", "spid",
  227. "spif";
  228. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. };
  231. conf_ddc {
  232. nvidia,pins = "ddc", "irrx", "irtx", "kbca",
  233. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  234. "spic", "spig", "uaa", "uab";
  235. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  236. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  237. };
  238. conf_dta {
  239. nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
  240. "spie", "spih", "uad", "uca", "ucb";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  243. };
  244. conf_hdint {
  245. nvidia,pins = "hdint", "ld0", "ld1", "ld2",
  246. "ld3", "ld4", "ld5", "ld6", "ld7",
  247. "ld8", "ld9", "ld10", "ld11", "ld12",
  248. "ld13", "ld14", "ld15", "ld16", "ld17",
  249. "ldc", "ldi", "lhs", "lsc0", "lspi",
  250. "lvs", "pmc";
  251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  252. };
  253. conf_lc {
  254. nvidia,pins = "lc", "ls";
  255. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  256. };
  257. conf_lcsn {
  258. nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
  259. "lm0", "lm1", "lpp", "lpw0", "lpw1",
  260. "lpw2", "lsc1", "lsck", "lsda", "lsdi",
  261. "lvp0", "lvp1", "sdb";
  262. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  263. };
  264. conf_ld17_0 {
  265. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  266. "ld23_22";
  267. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  268. };
  269. };
  270. };
  271. i2s@70002800 {
  272. status = "okay";
  273. };
  274. serial@70006000 {
  275. status = "okay";
  276. };
  277. serial@70006200 {
  278. status = "okay";
  279. };
  280. pwm: pwm@7000a000 {
  281. status = "okay";
  282. };
  283. lvds_ddc: i2c@7000c000 {
  284. status = "okay";
  285. clock-frequency = <400000>;
  286. alc5632: alc5632@1e {
  287. compatible = "realtek,alc5632";
  288. reg = <0x1e>;
  289. gpio-controller;
  290. #gpio-cells = <2>;
  291. };
  292. };
  293. hdmi_ddc: i2c@7000c400 {
  294. status = "okay";
  295. clock-frequency = <100000>;
  296. };
  297. nvec@7000c500 {
  298. compatible = "nvidia,nvec";
  299. reg = <0x7000c500 0x100>;
  300. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  301. #address-cells = <1>;
  302. #size-cells = <0>;
  303. clock-frequency = <80000>;
  304. request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  305. slave-addr = <138>;
  306. clocks = <&tegra_car TEGRA20_CLK_I2C3>,
  307. <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  308. clock-names = "div-clk", "fast-clk";
  309. resets = <&tegra_car 67>;
  310. reset-names = "i2c";
  311. };
  312. i2c@7000d000 {
  313. status = "okay";
  314. clock-frequency = <400000>;
  315. pmic: tps6586x@34 {
  316. compatible = "ti,tps6586x";
  317. reg = <0x34>;
  318. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  319. #gpio-cells = <2>;
  320. gpio-controller;
  321. sys-supply = <&p5valw_reg>;
  322. vin-sm0-supply = <&sys_reg>;
  323. vin-sm1-supply = <&sys_reg>;
  324. vin-sm2-supply = <&sys_reg>;
  325. vinldo01-supply = <&sm2_reg>;
  326. vinldo23-supply = <&sm2_reg>;
  327. vinldo4-supply = <&sm2_reg>;
  328. vinldo678-supply = <&sm2_reg>;
  329. vinldo9-supply = <&sm2_reg>;
  330. regulators {
  331. sys_reg: sys {
  332. regulator-name = "vdd_sys";
  333. regulator-always-on;
  334. };
  335. sm0 {
  336. regulator-name = "+1.2vs_sm0,vdd_core";
  337. regulator-min-microvolt = <1200000>;
  338. regulator-max-microvolt = <1200000>;
  339. regulator-always-on;
  340. };
  341. sm1 {
  342. regulator-name = "+1.0vs_sm1,vdd_cpu";
  343. regulator-min-microvolt = <1000000>;
  344. regulator-max-microvolt = <1000000>;
  345. regulator-always-on;
  346. };
  347. sm2_reg: sm2 {
  348. regulator-name = "+3.7vs_sm2,vin_ldo*";
  349. regulator-min-microvolt = <3700000>;
  350. regulator-max-microvolt = <3700000>;
  351. regulator-always-on;
  352. };
  353. /* LDO0 is not connected to anything */
  354. ldo1 {
  355. regulator-name = "+1.1vs_ldo1,avdd_pll*";
  356. regulator-min-microvolt = <1100000>;
  357. regulator-max-microvolt = <1100000>;
  358. regulator-always-on;
  359. };
  360. ldo2 {
  361. regulator-name = "+1.2vs_ldo2,vdd_rtc";
  362. regulator-min-microvolt = <1200000>;
  363. regulator-max-microvolt = <1200000>;
  364. };
  365. ldo3 {
  366. regulator-name = "+3.3vs_ldo3,avdd_usb*";
  367. regulator-min-microvolt = <3300000>;
  368. regulator-max-microvolt = <3300000>;
  369. regulator-always-on;
  370. };
  371. ldo4 {
  372. regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
  373. regulator-min-microvolt = <1800000>;
  374. regulator-max-microvolt = <1800000>;
  375. regulator-always-on;
  376. };
  377. ldo5 {
  378. regulator-name = "+2.85vs_ldo5,vcore_mmc";
  379. regulator-min-microvolt = <2850000>;
  380. regulator-max-microvolt = <2850000>;
  381. regulator-always-on;
  382. };
  383. ldo6 {
  384. /*
  385. * Research indicates this should be
  386. * 1.8v; other boards that use this
  387. * rail for the same purpose need it
  388. * set to 1.8v. The schematic signal
  389. * name is incorrect; perhaps copied
  390. * from an incorrect NVIDIA reference.
  391. */
  392. regulator-name = "+2.85vs_ldo6,avdd_vdac";
  393. regulator-min-microvolt = <1800000>;
  394. regulator-max-microvolt = <1800000>;
  395. };
  396. hdmi_vdd_reg: ldo7 {
  397. regulator-name = "+3.3vs_ldo7,avdd_hdmi";
  398. regulator-min-microvolt = <3300000>;
  399. regulator-max-microvolt = <3300000>;
  400. };
  401. hdmi_pll_reg: ldo8 {
  402. regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
  403. regulator-min-microvolt = <1800000>;
  404. regulator-max-microvolt = <1800000>;
  405. };
  406. ldo9 {
  407. regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
  408. regulator-min-microvolt = <2850000>;
  409. regulator-max-microvolt = <2850000>;
  410. regulator-always-on;
  411. };
  412. ldo_rtc {
  413. regulator-name = "+3.3vs_rtc";
  414. regulator-min-microvolt = <3300000>;
  415. regulator-max-microvolt = <3300000>;
  416. regulator-always-on;
  417. };
  418. };
  419. };
  420. adt7461@4c {
  421. compatible = "adi,adt7461";
  422. reg = <0x4c>;
  423. };
  424. };
  425. pmc@7000e400 {
  426. nvidia,invert-interrupt;
  427. nvidia,suspend-mode = <1>;
  428. nvidia,cpu-pwr-good-time = <2000>;
  429. nvidia,cpu-pwr-off-time = <0>;
  430. nvidia,core-pwr-good-time = <3845 3845>;
  431. nvidia,core-pwr-off-time = <0>;
  432. nvidia,sys-clock-req-active-high;
  433. };
  434. usb@c5000000 {
  435. status = "okay";
  436. };
  437. usb-phy@c5000000 {
  438. status = "okay";
  439. };
  440. usb@c5004000 {
  441. status = "okay";
  442. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  443. GPIO_ACTIVE_LOW>;
  444. };
  445. usb-phy@c5004000 {
  446. status = "okay";
  447. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  448. GPIO_ACTIVE_LOW>;
  449. };
  450. usb@c5008000 {
  451. status = "okay";
  452. };
  453. usb-phy@c5008000 {
  454. status = "okay";
  455. };
  456. sdhci@c8000000 {
  457. status = "okay";
  458. cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
  459. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  460. power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  461. bus-width = <4>;
  462. };
  463. sdhci@c8000600 {
  464. status = "okay";
  465. bus-width = <8>;
  466. non-removable;
  467. };
  468. backlight: backlight {
  469. compatible = "pwm-backlight";
  470. enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
  471. power-supply = <&vdd_bl_reg>;
  472. pwms = <&pwm 0 5000000>;
  473. brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
  474. default-brightness-level = <10>;
  475. backlight-boot-off;
  476. };
  477. clocks {
  478. compatible = "simple-bus";
  479. #address-cells = <1>;
  480. #size-cells = <0>;
  481. clk32k_in: clock@0 {
  482. compatible = "fixed-clock";
  483. reg = <0>;
  484. #clock-cells = <0>;
  485. clock-frequency = <32768>;
  486. };
  487. };
  488. gpio-keys {
  489. compatible = "gpio-keys";
  490. power {
  491. label = "Power";
  492. gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
  493. linux,code = <KEY_POWER>;
  494. wakeup-source;
  495. };
  496. };
  497. gpio-leds {
  498. compatible = "gpio-leds";
  499. wifi {
  500. label = "wifi-led";
  501. gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  502. linux,default-trigger = "rfkill0";
  503. };
  504. };
  505. panel: panel {
  506. compatible = "samsung,ltn101nt05", "simple-panel";
  507. ddc-i2c-bus = <&lvds_ddc>;
  508. power-supply = <&vdd_pnl_reg>;
  509. enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
  510. backlight = <&backlight>;
  511. };
  512. regulators {
  513. compatible = "simple-bus";
  514. #address-cells = <1>;
  515. #size-cells = <0>;
  516. p5valw_reg: regulator@0 {
  517. compatible = "regulator-fixed";
  518. reg = <0>;
  519. regulator-name = "+5valw";
  520. regulator-min-microvolt = <5000000>;
  521. regulator-max-microvolt = <5000000>;
  522. regulator-always-on;
  523. };
  524. vdd_pnl_reg: regulator@1 {
  525. compatible = "regulator-fixed";
  526. reg = <1>;
  527. regulator-name = "+3VS,vdd_pnl";
  528. regulator-min-microvolt = <3300000>;
  529. regulator-max-microvolt = <3300000>;
  530. gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
  531. enable-active-high;
  532. };
  533. vdd_bl_reg: regulator@2 {
  534. compatible = "regulator-fixed";
  535. reg = <2>;
  536. regulator-name = "vdd_bl";
  537. regulator-min-microvolt = <2800000>;
  538. regulator-max-microvolt = <2800000>;
  539. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  540. enable-active-high;
  541. };
  542. };
  543. sound {
  544. compatible = "nvidia,tegra-audio-alc5632-paz00",
  545. "nvidia,tegra-audio-alc5632";
  546. nvidia,model = "Compal PAZ00";
  547. nvidia,audio-routing =
  548. "Int Spk", "SPKOUT",
  549. "Int Spk", "SPKOUTN",
  550. "Headset Mic", "MICBIAS1",
  551. "MIC1", "Headset Mic",
  552. "Headset Stereophone", "HPR",
  553. "Headset Stereophone", "HPL",
  554. "DMICDAT", "Digital Mic";
  555. nvidia,audio-codec = <&alc5632>;
  556. nvidia,i2s-controller = <&tegra_i2s1>;
  557. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  558. GPIO_ACTIVE_HIGH>;
  559. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  560. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  561. <&tegra_car TEGRA20_CLK_CDEV1>;
  562. clock-names = "pll_a", "pll_a_out0", "mclk";
  563. };
  564. };