tegra20-harmony.dts 19 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Tegra20 Harmony evaluation board";
  6. compatible = "nvidia,harmony", "nvidia,tegra20";
  7. chosen {
  8. stdout-path = &uartd;
  9. };
  10. aliases {
  11. rtc0 = "/i2c@7000d000/tps6586x@34";
  12. rtc1 = "/rtc@7000e000";
  13. serial0 = &uartd;
  14. usb0 = "/usb@c5000000";
  15. usb1 = "/usb@c5004000";
  16. usb2 = "/usb@c5008000";
  17. mmc0 = "/sdhci@c8000600";
  18. mmc1 = "/sdhci@c8000200";
  19. };
  20. memory {
  21. reg = <0x00000000 0x40000000>;
  22. };
  23. host1x@50000000 {
  24. status = "okay";
  25. dc@54200000 {
  26. status = "okay";
  27. rgb {
  28. status = "okay";
  29. nvidia,panel = <&panel>;
  30. display-timings {
  31. timing@0 {
  32. /* Seaboard has 1366x768 */
  33. clock-frequency = <42430000>;
  34. hactive = <1024>;
  35. vactive = <600>;
  36. hback-porch = <138>;
  37. hfront-porch = <34>;
  38. hsync-len = <136>;
  39. vback-porch = <21>;
  40. vfront-porch = <4>;
  41. vsync-len = <4>;
  42. };
  43. };
  44. };
  45. };
  46. hdmi@54280000 {
  47. status = "okay";
  48. hdmi-supply = <&vdd_5v0_hdmi>;
  49. vdd-supply = <&hdmi_vdd_reg>;
  50. pll-supply = <&hdmi_pll_reg>;
  51. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  52. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  53. GPIO_ACTIVE_HIGH>;
  54. };
  55. };
  56. pinmux@70000014 {
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&state_default>;
  59. state_default: pinmux {
  60. ata {
  61. nvidia,pins = "ata";
  62. nvidia,function = "ide";
  63. };
  64. atb {
  65. nvidia,pins = "atb", "gma", "gme";
  66. nvidia,function = "sdio4";
  67. };
  68. atc {
  69. nvidia,pins = "atc";
  70. nvidia,function = "nand";
  71. };
  72. atd {
  73. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  74. "spia", "spib", "spic";
  75. nvidia,function = "gmi";
  76. };
  77. cdev1 {
  78. nvidia,pins = "cdev1";
  79. nvidia,function = "plla_out";
  80. };
  81. cdev2 {
  82. nvidia,pins = "cdev2";
  83. nvidia,function = "pllp_out4";
  84. };
  85. crtp {
  86. nvidia,pins = "crtp";
  87. nvidia,function = "crt";
  88. };
  89. csus {
  90. nvidia,pins = "csus";
  91. nvidia,function = "vi_sensor_clk";
  92. };
  93. dap1 {
  94. nvidia,pins = "dap1";
  95. nvidia,function = "dap1";
  96. };
  97. dap2 {
  98. nvidia,pins = "dap2";
  99. nvidia,function = "dap2";
  100. };
  101. dap3 {
  102. nvidia,pins = "dap3";
  103. nvidia,function = "dap3";
  104. };
  105. dap4 {
  106. nvidia,pins = "dap4";
  107. nvidia,function = "dap4";
  108. };
  109. ddc {
  110. nvidia,pins = "ddc";
  111. nvidia,function = "i2c2";
  112. };
  113. dta {
  114. nvidia,pins = "dta", "dtd";
  115. nvidia,function = "sdio2";
  116. };
  117. dtb {
  118. nvidia,pins = "dtb", "dtc", "dte";
  119. nvidia,function = "rsvd1";
  120. };
  121. dtf {
  122. nvidia,pins = "dtf";
  123. nvidia,function = "i2c3";
  124. };
  125. gmc {
  126. nvidia,pins = "gmc";
  127. nvidia,function = "uartd";
  128. };
  129. gpu7 {
  130. nvidia,pins = "gpu7";
  131. nvidia,function = "rtck";
  132. };
  133. gpv {
  134. nvidia,pins = "gpv", "slxa", "slxk";
  135. nvidia,function = "pcie";
  136. };
  137. hdint {
  138. nvidia,pins = "hdint", "pta";
  139. nvidia,function = "hdmi";
  140. };
  141. i2cp {
  142. nvidia,pins = "i2cp";
  143. nvidia,function = "i2cp";
  144. };
  145. irrx {
  146. nvidia,pins = "irrx", "irtx";
  147. nvidia,function = "uarta";
  148. };
  149. kbca {
  150. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  151. "kbce", "kbcf";
  152. nvidia,function = "kbc";
  153. };
  154. lcsn {
  155. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  156. "ld3", "ld4", "ld5", "ld6", "ld7",
  157. "ld8", "ld9", "ld10", "ld11", "ld12",
  158. "ld13", "ld14", "ld15", "ld16", "ld17",
  159. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  160. "lhs", "lm0", "lm1", "lpp", "lpw0",
  161. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  162. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  163. "lvs";
  164. nvidia,function = "displaya";
  165. };
  166. owc {
  167. nvidia,pins = "owc", "spdi", "spdo", "uac";
  168. nvidia,function = "rsvd2";
  169. };
  170. pmc {
  171. nvidia,pins = "pmc";
  172. nvidia,function = "pwr_on";
  173. };
  174. rm {
  175. nvidia,pins = "rm";
  176. nvidia,function = "i2c1";
  177. };
  178. sdb {
  179. nvidia,pins = "sdb", "sdc", "sdd";
  180. nvidia,function = "pwm";
  181. };
  182. sdio1 {
  183. nvidia,pins = "sdio1";
  184. nvidia,function = "sdio1";
  185. };
  186. slxc {
  187. nvidia,pins = "slxc", "slxd";
  188. nvidia,function = "spdif";
  189. };
  190. spid {
  191. nvidia,pins = "spid", "spie", "spif";
  192. nvidia,function = "spi1";
  193. };
  194. spig {
  195. nvidia,pins = "spig", "spih";
  196. nvidia,function = "spi2_alt";
  197. };
  198. uaa {
  199. nvidia,pins = "uaa", "uab", "uda";
  200. nvidia,function = "ulpi";
  201. };
  202. uad {
  203. nvidia,pins = "uad";
  204. nvidia,function = "irda";
  205. };
  206. uca {
  207. nvidia,pins = "uca", "ucb";
  208. nvidia,function = "uartc";
  209. };
  210. conf_ata {
  211. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  212. "cdev1", "cdev2", "dap1", "dtb", "gma",
  213. "gmb", "gmc", "gmd", "gme", "gpu7",
  214. "gpv", "i2cp", "pta", "rm", "slxa",
  215. "slxk", "spia", "spib", "uac";
  216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. };
  219. conf_ck32 {
  220. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  221. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  222. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  223. };
  224. conf_csus {
  225. nvidia,pins = "csus", "spid", "spif";
  226. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. };
  229. conf_crtp {
  230. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  231. "dtc", "dte", "dtf", "gpu", "sdio1",
  232. "slxc", "slxd", "spdi", "spdo", "spig",
  233. "uda";
  234. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  236. };
  237. conf_ddc {
  238. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  239. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  240. "sdc";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. };
  244. conf_hdint {
  245. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  246. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  247. "lvp0", "owc", "sdb";
  248. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  249. };
  250. conf_irrx {
  251. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  252. "spie", "spih", "uaa", "uab", "uad",
  253. "uca", "ucb";
  254. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  255. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  256. };
  257. conf_lc {
  258. nvidia,pins = "lc", "ls";
  259. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  260. };
  261. conf_ld0 {
  262. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  263. "ld5", "ld6", "ld7", "ld8", "ld9",
  264. "ld10", "ld11", "ld12", "ld13", "ld14",
  265. "ld15", "ld16", "ld17", "ldi", "lhp0",
  266. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  267. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  268. "lvs", "pmc";
  269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  270. };
  271. conf_ld17_0 {
  272. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  273. "ld23_22";
  274. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  275. };
  276. };
  277. };
  278. i2s@70002800 {
  279. status = "okay";
  280. };
  281. serial@70006300 {
  282. status = "okay";
  283. clock-frequency = < 216000000 >;
  284. };
  285. pwm: pwm@7000a000 {
  286. status = "okay";
  287. };
  288. i2c@7000c000 {
  289. status = "okay";
  290. clock-frequency = <400000>;
  291. wm8903: wm8903@1a {
  292. compatible = "wlf,wm8903";
  293. reg = <0x1a>;
  294. interrupt-parent = <&gpio>;
  295. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  296. gpio-controller;
  297. #gpio-cells = <2>;
  298. micdet-cfg = <0>;
  299. micdet-delay = <100>;
  300. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  301. };
  302. };
  303. nand-controller@70008000 {
  304. nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  305. nvidia,width = <8>;
  306. nvidia,timing = <26 100 20 80 20 10 12 10 70>;
  307. nand@0 {
  308. reg = <0>;
  309. compatible = "hynix,hy27uf4g2b", "nand-flash";
  310. };
  311. };
  312. hdmi_ddc: i2c@7000c400 {
  313. status = "okay";
  314. clock-frequency = <100000>;
  315. };
  316. i2c@7000c500 {
  317. status = "okay";
  318. clock-frequency = <400000>;
  319. };
  320. i2c@7000d000 {
  321. status = "okay";
  322. clock-frequency = <400000>;
  323. pmic: tps6586x@34 {
  324. compatible = "ti,tps6586x";
  325. reg = <0x34>;
  326. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  327. ti,system-power-controller;
  328. #gpio-cells = <2>;
  329. gpio-controller;
  330. sys-supply = <&vdd_5v0_reg>;
  331. vin-sm0-supply = <&sys_reg>;
  332. vin-sm1-supply = <&sys_reg>;
  333. vin-sm2-supply = <&sys_reg>;
  334. vinldo01-supply = <&sm2_reg>;
  335. vinldo23-supply = <&sm2_reg>;
  336. vinldo4-supply = <&sm2_reg>;
  337. vinldo678-supply = <&sm2_reg>;
  338. vinldo9-supply = <&sm2_reg>;
  339. regulators {
  340. sys_reg: sys {
  341. regulator-name = "vdd_sys";
  342. regulator-always-on;
  343. };
  344. sm0 {
  345. regulator-name = "vdd_sm0,vdd_core";
  346. regulator-min-microvolt = <1200000>;
  347. regulator-max-microvolt = <1200000>;
  348. regulator-always-on;
  349. };
  350. sm1 {
  351. regulator-name = "vdd_sm1,vdd_cpu";
  352. regulator-min-microvolt = <1000000>;
  353. regulator-max-microvolt = <1000000>;
  354. regulator-always-on;
  355. };
  356. sm2_reg: sm2 {
  357. regulator-name = "vdd_sm2,vin_ldo*";
  358. regulator-min-microvolt = <3700000>;
  359. regulator-max-microvolt = <3700000>;
  360. regulator-always-on;
  361. };
  362. pci_clk_reg: ldo0 {
  363. regulator-name = "vdd_ldo0,vddio_pex_clk";
  364. regulator-min-microvolt = <3300000>;
  365. regulator-max-microvolt = <3300000>;
  366. };
  367. ldo1 {
  368. regulator-name = "vdd_ldo1,avdd_pll*";
  369. regulator-min-microvolt = <1100000>;
  370. regulator-max-microvolt = <1100000>;
  371. regulator-always-on;
  372. };
  373. ldo2 {
  374. regulator-name = "vdd_ldo2,vdd_rtc";
  375. regulator-min-microvolt = <1200000>;
  376. regulator-max-microvolt = <1200000>;
  377. };
  378. ldo3 {
  379. regulator-name = "vdd_ldo3,avdd_usb*";
  380. regulator-min-microvolt = <3300000>;
  381. regulator-max-microvolt = <3300000>;
  382. regulator-always-on;
  383. };
  384. ldo4 {
  385. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  386. regulator-min-microvolt = <1800000>;
  387. regulator-max-microvolt = <1800000>;
  388. regulator-always-on;
  389. };
  390. ldo5 {
  391. regulator-name = "vdd_ldo5,vcore_mmc";
  392. regulator-min-microvolt = <2850000>;
  393. regulator-max-microvolt = <2850000>;
  394. regulator-always-on;
  395. };
  396. ldo6 {
  397. regulator-name = "vdd_ldo6,avdd_vdac";
  398. regulator-min-microvolt = <1800000>;
  399. regulator-max-microvolt = <1800000>;
  400. };
  401. hdmi_vdd_reg: ldo7 {
  402. regulator-name = "vdd_ldo7,avdd_hdmi";
  403. regulator-min-microvolt = <3300000>;
  404. regulator-max-microvolt = <3300000>;
  405. };
  406. hdmi_pll_reg: ldo8 {
  407. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  408. regulator-min-microvolt = <1800000>;
  409. regulator-max-microvolt = <1800000>;
  410. };
  411. ldo9 {
  412. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  413. regulator-min-microvolt = <2850000>;
  414. regulator-max-microvolt = <2850000>;
  415. regulator-always-on;
  416. };
  417. ldo_rtc {
  418. regulator-name = "vdd_rtc_out,vdd_cell";
  419. regulator-min-microvolt = <3300000>;
  420. regulator-max-microvolt = <3300000>;
  421. regulator-always-on;
  422. };
  423. };
  424. };
  425. temperature-sensor@4c {
  426. compatible = "adi,adt7461";
  427. reg = <0x4c>;
  428. };
  429. };
  430. kbc@7000e200 {
  431. status = "okay";
  432. nvidia,debounce-delay-ms = <2>;
  433. nvidia,repeat-delay-ms = <160>;
  434. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  435. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  436. linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
  437. MATRIX_KEY(0x00, 0x03, KEY_S)
  438. MATRIX_KEY(0x00, 0x04, KEY_A)
  439. MATRIX_KEY(0x00, 0x05, KEY_Z)
  440. MATRIX_KEY(0x00, 0x07, KEY_FN)
  441. MATRIX_KEY(0x01, 0x07, KEY_MENU)
  442. MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
  443. MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
  444. MATRIX_KEY(0x03, 0x00, KEY_5)
  445. MATRIX_KEY(0x03, 0x01, KEY_4)
  446. MATRIX_KEY(0x03, 0x02, KEY_R)
  447. MATRIX_KEY(0x03, 0x03, KEY_E)
  448. MATRIX_KEY(0x03, 0x04, KEY_F)
  449. MATRIX_KEY(0x03, 0x05, KEY_D)
  450. MATRIX_KEY(0x03, 0x06, KEY_X)
  451. MATRIX_KEY(0x04, 0x00, KEY_7)
  452. MATRIX_KEY(0x04, 0x01, KEY_6)
  453. MATRIX_KEY(0x04, 0x02, KEY_T)
  454. MATRIX_KEY(0x04, 0x03, KEY_H)
  455. MATRIX_KEY(0x04, 0x04, KEY_G)
  456. MATRIX_KEY(0x04, 0x05, KEY_V)
  457. MATRIX_KEY(0x04, 0x06, KEY_C)
  458. MATRIX_KEY(0x04, 0x07, KEY_SPACE)
  459. MATRIX_KEY(0x05, 0x00, KEY_9)
  460. MATRIX_KEY(0x05, 0x01, KEY_8)
  461. MATRIX_KEY(0x05, 0x02, KEY_U)
  462. MATRIX_KEY(0x05, 0x03, KEY_Y)
  463. MATRIX_KEY(0x05, 0x04, KEY_J)
  464. MATRIX_KEY(0x05, 0x05, KEY_N)
  465. MATRIX_KEY(0x05, 0x06, KEY_B)
  466. MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
  467. MATRIX_KEY(0x06, 0x00, KEY_MINUS)
  468. MATRIX_KEY(0x06, 0x01, KEY_0)
  469. MATRIX_KEY(0x06, 0x02, KEY_O)
  470. MATRIX_KEY(0x06, 0x03, KEY_I)
  471. MATRIX_KEY(0x06, 0x04, KEY_L)
  472. MATRIX_KEY(0x06, 0x05, KEY_K)
  473. MATRIX_KEY(0x06, 0x06, KEY_COMMA)
  474. MATRIX_KEY(0x06, 0x07, KEY_M)
  475. MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
  476. MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
  477. MATRIX_KEY(0x07, 0x03, KEY_ENTER)
  478. MATRIX_KEY(0x07, 0x07, KEY_MENU)
  479. MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
  480. MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
  481. MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
  482. MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
  483. MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
  484. MATRIX_KEY(0x0B, 0x01, KEY_P)
  485. MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
  486. MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
  487. MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
  488. MATRIX_KEY(0x0B, 0x05, KEY_DOT)
  489. MATRIX_KEY(0x0C, 0x00, KEY_F10)
  490. MATRIX_KEY(0x0C, 0x01, KEY_F9)
  491. MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
  492. MATRIX_KEY(0x0C, 0x03, KEY_3)
  493. MATRIX_KEY(0x0C, 0x04, KEY_2)
  494. MATRIX_KEY(0x0C, 0x05, KEY_UP)
  495. MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
  496. MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
  497. MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
  498. MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
  499. MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
  500. MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
  501. MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
  502. MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
  503. MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
  504. MATRIX_KEY(0x0E, 0x00, KEY_F11)
  505. MATRIX_KEY(0x0E, 0x01, KEY_F12)
  506. MATRIX_KEY(0x0E, 0x02, KEY_F8)
  507. MATRIX_KEY(0x0E, 0x03, KEY_Q)
  508. MATRIX_KEY(0x0E, 0x04, KEY_F4)
  509. MATRIX_KEY(0x0E, 0x05, KEY_F3)
  510. MATRIX_KEY(0x0E, 0x06, KEY_1)
  511. MATRIX_KEY(0x0E, 0x07, KEY_F7)
  512. MATRIX_KEY(0x0F, 0x00, KEY_ESC)
  513. MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
  514. MATRIX_KEY(0x0F, 0x02, KEY_F5)
  515. MATRIX_KEY(0x0F, 0x03, KEY_TAB)
  516. MATRIX_KEY(0x0F, 0x04, KEY_F1)
  517. MATRIX_KEY(0x0F, 0x05, KEY_F2)
  518. MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
  519. MATRIX_KEY(0x0F, 0x07, KEY_F6)
  520. MATRIX_KEY(0x14, 0x00, KEY_KP7)
  521. MATRIX_KEY(0x15, 0x00, KEY_KP9)
  522. MATRIX_KEY(0x15, 0x01, KEY_KP8)
  523. MATRIX_KEY(0x15, 0x02, KEY_KP4)
  524. MATRIX_KEY(0x15, 0x04, KEY_KP1)
  525. MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
  526. MATRIX_KEY(0x16, 0x02, KEY_KP6)
  527. MATRIX_KEY(0x16, 0x03, KEY_KP5)
  528. MATRIX_KEY(0x16, 0x04, KEY_KP3)
  529. MATRIX_KEY(0x16, 0x05, KEY_KP2)
  530. MATRIX_KEY(0x16, 0x07, KEY_KP0)
  531. MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
  532. MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
  533. MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
  534. MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
  535. MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
  536. MATRIX_KEY(0x1D, 0x03, KEY_HOME)
  537. MATRIX_KEY(0x1D, 0x04, KEY_END)
  538. MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
  539. MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
  540. MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
  541. MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
  542. MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
  543. MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
  544. MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
  545. };
  546. pmc@7000e400 {
  547. nvidia,invert-interrupt;
  548. nvidia,suspend-mode = <1>;
  549. nvidia,cpu-pwr-good-time = <5000>;
  550. nvidia,cpu-pwr-off-time = <5000>;
  551. nvidia,core-pwr-good-time = <3845 3845>;
  552. nvidia,core-pwr-off-time = <3875>;
  553. nvidia,sys-clock-req-active-high;
  554. };
  555. pcie-controller@80003000 {
  556. status = "okay";
  557. avdd-pex-supply = <&pci_vdd_reg>;
  558. vdd-pex-supply = <&pci_vdd_reg>;
  559. avdd-pex-pll-supply = <&pci_vdd_reg>;
  560. avdd-plle-supply = <&pci_vdd_reg>;
  561. vddio-pex-clk-supply = <&pci_clk_reg>;
  562. pci@1,0 {
  563. status = "okay";
  564. };
  565. pci@2,0 {
  566. status = "okay";
  567. };
  568. };
  569. usb@c5000000 {
  570. status = "okay";
  571. };
  572. usb-phy@c5000000 {
  573. status = "okay";
  574. };
  575. usb@c5004000 {
  576. status = "okay";
  577. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  578. GPIO_ACTIVE_LOW>;
  579. };
  580. usb-phy@c5004000 {
  581. status = "okay";
  582. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  583. GPIO_ACTIVE_LOW>;
  584. };
  585. usb@c5008000 {
  586. status = "okay";
  587. };
  588. usb-phy@c5008000 {
  589. status = "okay";
  590. };
  591. sdhci@c8000200 {
  592. status = "okay";
  593. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  594. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  595. power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  596. bus-width = <4>;
  597. };
  598. sdhci@c8000600 {
  599. status = "okay";
  600. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  601. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  602. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  603. bus-width = <8>;
  604. };
  605. backlight: backlight {
  606. compatible = "pwm-backlight";
  607. enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
  608. power-supply = <&vdd_bl_reg>;
  609. pwms = <&pwm 0 5000000>;
  610. brightness-levels = <0 4 8 16 32 64 128 255>;
  611. default-brightness-level = <6>;
  612. };
  613. clocks {
  614. compatible = "simple-bus";
  615. #address-cells = <1>;
  616. #size-cells = <0>;
  617. clk32k_in: clock@0 {
  618. compatible = "fixed-clock";
  619. reg=<0>;
  620. #clock-cells = <0>;
  621. clock-frequency = <32768>;
  622. };
  623. };
  624. gpio-keys {
  625. compatible = "gpio-keys";
  626. power {
  627. label = "Power";
  628. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  629. linux,code = <KEY_POWER>;
  630. gpio-key,wakeup;
  631. };
  632. };
  633. panel: panel {
  634. compatible = "auo,b101aw03", "simple-panel";
  635. power-supply = <&vdd_pnl_reg>;
  636. enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
  637. backlight = <&backlight>;
  638. };
  639. regulators {
  640. compatible = "simple-bus";
  641. #address-cells = <1>;
  642. #size-cells = <0>;
  643. vdd_5v0_reg: regulator@0 {
  644. compatible = "regulator-fixed";
  645. reg = <0>;
  646. regulator-name = "vdd_5v0";
  647. regulator-min-microvolt = <5000000>;
  648. regulator-max-microvolt = <5000000>;
  649. regulator-always-on;
  650. };
  651. regulator@1 {
  652. compatible = "regulator-fixed";
  653. reg = <1>;
  654. regulator-name = "vdd_1v5";
  655. regulator-min-microvolt = <1500000>;
  656. regulator-max-microvolt = <1500000>;
  657. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  658. };
  659. regulator@2 {
  660. compatible = "regulator-fixed";
  661. reg = <2>;
  662. regulator-name = "vdd_1v2";
  663. regulator-min-microvolt = <1200000>;
  664. regulator-max-microvolt = <1200000>;
  665. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  666. enable-active-high;
  667. };
  668. pci_vdd_reg: regulator@3 {
  669. compatible = "regulator-fixed";
  670. reg = <3>;
  671. regulator-name = "vdd_1v05";
  672. regulator-min-microvolt = <1050000>;
  673. regulator-max-microvolt = <1050000>;
  674. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  675. enable-active-high;
  676. };
  677. vdd_pnl_reg: regulator@4 {
  678. compatible = "regulator-fixed";
  679. reg = <4>;
  680. regulator-name = "vdd_pnl";
  681. regulator-min-microvolt = <2800000>;
  682. regulator-max-microvolt = <2800000>;
  683. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  684. enable-active-high;
  685. };
  686. vdd_bl_reg: regulator@5 {
  687. compatible = "regulator-fixed";
  688. reg = <5>;
  689. regulator-name = "vdd_bl";
  690. regulator-min-microvolt = <2800000>;
  691. regulator-max-microvolt = <2800000>;
  692. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  693. enable-active-high;
  694. };
  695. vdd_5v0_hdmi: regulator@6 {
  696. compatible = "regulator-fixed";
  697. reg = <6>;
  698. regulator-name = "VDDIO_HDMI";
  699. regulator-min-microvolt = <5000000>;
  700. regulator-max-microvolt = <5000000>;
  701. gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
  702. enable-active-high;
  703. vin-supply = <&vdd_5v0_reg>;
  704. };
  705. };
  706. sound {
  707. compatible = "nvidia,tegra-audio-wm8903-harmony",
  708. "nvidia,tegra-audio-wm8903";
  709. nvidia,model = "NVIDIA Tegra Harmony";
  710. nvidia,audio-routing =
  711. "Headphone Jack", "HPOUTR",
  712. "Headphone Jack", "HPOUTL",
  713. "Int Spk", "ROP",
  714. "Int Spk", "RON",
  715. "Int Spk", "LOP",
  716. "Int Spk", "LON",
  717. "Mic Jack", "MICBIAS",
  718. "IN1L", "Mic Jack";
  719. nvidia,i2s-controller = <&tegra_i2s1>;
  720. nvidia,audio-codec = <&wm8903>;
  721. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  722. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  723. GPIO_ACTIVE_HIGH>;
  724. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  725. GPIO_ACTIVE_HIGH>;
  726. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  727. GPIO_ACTIVE_HIGH>;
  728. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  729. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  730. <&tegra_car TEGRA20_CLK_CDEV1>;
  731. clock-names = "pll_a", "pll_a_out0", "mclk";
  732. };
  733. };