tegra124-nyan-big.dts 41 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379
  1. /dts-v1/;
  2. #include "tegra124-nyan.dtsi"
  3. / {
  4. model = "Acer Chromebook 13 CB5-311";
  5. compatible = "google,nyan-big", "nvidia,tegra124";
  6. aliases {
  7. console = &uarta;
  8. stdout-path = &uarta;
  9. i2c0 = "/i2c@7000d000";
  10. i2c1 = "/i2c@7000c000";
  11. i2c2 = "/i2c@7000c400";
  12. i2c3 = "/i2c@7000c500";
  13. i2c4 = "/i2c@7000c700";
  14. i2c5 = "/i2c@7000d100";
  15. rtc0 = "/i2c@7000d000/pmic@40";
  16. rtc1 = "/rtc@7000e000";
  17. mmc0 = "/sdhci@700b0600";
  18. mmc1 = "/sdhci@700b0400";
  19. spi0 = "/spi@7000d400";
  20. spi1 = "/spi@7000da00";
  21. usb0 = "/usb@7d000000";
  22. usb1 = "/usb@7d008000";
  23. usb2 = "/usb@7d004000";
  24. };
  25. host1x@50000000 {
  26. dc@54200000 {
  27. display-timings {
  28. timing@0 {
  29. clock-frequency = <69500000>;
  30. hactive = <1366>;
  31. vactive = <768>;
  32. hsync-len = <32>;
  33. hfront-porch = <48>;
  34. hback-porch = <20>;
  35. vfront-porch = <3>;
  36. vback-porch = <13>;
  37. vsync-len = <6>;
  38. };
  39. };
  40. };
  41. dc@54240000 {
  42. status = "disabled";
  43. };
  44. };
  45. panel: panel {
  46. compatible = "auo,b133xtn01";
  47. backlight = <&backlight>;
  48. ddc-i2c-bus = <&dpaux>;
  49. };
  50. sdhci@700b0400 { /* SD Card on this bus */
  51. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
  52. };
  53. sound {
  54. compatible = "nvidia,tegra-audio-max98090-nyan-big",
  55. "nvidia,tegra-audio-max98090-nyan",
  56. "nvidia,tegra-audio-max98090";
  57. nvidia,model = "GoogleNyanBig";
  58. };
  59. pinmux@70000868 {
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&pinmux_default>;
  62. pinmux_default: common {
  63. clk_32k_out_pa0 {
  64. nvidia,pins = "clk_32k_out_pa0";
  65. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  66. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  67. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  68. };
  69. uart3_cts_n_pa1 {
  70. nvidia,pins = "uart3_cts_n_pa1";
  71. nvidia,function = "gmi";
  72. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  73. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  74. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  75. };
  76. dap2_fs_pa2 {
  77. nvidia,pins = "dap2_fs_pa2";
  78. nvidia,function = "i2s1";
  79. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  80. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  81. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  82. };
  83. dap2_sclk_pa3 {
  84. nvidia,pins = "dap2_sclk_pa3";
  85. nvidia,function = "i2s1";
  86. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  87. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  88. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  89. };
  90. dap2_din_pa4 {
  91. nvidia,pins = "dap2_din_pa4";
  92. nvidia,function = "i2s1";
  93. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  94. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  96. };
  97. dap2_dout_pa5 {
  98. nvidia,pins = "dap2_dout_pa5";
  99. nvidia,function = "i2s1";
  100. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  101. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  102. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  103. };
  104. sdmmc3_clk_pa6 {
  105. nvidia,pins = "sdmmc3_clk_pa6";
  106. nvidia,function = "sdmmc3";
  107. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  108. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  109. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  110. };
  111. sdmmc3_cmd_pa7 {
  112. nvidia,pins = "sdmmc3_cmd_pa7";
  113. nvidia,function = "sdmmc3";
  114. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  115. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  116. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  117. };
  118. pb0 {
  119. nvidia,pins = "pb0";
  120. nvidia,function = "rsvd2";
  121. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  124. };
  125. pb1 {
  126. nvidia,pins = "pb1";
  127. nvidia,function = "rsvd2";
  128. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  129. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. };
  132. sdmmc3_dat3_pb4 {
  133. nvidia,pins = "sdmmc3_dat3_pb4";
  134. nvidia,function = "sdmmc3";
  135. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  136. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  138. };
  139. sdmmc3_dat2_pb5 {
  140. nvidia,pins = "sdmmc3_dat2_pb5";
  141. nvidia,function = "sdmmc3";
  142. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  143. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  144. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  145. };
  146. sdmmc3_dat1_pb6 {
  147. nvidia,pins = "sdmmc3_dat1_pb6";
  148. nvidia,function = "sdmmc3";
  149. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  150. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  151. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  152. };
  153. sdmmc3_dat0_pb7 {
  154. nvidia,pins = "sdmmc3_dat0_pb7";
  155. nvidia,function = "sdmmc3";
  156. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  157. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  158. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  159. };
  160. uart3_rts_n_pc0 {
  161. nvidia,pins = "uart3_rts_n_pc0";
  162. nvidia,function = "gmi";
  163. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  164. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  165. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  166. };
  167. uart2_txd_pc2 {
  168. nvidia,pins = "uart2_txd_pc2";
  169. nvidia,function = "irda";
  170. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  171. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  172. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  173. };
  174. uart2_rxd_pc3 {
  175. nvidia,pins = "uart2_rxd_pc3";
  176. nvidia,function = "irda";
  177. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  178. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  180. };
  181. gen1_i2c_scl_pc4 {
  182. nvidia,pins = "gen1_i2c_scl_pc4";
  183. nvidia,function = "i2c1";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  187. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  188. };
  189. gen1_i2c_sda_pc5 {
  190. nvidia,pins = "gen1_i2c_sda_pc5";
  191. nvidia,function = "i2c1";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  195. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  196. };
  197. pc7 {
  198. nvidia,pins = "pc7";
  199. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  200. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  202. };
  203. pg0 {
  204. nvidia,pins = "pg0";
  205. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  206. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  207. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  208. };
  209. pg1 {
  210. nvidia,pins = "pg1";
  211. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  212. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  213. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  214. };
  215. pg2 {
  216. nvidia,pins = "pg2";
  217. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  219. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  220. };
  221. pg3 {
  222. nvidia,pins = "pg3";
  223. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  224. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  225. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  226. };
  227. pg4 {
  228. nvidia,pins = "pg4";
  229. nvidia,function = "spi4";
  230. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  233. };
  234. pg5 {
  235. nvidia,pins = "pg5";
  236. nvidia,function = "spi4";
  237. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  238. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  239. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  240. };
  241. pg6 {
  242. nvidia,pins = "pg6";
  243. nvidia,function = "spi4";
  244. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  246. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  247. };
  248. pg7 {
  249. nvidia,pins = "pg7";
  250. nvidia,function = "spi4";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  254. };
  255. ph0 {
  256. nvidia,pins = "ph0";
  257. nvidia,function = "gmi";
  258. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  259. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  260. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  261. };
  262. ph1 {
  263. nvidia,pins = "ph1";
  264. nvidia,function = "pwm1";
  265. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  268. };
  269. ph2 {
  270. nvidia,pins = "ph2";
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  274. };
  275. ph3 {
  276. nvidia,pins = "ph3";
  277. nvidia,function = "gmi";
  278. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  279. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  280. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  281. };
  282. ph4 {
  283. nvidia,pins = "ph4";
  284. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  285. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  286. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  287. };
  288. ph5 {
  289. nvidia,pins = "ph5";
  290. nvidia,function = "rsvd2";
  291. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  292. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  293. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  294. };
  295. ph6 {
  296. nvidia,pins = "ph6";
  297. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  298. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  299. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  300. };
  301. ph7 {
  302. nvidia,pins = "ph7";
  303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  306. };
  307. pi0 {
  308. nvidia,pins = "pi0";
  309. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  310. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  311. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  312. };
  313. pi1 {
  314. nvidia,pins = "pi1";
  315. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  316. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  317. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  318. };
  319. pi2 {
  320. nvidia,pins = "pi2";
  321. nvidia,function = "rsvd4";
  322. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  323. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  324. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  325. };
  326. pi3 {
  327. nvidia,pins = "pi3";
  328. nvidia,function = "spi4";
  329. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  330. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  331. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  332. };
  333. pi4 {
  334. nvidia,pins = "pi4";
  335. nvidia,function = "gmi";
  336. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  337. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  338. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  339. };
  340. pi5 {
  341. nvidia,pins = "pi5";
  342. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  343. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  344. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  345. };
  346. pi6 {
  347. nvidia,pins = "pi6";
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  351. };
  352. pi7 {
  353. nvidia,pins = "pi7";
  354. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  355. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  356. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  357. };
  358. pj0 {
  359. nvidia,pins = "pj0";
  360. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  361. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  362. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  363. };
  364. pj2 {
  365. nvidia,pins = "pj2";
  366. nvidia,function = "rsvd1";
  367. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  368. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  369. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  370. };
  371. uart2_cts_n_pj5 {
  372. nvidia,pins = "uart2_cts_n_pj5";
  373. nvidia,function = "gmi";
  374. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  375. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  376. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  377. };
  378. uart2_rts_n_pj6 {
  379. nvidia,pins = "uart2_rts_n_pj6";
  380. nvidia,function = "gmi";
  381. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  382. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  383. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  384. };
  385. pj7 {
  386. nvidia,pins = "pj7";
  387. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  388. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  389. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  390. };
  391. pk0 {
  392. nvidia,pins = "pk0";
  393. nvidia,function = "rsvd1";
  394. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  395. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  396. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  397. };
  398. pk1 {
  399. nvidia,pins = "pk1";
  400. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  403. };
  404. pk2 {
  405. nvidia,pins = "pk2";
  406. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  407. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  408. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  409. };
  410. pk3 {
  411. nvidia,pins = "pk3";
  412. nvidia,function = "gmi";
  413. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  414. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  415. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  416. };
  417. pk4 {
  418. nvidia,pins = "pk4";
  419. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  420. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  421. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  422. };
  423. spdif_out_pk5 {
  424. nvidia,pins = "spdif_out_pk5";
  425. nvidia,function = "rsvd2";
  426. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  427. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  428. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  429. };
  430. spdif_in_pk6 {
  431. nvidia,pins = "spdif_in_pk6";
  432. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  433. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  434. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  435. };
  436. pk7 {
  437. nvidia,pins = "pk7";
  438. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  439. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  440. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  441. };
  442. dap1_fs_pn0 {
  443. nvidia,pins = "dap1_fs_pn0";
  444. nvidia,function = "rsvd4";
  445. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  446. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  447. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  448. };
  449. dap1_din_pn1 {
  450. nvidia,pins = "dap1_din_pn1";
  451. nvidia,function = "rsvd4";
  452. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  453. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  454. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  455. };
  456. dap1_dout_pn2 {
  457. nvidia,pins = "dap1_dout_pn2";
  458. nvidia,function = "i2s0";
  459. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  460. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  461. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  462. };
  463. dap1_sclk_pn3 {
  464. nvidia,pins = "dap1_sclk_pn3";
  465. nvidia,function = "rsvd4";
  466. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  467. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  468. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  469. };
  470. usb_vbus_en0_pn4 {
  471. nvidia,pins = "usb_vbus_en0_pn4";
  472. nvidia,function = "usb";
  473. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  474. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  475. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  476. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  477. };
  478. usb_vbus_en1_pn5 {
  479. nvidia,pins = "usb_vbus_en1_pn5";
  480. nvidia,function = "usb";
  481. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  482. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  483. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  484. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  485. };
  486. hdmi_int_pn7 {
  487. nvidia,pins = "hdmi_int_pn7";
  488. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  489. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  490. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  491. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  492. };
  493. ulpi_data7_po0 {
  494. nvidia,pins = "ulpi_data7_po0";
  495. nvidia,function = "ulpi";
  496. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  497. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  498. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  499. };
  500. ulpi_data0_po1 {
  501. nvidia,pins = "ulpi_data0_po1";
  502. nvidia,function = "ulpi";
  503. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  504. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  506. };
  507. ulpi_data1_po2 {
  508. nvidia,pins = "ulpi_data1_po2";
  509. nvidia,function = "ulpi";
  510. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  511. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  512. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  513. };
  514. ulpi_data2_po3 {
  515. nvidia,pins = "ulpi_data2_po3";
  516. nvidia,function = "ulpi";
  517. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  518. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  519. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  520. };
  521. ulpi_data3_po4 {
  522. nvidia,pins = "ulpi_data3_po4";
  523. nvidia,function = "ulpi";
  524. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  525. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  526. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  527. };
  528. ulpi_data4_po5 {
  529. nvidia,pins = "ulpi_data4_po5";
  530. nvidia,function = "ulpi";
  531. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  532. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  533. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  534. };
  535. ulpi_data5_po6 {
  536. nvidia,pins = "ulpi_data5_po6";
  537. nvidia,function = "ulpi";
  538. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  539. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  540. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  541. };
  542. ulpi_data6_po7 {
  543. nvidia,pins = "ulpi_data6_po7";
  544. nvidia,function = "ulpi";
  545. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  546. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  547. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  548. };
  549. dap3_fs_pp0 {
  550. nvidia,pins = "dap3_fs_pp0";
  551. nvidia,function = "i2s2";
  552. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  553. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  555. };
  556. dap3_din_pp1 {
  557. nvidia,pins = "dap3_din_pp1";
  558. nvidia,function = "i2s2";
  559. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  560. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  562. };
  563. dap3_dout_pp2 {
  564. nvidia,pins = "dap3_dout_pp2";
  565. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  566. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  567. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  568. };
  569. dap3_sclk_pp3 {
  570. nvidia,pins = "dap3_sclk_pp3";
  571. nvidia,function = "rsvd3";
  572. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  573. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  574. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  575. };
  576. dap4_fs_pp4 {
  577. nvidia,pins = "dap4_fs_pp4";
  578. nvidia,function = "rsvd4";
  579. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  580. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  581. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  582. };
  583. dap4_din_pp5 {
  584. nvidia,pins = "dap4_din_pp5";
  585. nvidia,function = "rsvd3";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  589. };
  590. dap4_dout_pp6 {
  591. nvidia,pins = "dap4_dout_pp6";
  592. nvidia,function = "rsvd4";
  593. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  594. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  595. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  596. };
  597. dap4_sclk_pp7 {
  598. nvidia,pins = "dap4_sclk_pp7";
  599. nvidia,function = "rsvd3";
  600. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  601. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  602. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  603. };
  604. kb_col0_pq0 {
  605. nvidia,pins = "kb_col0_pq0";
  606. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  607. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  608. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  609. };
  610. kb_col1_pq1 {
  611. nvidia,pins = "kb_col1_pq1";
  612. nvidia,function = "rsvd2";
  613. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  614. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  615. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  616. };
  617. kb_col2_pq2 {
  618. nvidia,pins = "kb_col2_pq2";
  619. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  620. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  621. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  622. };
  623. kb_col3_pq3 {
  624. nvidia,pins = "kb_col3_pq3";
  625. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  626. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  627. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  628. };
  629. kb_col4_pq4 {
  630. nvidia,pins = "kb_col4_pq4";
  631. nvidia,function = "sdmmc3";
  632. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  633. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  634. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  635. };
  636. kb_col5_pq5 {
  637. nvidia,pins = "kb_col5_pq5";
  638. nvidia,function = "rsvd2";
  639. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  640. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  641. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  642. };
  643. kb_col6_pq6 {
  644. nvidia,pins = "kb_col6_pq6";
  645. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  646. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  647. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  648. };
  649. kb_col7_pq7 {
  650. nvidia,pins = "kb_col7_pq7";
  651. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  652. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  654. };
  655. kb_row0_pr0 {
  656. nvidia,pins = "kb_row0_pr0";
  657. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  658. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  659. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  660. };
  661. kb_row1_pr1 {
  662. nvidia,pins = "kb_row1_pr1";
  663. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  664. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  665. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  666. };
  667. kb_row2_pr2 {
  668. nvidia,pins = "kb_row2_pr2";
  669. nvidia,function = "rsvd2";
  670. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  671. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  672. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  673. };
  674. kb_row3_pr3 {
  675. nvidia,pins = "kb_row3_pr3";
  676. nvidia,function = "kbc";
  677. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  678. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  679. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  680. };
  681. kb_row4_pr4 {
  682. nvidia,pins = "kb_row4_pr4";
  683. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  684. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  685. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  686. };
  687. kb_row5_pr5 {
  688. nvidia,pins = "kb_row5_pr5";
  689. nvidia,function = "rsvd3";
  690. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  691. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  692. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  693. };
  694. kb_row6_pr6 {
  695. nvidia,pins = "kb_row6_pr6";
  696. nvidia,function = "kbc";
  697. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  698. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  699. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  700. };
  701. kb_row7_pr7 {
  702. nvidia,pins = "kb_row7_pr7";
  703. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  704. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  705. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  706. };
  707. kb_row8_ps0 {
  708. nvidia,pins = "kb_row8_ps0";
  709. nvidia,function = "rsvd2";
  710. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  711. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  712. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  713. };
  714. kb_row9_ps1 {
  715. nvidia,pins = "kb_row9_ps1";
  716. nvidia,function = "uarta";
  717. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  718. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  719. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  720. };
  721. kb_row10_ps2 {
  722. nvidia,pins = "kb_row10_ps2";
  723. nvidia,function = "uarta";
  724. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  725. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  726. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  727. };
  728. kb_row11_ps3 {
  729. nvidia,pins = "kb_row11_ps3";
  730. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  731. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  732. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  733. };
  734. kb_row12_ps4 {
  735. nvidia,pins = "kb_row12_ps4";
  736. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  737. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  738. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  739. };
  740. kb_row13_ps5 {
  741. nvidia,pins = "kb_row13_ps5";
  742. nvidia,function = "rsvd2";
  743. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  744. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  745. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  746. };
  747. kb_row14_ps6 {
  748. nvidia,pins = "kb_row14_ps6";
  749. nvidia,function = "rsvd2";
  750. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  751. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  752. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  753. };
  754. kb_row15_ps7 {
  755. nvidia,pins = "kb_row15_ps7";
  756. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  757. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  758. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  759. };
  760. kb_row16_pt0 {
  761. nvidia,pins = "kb_row16_pt0";
  762. nvidia,function = "rsvd2";
  763. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  764. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  765. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  766. };
  767. kb_row17_pt1 {
  768. nvidia,pins = "kb_row17_pt1";
  769. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  770. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  771. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  772. };
  773. gen2_i2c_scl_pt5 {
  774. nvidia,pins = "gen2_i2c_scl_pt5";
  775. nvidia,function = "i2c2";
  776. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  777. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  778. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  779. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  780. };
  781. gen2_i2c_sda_pt6 {
  782. nvidia,pins = "gen2_i2c_sda_pt6";
  783. nvidia,function = "i2c2";
  784. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  785. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  786. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  787. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  788. };
  789. sdmmc4_cmd_pt7 {
  790. nvidia,pins = "sdmmc4_cmd_pt7";
  791. nvidia,function = "sdmmc4";
  792. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  793. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  794. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  795. };
  796. pu0 {
  797. nvidia,pins = "pu0";
  798. nvidia,function = "rsvd4";
  799. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  800. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  801. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  802. };
  803. pu1 {
  804. nvidia,pins = "pu1";
  805. nvidia,function = "rsvd1";
  806. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  807. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  808. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  809. };
  810. pu2 {
  811. nvidia,pins = "pu2";
  812. nvidia,function = "rsvd1";
  813. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  814. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  815. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  816. };
  817. pu3 {
  818. nvidia,pins = "pu3";
  819. nvidia,function = "gmi";
  820. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  821. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  822. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  823. };
  824. pu4 {
  825. nvidia,pins = "pu4";
  826. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  827. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  828. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  829. };
  830. pu5 {
  831. nvidia,pins = "pu5";
  832. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  833. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  834. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  835. };
  836. pu6 {
  837. nvidia,pins = "pu6";
  838. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  839. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  840. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  841. };
  842. pv0 {
  843. nvidia,pins = "pv0";
  844. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  845. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  846. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  847. };
  848. pv1 {
  849. nvidia,pins = "pv1";
  850. nvidia,function = "rsvd1";
  851. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  852. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  853. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  854. };
  855. sdmmc3_cd_n_pv2 {
  856. nvidia,pins = "sdmmc3_cd_n_pv2";
  857. nvidia,function = "sdmmc3";
  858. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  859. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  860. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  861. };
  862. sdmmc1_wp_n_pv3 {
  863. nvidia,pins = "sdmmc1_wp_n_pv3";
  864. nvidia,function = "sdmmc1";
  865. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  866. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  868. };
  869. ddc_scl_pv4 {
  870. nvidia,pins = "ddc_scl_pv4";
  871. nvidia,function = "i2c4";
  872. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  873. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  874. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  875. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  876. };
  877. ddc_sda_pv5 {
  878. nvidia,pins = "ddc_sda_pv5";
  879. nvidia,function = "i2c4";
  880. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  881. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  883. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  884. };
  885. gpio_w2_aud_pw2 {
  886. nvidia,pins = "gpio_w2_aud_pw2";
  887. nvidia,function = "rsvd2";
  888. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  889. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  890. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  891. };
  892. gpio_w3_aud_pw3 {
  893. nvidia,pins = "gpio_w3_aud_pw3";
  894. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  895. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  897. };
  898. dap_mclk1_pw4 {
  899. nvidia,pins = "dap_mclk1_pw4";
  900. nvidia,function = "extperiph1";
  901. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  904. };
  905. clk2_out_pw5 {
  906. nvidia,pins = "clk2_out_pw5";
  907. nvidia,function = "rsvd2";
  908. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  909. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  910. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  911. };
  912. uart3_txd_pw6 {
  913. nvidia,pins = "uart3_txd_pw6";
  914. nvidia,function = "rsvd2";
  915. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  916. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  917. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  918. };
  919. uart3_rxd_pw7 {
  920. nvidia,pins = "uart3_rxd_pw7";
  921. nvidia,function = "rsvd2";
  922. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  923. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  925. };
  926. dvfs_pwm_px0 {
  927. nvidia,pins = "dvfs_pwm_px0";
  928. nvidia,function = "cldvfs";
  929. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  930. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  931. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  932. };
  933. gpio_x1_aud_px1 {
  934. nvidia,pins = "gpio_x1_aud_px1";
  935. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  936. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  937. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  938. };
  939. dvfs_clk_px2 {
  940. nvidia,pins = "dvfs_clk_px2";
  941. nvidia,function = "cldvfs";
  942. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  943. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  944. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  945. };
  946. gpio_x3_aud_px3 {
  947. nvidia,pins = "gpio_x3_aud_px3";
  948. nvidia,function = "rsvd4";
  949. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  950. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  951. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  952. };
  953. gpio_x4_aud_px4 {
  954. nvidia,pins = "gpio_x4_aud_px4";
  955. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  956. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  957. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  958. };
  959. gpio_x5_aud_px5 {
  960. nvidia,pins = "gpio_x5_aud_px5";
  961. nvidia,function = "rsvd4";
  962. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  963. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  964. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  965. };
  966. gpio_x6_aud_px6 {
  967. nvidia,pins = "gpio_x6_aud_px6";
  968. nvidia,function = "gmi";
  969. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  970. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  971. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  972. };
  973. gpio_x7_aud_px7 {
  974. nvidia,pins = "gpio_x7_aud_px7";
  975. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  976. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  977. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  978. };
  979. ulpi_clk_py0 {
  980. nvidia,pins = "ulpi_clk_py0";
  981. nvidia,function = "spi1";
  982. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  983. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  984. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  985. };
  986. ulpi_dir_py1 {
  987. nvidia,pins = "ulpi_dir_py1";
  988. nvidia,function = "spi1";
  989. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  990. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  991. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  992. };
  993. ulpi_nxt_py2 {
  994. nvidia,pins = "ulpi_nxt_py2";
  995. nvidia,function = "spi1";
  996. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  997. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  998. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  999. };
  1000. ulpi_stp_py3 {
  1001. nvidia,pins = "ulpi_stp_py3";
  1002. nvidia,function = "spi1";
  1003. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1004. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1005. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1006. };
  1007. sdmmc1_dat3_py4 {
  1008. nvidia,pins = "sdmmc1_dat3_py4";
  1009. nvidia,function = "sdmmc1";
  1010. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1011. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1012. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1013. };
  1014. sdmmc1_dat2_py5 {
  1015. nvidia,pins = "sdmmc1_dat2_py5";
  1016. nvidia,function = "sdmmc1";
  1017. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1018. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1019. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1020. };
  1021. sdmmc1_dat1_py6 {
  1022. nvidia,pins = "sdmmc1_dat1_py6";
  1023. nvidia,function = "sdmmc1";
  1024. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1025. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1026. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1027. };
  1028. sdmmc1_dat0_py7 {
  1029. nvidia,pins = "sdmmc1_dat0_py7";
  1030. nvidia,function = "sdmmc1";
  1031. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1032. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1033. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1034. };
  1035. sdmmc1_clk_pz0 {
  1036. nvidia,pins = "sdmmc1_clk_pz0";
  1037. nvidia,function = "sdmmc1";
  1038. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1039. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1040. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1041. };
  1042. sdmmc1_cmd_pz1 {
  1043. nvidia,pins = "sdmmc1_cmd_pz1";
  1044. nvidia,function = "sdmmc1";
  1045. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1046. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1047. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1048. };
  1049. pwr_i2c_scl_pz6 {
  1050. nvidia,pins = "pwr_i2c_scl_pz6";
  1051. nvidia,function = "i2cpwr";
  1052. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1053. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1054. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1055. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1056. };
  1057. pwr_i2c_sda_pz7 {
  1058. nvidia,pins = "pwr_i2c_sda_pz7";
  1059. nvidia,function = "i2cpwr";
  1060. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1061. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1062. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1063. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1064. };
  1065. sdmmc4_dat0_paa0 {
  1066. nvidia,pins = "sdmmc4_dat0_paa0";
  1067. nvidia,function = "sdmmc4";
  1068. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1069. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1070. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1071. };
  1072. sdmmc4_dat1_paa1 {
  1073. nvidia,pins = "sdmmc4_dat1_paa1";
  1074. nvidia,function = "sdmmc4";
  1075. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1076. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1077. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1078. };
  1079. sdmmc4_dat2_paa2 {
  1080. nvidia,pins = "sdmmc4_dat2_paa2";
  1081. nvidia,function = "sdmmc4";
  1082. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1083. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1084. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1085. };
  1086. sdmmc4_dat3_paa3 {
  1087. nvidia,pins = "sdmmc4_dat3_paa3";
  1088. nvidia,function = "sdmmc4";
  1089. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1090. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1091. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1092. };
  1093. sdmmc4_dat4_paa4 {
  1094. nvidia,pins = "sdmmc4_dat4_paa4";
  1095. nvidia,function = "sdmmc4";
  1096. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1097. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1098. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1099. };
  1100. sdmmc4_dat5_paa5 {
  1101. nvidia,pins = "sdmmc4_dat5_paa5";
  1102. nvidia,function = "sdmmc4";
  1103. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1106. };
  1107. sdmmc4_dat6_paa6 {
  1108. nvidia,pins = "sdmmc4_dat6_paa6";
  1109. nvidia,function = "sdmmc4";
  1110. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1111. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1112. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1113. };
  1114. sdmmc4_dat7_paa7 {
  1115. nvidia,pins = "sdmmc4_dat7_paa7";
  1116. nvidia,function = "sdmmc4";
  1117. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1118. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1119. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1120. };
  1121. pbb0 {
  1122. nvidia,pins = "pbb0";
  1123. nvidia,function = "vgp6";
  1124. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1125. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1126. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1127. };
  1128. cam_i2c_scl_pbb1 {
  1129. nvidia,pins = "cam_i2c_scl_pbb1";
  1130. nvidia,function = "rsvd3";
  1131. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1132. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1133. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1134. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1135. };
  1136. cam_i2c_sda_pbb2 {
  1137. nvidia,pins = "cam_i2c_sda_pbb2";
  1138. nvidia,function = "rsvd3";
  1139. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1140. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1141. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1142. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1143. };
  1144. pbb3 {
  1145. nvidia,pins = "pbb3";
  1146. nvidia,function = "vgp3";
  1147. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1148. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1149. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1150. };
  1151. pbb4 {
  1152. nvidia,pins = "pbb4";
  1153. nvidia,function = "vgp4";
  1154. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1155. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1156. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1157. };
  1158. pbb5 {
  1159. nvidia,pins = "pbb5";
  1160. nvidia,function = "rsvd3";
  1161. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1162. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1163. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1164. };
  1165. pbb6 {
  1166. nvidia,pins = "pbb6";
  1167. nvidia,function = "rsvd2";
  1168. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1169. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1170. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1171. };
  1172. pbb7 {
  1173. nvidia,pins = "pbb7";
  1174. nvidia,function = "rsvd2";
  1175. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1176. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1177. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1178. };
  1179. cam_mclk_pcc0 {
  1180. nvidia,pins = "cam_mclk_pcc0";
  1181. nvidia,function = "vi";
  1182. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1183. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1184. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1185. };
  1186. pcc1 {
  1187. nvidia,pins = "pcc1";
  1188. nvidia,function = "rsvd2";
  1189. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1190. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1191. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1192. };
  1193. pcc2 {
  1194. nvidia,pins = "pcc2";
  1195. nvidia,function = "rsvd2";
  1196. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1197. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1198. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1199. };
  1200. sdmmc4_clk_pcc4 {
  1201. nvidia,pins = "sdmmc4_clk_pcc4";
  1202. nvidia,function = "sdmmc4";
  1203. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1205. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1206. };
  1207. clk2_req_pcc5 {
  1208. nvidia,pins = "clk2_req_pcc5";
  1209. nvidia,function = "rsvd2";
  1210. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1211. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1212. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1213. };
  1214. pex_l0_rst_n_pdd1 {
  1215. nvidia,pins = "pex_l0_rst_n_pdd1";
  1216. nvidia,function = "rsvd2";
  1217. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1218. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1220. };
  1221. pex_l0_clkreq_n_pdd2 {
  1222. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1223. nvidia,function = "rsvd2";
  1224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1227. };
  1228. pex_wake_n_pdd3 {
  1229. nvidia,pins = "pex_wake_n_pdd3";
  1230. nvidia,function = "rsvd2";
  1231. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1232. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1233. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1234. };
  1235. pex_l1_rst_n_pdd5 {
  1236. nvidia,pins = "pex_l1_rst_n_pdd5";
  1237. nvidia,function = "rsvd2";
  1238. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1239. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1240. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1241. };
  1242. pex_l1_clkreq_n_pdd6 {
  1243. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1244. nvidia,function = "rsvd2";
  1245. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1246. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1247. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1248. };
  1249. clk3_out_pee0 {
  1250. nvidia,pins = "clk3_out_pee0";
  1251. nvidia,function = "rsvd2";
  1252. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1253. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1254. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1255. };
  1256. clk3_req_pee1 {
  1257. nvidia,pins = "clk3_req_pee1";
  1258. nvidia,function = "rsvd2";
  1259. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1260. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1261. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1262. };
  1263. dap_mclk1_req_pee2 {
  1264. nvidia,pins = "dap_mclk1_req_pee2";
  1265. nvidia,function = "rsvd4";
  1266. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1267. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1268. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1269. };
  1270. hdmi_cec_pee3 {
  1271. nvidia,pins = "hdmi_cec_pee3";
  1272. nvidia,function = "cec";
  1273. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1274. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1275. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1276. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  1277. };
  1278. sdmmc3_clk_lb_out_pee4 {
  1279. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  1280. nvidia,function = "sdmmc3";
  1281. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1282. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1283. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1284. };
  1285. sdmmc3_clk_lb_in_pee5 {
  1286. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  1287. nvidia,function = "sdmmc3";
  1288. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1289. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1290. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1291. };
  1292. dp_hpd_pff0 {
  1293. nvidia,pins = "dp_hpd_pff0";
  1294. nvidia,function = "dp";
  1295. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1296. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1297. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1298. };
  1299. usb_vbus_en2_pff1 {
  1300. nvidia,pins = "usb_vbus_en2_pff1";
  1301. nvidia,function = "rsvd2";
  1302. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1303. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1304. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1305. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1306. };
  1307. pff2 {
  1308. nvidia,pins = "pff2";
  1309. nvidia,function = "rsvd2";
  1310. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1311. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1312. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1313. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1314. };
  1315. core_pwr_req {
  1316. nvidia,pins = "core_pwr_req";
  1317. nvidia,function = "pwron";
  1318. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1319. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1320. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1321. };
  1322. cpu_pwr_req {
  1323. nvidia,pins = "cpu_pwr_req";
  1324. nvidia,function = "cpu";
  1325. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1326. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1327. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1328. };
  1329. pwr_int_n {
  1330. nvidia,pins = "pwr_int_n";
  1331. nvidia,function = "pmi";
  1332. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1333. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1334. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1335. };
  1336. reset_out_n {
  1337. nvidia,pins = "reset_out_n";
  1338. nvidia,function = "reset_out_n";
  1339. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1340. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1341. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1342. };
  1343. owr {
  1344. nvidia,pins = "owr";
  1345. nvidia,function = "rsvd2";
  1346. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1347. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1348. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1349. nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
  1350. };
  1351. clk_32k_in {
  1352. nvidia,pins = "clk_32k_in";
  1353. nvidia,function = "clk";
  1354. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1355. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1356. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1357. };
  1358. jtag_rtck {
  1359. nvidia,pins = "jtag_rtck";
  1360. nvidia,function = "rtck";
  1361. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1362. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1363. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1364. };
  1365. };
  1366. };
  1367. };