meson-gxbb.dtsi 8.7 KB

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  1. /*
  2. * Copyright (c) 2016 Andreas Färber
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include <dt-bindings/gpio/gpio.h>
  43. #include <dt-bindings/interrupt-controller/irq.h>
  44. #include <dt-bindings/interrupt-controller/arm-gic.h>
  45. #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  46. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  47. / {
  48. compatible = "amlogic,meson-gxbb";
  49. interrupt-parent = <&gic>;
  50. #address-cells = <2>;
  51. #size-cells = <2>;
  52. cpus {
  53. #address-cells = <0x2>;
  54. #size-cells = <0x0>;
  55. cpu0: cpu@0 {
  56. device_type = "cpu";
  57. compatible = "arm,cortex-a53", "arm,armv8";
  58. reg = <0x0 0x0>;
  59. enable-method = "psci";
  60. };
  61. cpu1: cpu@1 {
  62. device_type = "cpu";
  63. compatible = "arm,cortex-a53", "arm,armv8";
  64. reg = <0x0 0x1>;
  65. enable-method = "psci";
  66. };
  67. cpu2: cpu@2 {
  68. device_type = "cpu";
  69. compatible = "arm,cortex-a53", "arm,armv8";
  70. reg = <0x0 0x2>;
  71. enable-method = "psci";
  72. };
  73. cpu3: cpu@3 {
  74. device_type = "cpu";
  75. compatible = "arm,cortex-a53", "arm,armv8";
  76. reg = <0x0 0x3>;
  77. enable-method = "psci";
  78. };
  79. };
  80. arm-pmu {
  81. compatible = "arm,cortex-a53-pmu";
  82. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  83. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  84. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  85. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  86. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  87. };
  88. psci {
  89. compatible = "arm,psci-0.2";
  90. method = "smc";
  91. };
  92. timer {
  93. compatible = "arm,armv8-timer";
  94. interrupts = <GIC_PPI 13
  95. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
  96. <GIC_PPI 14
  97. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
  98. <GIC_PPI 11
  99. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
  100. <GIC_PPI 10
  101. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
  102. };
  103. xtal: xtal-clk {
  104. compatible = "fixed-clock";
  105. clock-frequency = <24000000>;
  106. clock-output-names = "xtal";
  107. #clock-cells = <0>;
  108. };
  109. soc {
  110. compatible = "simple-bus";
  111. #address-cells = <2>;
  112. #size-cells = <2>;
  113. ranges;
  114. cbus: cbus@c1100000 {
  115. compatible = "simple-bus";
  116. reg = <0x0 0xc1100000 0x0 0x100000>;
  117. #address-cells = <2>;
  118. #size-cells = <2>;
  119. ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
  120. reset: reset-controller@4404 {
  121. compatible = "amlogic,meson-gxbb-reset";
  122. reg = <0x0 0x04404 0x0 0x20>;
  123. #reset-cells = <1>;
  124. };
  125. uart_A: serial@84c0 {
  126. compatible = "amlogic,meson-uart";
  127. reg = <0x0 0x84c0 0x0 0x14>;
  128. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  129. clocks = <&xtal>;
  130. status = "disabled";
  131. };
  132. uart_B: serial@84dc {
  133. compatible = "amlogic,meson-uart";
  134. reg = <0x0 0x84dc 0x0 0x14>;
  135. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  136. clocks = <&xtal>;
  137. status = "disabled";
  138. };
  139. uart_C: serial@8700 {
  140. compatible = "amlogic,meson-uart";
  141. reg = <0x0 0x8700 0x0 0x14>;
  142. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  143. clocks = <&xtal>;
  144. status = "disabled";
  145. };
  146. };
  147. gic: interrupt-controller@c4301000 {
  148. compatible = "arm,gic-400";
  149. reg = <0x0 0xc4301000 0 0x1000>,
  150. <0x0 0xc4302000 0 0x2000>,
  151. <0x0 0xc4304000 0 0x2000>,
  152. <0x0 0xc4306000 0 0x2000>;
  153. interrupt-controller;
  154. interrupts = <GIC_PPI 9
  155. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  156. #interrupt-cells = <3>;
  157. #address-cells = <0>;
  158. };
  159. aobus: aobus@c8100000 {
  160. compatible = "simple-bus";
  161. reg = <0x0 0xc8100000 0x0 0x100000>;
  162. #address-cells = <2>;
  163. #size-cells = <2>;
  164. ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
  165. pinctrl_aobus: pinctrl@14 {
  166. compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  167. #address-cells = <2>;
  168. #size-cells = <2>;
  169. ranges;
  170. gpio_ao: bank@14 {
  171. reg = <0x0 0x00014 0x0 0x8>,
  172. <0x0 0x0002c 0x0 0x4>,
  173. <0x0 0x00024 0x0 0x8>;
  174. reg-names = "mux", "pull", "gpio";
  175. gpio-controller;
  176. #gpio-cells = <2>;
  177. };
  178. uart_ao_a_pins: uart_ao_a {
  179. mux {
  180. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  181. function = "uart_ao";
  182. };
  183. };
  184. };
  185. uart_AO: serial@4c0 {
  186. compatible = "amlogic,meson-uart";
  187. reg = <0x0 0x004c0 0x0 0x14>;
  188. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  189. clocks = <&xtal>;
  190. status = "disabled";
  191. };
  192. };
  193. periphs: periphs@c8834000 {
  194. compatible = "simple-bus";
  195. reg = <0x0 0xc8834000 0x0 0x2000>;
  196. #address-cells = <2>;
  197. #size-cells = <2>;
  198. ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
  199. rng {
  200. compatible = "amlogic,meson-rng";
  201. reg = <0x0 0x0 0x0 0x4>;
  202. };
  203. pinctrl_periphs: pinctrl@4b0 {
  204. compatible = "amlogic,meson-gxbb-periphs-pinctrl";
  205. #address-cells = <2>;
  206. #size-cells = <2>;
  207. ranges;
  208. gpio: bank@4b0 {
  209. reg = <0x0 0x004b0 0x0 0x28>,
  210. <0x0 0x004e8 0x0 0x14>,
  211. <0x0 0x00120 0x0 0x14>,
  212. <0x0 0x00430 0x0 0x40>;
  213. reg-names = "mux", "pull", "pull-enable", "gpio";
  214. gpio-controller;
  215. #gpio-cells = <2>;
  216. };
  217. emmc_pins: emmc {
  218. mux {
  219. groups = "emmc_nand_d07",
  220. "emmc_cmd",
  221. "emmc_clk";
  222. function = "emmc";
  223. };
  224. };
  225. sdcard_pins: sdcard {
  226. mux {
  227. groups = "sdcard_d0",
  228. "sdcard_d1",
  229. "sdcard_d2",
  230. "sdcard_d3",
  231. "sdcard_cmd",
  232. "sdcard_clk";
  233. function = "sdcard";
  234. };
  235. };
  236. uart_a_pins: uart_a {
  237. mux {
  238. groups = "uart_tx_a",
  239. "uart_rx_a";
  240. function = "uart_a";
  241. };
  242. };
  243. uart_b_pins: uart_b {
  244. mux {
  245. groups = "uart_tx_b",
  246. "uart_rx_b";
  247. function = "uart_b";
  248. };
  249. };
  250. uart_c_pins: uart_c {
  251. mux {
  252. groups = "uart_tx_c",
  253. "uart_rx_c";
  254. function = "uart_c";
  255. };
  256. };
  257. eth_pins: eth_c {
  258. mux {
  259. groups = "eth_mdio",
  260. "eth_mdc",
  261. "eth_clk_rx_clk",
  262. "eth_rx_dv",
  263. "eth_rxd0",
  264. "eth_rxd1",
  265. "eth_rxd2",
  266. "eth_rxd3",
  267. "eth_rgmii_tx_clk",
  268. "eth_tx_en",
  269. "eth_txd0",
  270. "eth_txd1",
  271. "eth_txd2",
  272. "eth_txd3";
  273. function = "eth";
  274. };
  275. };
  276. };
  277. };
  278. hiubus: hiubus@c883c000 {
  279. compatible = "simple-bus";
  280. reg = <0x0 0xc883c000 0x0 0x2000>;
  281. #address-cells = <2>;
  282. #size-cells = <2>;
  283. ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
  284. clkc: clock-controller@0 {
  285. compatible = "amlogic,gxbb-clkc";
  286. #clock-cells = <1>;
  287. reg = <0x0 0x0 0x0 0x3db>;
  288. };
  289. };
  290. apb: apb@d0000000 {
  291. compatible = "simple-bus";
  292. reg = <0x0 0xd0000000 0x0 0x200000>;
  293. #address-cells = <2>;
  294. #size-cells = <2>;
  295. ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
  296. };
  297. ethmac: ethernet@c9410000 {
  298. compatible = "amlogic,meson6-dwmac", "snps,dwmac";
  299. reg = <0x0 0xc9410000 0x0 0x10000
  300. 0x0 0xc8834540 0x0 0x4>;
  301. interrupts = <0 8 1>;
  302. interrupt-names = "macirq";
  303. clocks = <&xtal>;
  304. clock-names = "stmmaceth";
  305. phy-mode = "rgmii";
  306. status = "disabled";
  307. };
  308. };
  309. };