imx6ul.dtsi 26 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <dt-bindings/clock/imx6ul-clock.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. #include "imx6ul-pinfunc.h"
  13. #include "skeleton.dtsi"
  14. / {
  15. aliases {
  16. ethernet0 = &fec1;
  17. ethernet1 = &fec2;
  18. gpio0 = &gpio1;
  19. gpio1 = &gpio2;
  20. gpio2 = &gpio3;
  21. gpio3 = &gpio4;
  22. gpio4 = &gpio5;
  23. i2c0 = &i2c1;
  24. i2c1 = &i2c2;
  25. i2c2 = &i2c3;
  26. i2c3 = &i2c4;
  27. mmc0 = &usdhc1;
  28. mmc1 = &usdhc2;
  29. serial0 = &uart1;
  30. serial1 = &uart2;
  31. serial2 = &uart3;
  32. serial3 = &uart4;
  33. serial4 = &uart5;
  34. serial5 = &uart6;
  35. serial6 = &uart7;
  36. serial7 = &uart8;
  37. sai1 = &sai1;
  38. sai2 = &sai2;
  39. sai3 = &sai3;
  40. spi0 = &ecspi1;
  41. spi1 = &ecspi2;
  42. spi2 = &ecspi3;
  43. spi3 = &ecspi4;
  44. usbphy0 = &usbphy1;
  45. usbphy1 = &usbphy2;
  46. };
  47. cpus {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. cpu0: cpu@0 {
  51. compatible = "arm,cortex-a7";
  52. device_type = "cpu";
  53. reg = <0>;
  54. clock-latency = <61036>; /* two CLK32 periods */
  55. operating-points = <
  56. /* kHz uV */
  57. 528000 1175000
  58. 396000 1025000
  59. 198000 950000
  60. >;
  61. fsl,soc-operating-points = <
  62. /* KHz uV */
  63. 528000 1175000
  64. 396000 1175000
  65. 198000 1175000
  66. >;
  67. clocks = <&clks IMX6UL_CLK_ARM>,
  68. <&clks IMX6UL_CLK_PLL2_BUS>,
  69. <&clks IMX6UL_CLK_PLL2_PFD2>,
  70. <&clks IMX6UL_CA7_SECONDARY_SEL>,
  71. <&clks IMX6UL_CLK_STEP>,
  72. <&clks IMX6UL_CLK_PLL1_SW>,
  73. <&clks IMX6UL_CLK_PLL1_SYS>,
  74. <&clks IMX6UL_PLL1_BYPASS>,
  75. <&clks IMX6UL_CLK_PLL1>,
  76. <&clks IMX6UL_PLL1_BYPASS_SRC>,
  77. <&clks IMX6UL_CLK_OSC>;
  78. clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
  79. "secondary_sel", "step", "pll1_sw",
  80. "pll1_sys", "pll1_bypass", "pll1",
  81. "pll1_bypass_src", "osc";
  82. arm-supply = <&reg_arm>;
  83. soc-supply = <&reg_soc>;
  84. };
  85. };
  86. intc: interrupt-controller@00a01000 {
  87. compatible = "arm,cortex-a7-gic";
  88. #interrupt-cells = <3>;
  89. interrupt-controller;
  90. reg = <0x00a01000 0x1000>,
  91. <0x00a02000 0x1000>,
  92. <0x00a04000 0x2000>,
  93. <0x00a06000 0x2000>;
  94. };
  95. ckil: clock-cli {
  96. compatible = "fixed-clock";
  97. #clock-cells = <0>;
  98. clock-frequency = <32768>;
  99. clock-output-names = "ckil";
  100. };
  101. osc: clock-osc {
  102. compatible = "fixed-clock";
  103. #clock-cells = <0>;
  104. clock-frequency = <24000000>;
  105. clock-output-names = "osc";
  106. };
  107. ipp_di0: clock-di0 {
  108. compatible = "fixed-clock";
  109. #clock-cells = <0>;
  110. clock-frequency = <0>;
  111. clock-output-names = "ipp_di0";
  112. };
  113. ipp_di1: clock-di1 {
  114. compatible = "fixed-clock";
  115. #clock-cells = <0>;
  116. clock-frequency = <0>;
  117. clock-output-names = "ipp_di1";
  118. };
  119. soc {
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. compatible = "simple-bus";
  123. interrupt-parent = <&gpc>;
  124. ranges;
  125. pmu {
  126. compatible = "arm,cortex-a7-pmu";
  127. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  128. status = "disabled";
  129. };
  130. ocram: sram@00900000 {
  131. compatible = "mmio-sram";
  132. reg = <0x00900000 0x20000>;
  133. };
  134. dma_apbh: dma-apbh@01804000 {
  135. compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  136. reg = <0x01804000 0x2000>;
  137. interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  138. <0 13 IRQ_TYPE_LEVEL_HIGH>,
  139. <0 13 IRQ_TYPE_LEVEL_HIGH>,
  140. <0 13 IRQ_TYPE_LEVEL_HIGH>;
  141. interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  142. #dma-cells = <1>;
  143. dma-channels = <4>;
  144. clocks = <&clks IMX6UL_CLK_APBHDMA>;
  145. };
  146. gpmi: gpmi-nand@01806000 {
  147. compatible = "fsl,imx6q-gpmi-nand";
  148. #address-cells = <1>;
  149. #size-cells = <1>;
  150. reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
  151. reg-names = "gpmi-nand", "bch";
  152. interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
  153. interrupt-names = "bch";
  154. clocks = <&clks IMX6UL_CLK_GPMI_IO>,
  155. <&clks IMX6UL_CLK_GPMI_APB>,
  156. <&clks IMX6UL_CLK_GPMI_BCH>,
  157. <&clks IMX6UL_CLK_GPMI_BCH_APB>,
  158. <&clks IMX6UL_CLK_PER_BCH>;
  159. clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  160. "gpmi_bch_apb", "per1_bch";
  161. dmas = <&dma_apbh 0>;
  162. dma-names = "rx-tx";
  163. status = "disabled";
  164. };
  165. aips1: aips-bus@02000000 {
  166. compatible = "fsl,aips-bus", "simple-bus";
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. reg = <0x02000000 0x100000>;
  170. ranges;
  171. spba-bus@02000000 {
  172. compatible = "fsl,spba-bus", "simple-bus";
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. reg = <0x02000000 0x40000>;
  176. ranges;
  177. ecspi1: ecspi@02008000 {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
  181. reg = <0x02008000 0x4000>;
  182. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  183. clocks = <&clks IMX6UL_CLK_ECSPI1>,
  184. <&clks IMX6UL_CLK_ECSPI1>;
  185. clock-names = "ipg", "per";
  186. status = "disabled";
  187. };
  188. ecspi2: ecspi@0200c000 {
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
  192. reg = <0x0200c000 0x4000>;
  193. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  194. clocks = <&clks IMX6UL_CLK_ECSPI2>,
  195. <&clks IMX6UL_CLK_ECSPI2>;
  196. clock-names = "ipg", "per";
  197. status = "disabled";
  198. };
  199. ecspi3: ecspi@02010000 {
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
  203. reg = <0x02010000 0x4000>;
  204. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  205. clocks = <&clks IMX6UL_CLK_ECSPI3>,
  206. <&clks IMX6UL_CLK_ECSPI3>;
  207. clock-names = "ipg", "per";
  208. status = "disabled";
  209. };
  210. ecspi4: ecspi@02014000 {
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
  214. reg = <0x02014000 0x4000>;
  215. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  216. clocks = <&clks IMX6UL_CLK_ECSPI4>,
  217. <&clks IMX6UL_CLK_ECSPI4>;
  218. clock-names = "ipg", "per";
  219. status = "disabled";
  220. };
  221. uart7: serial@02018000 {
  222. compatible = "fsl,imx6ul-uart",
  223. "fsl,imx6q-uart";
  224. reg = <0x02018000 0x4000>;
  225. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  226. clocks = <&clks IMX6UL_CLK_UART7_IPG>,
  227. <&clks IMX6UL_CLK_UART7_SERIAL>;
  228. clock-names = "ipg", "per";
  229. status = "disabled";
  230. };
  231. uart1: serial@02020000 {
  232. compatible = "fsl,imx6ul-uart",
  233. "fsl,imx6q-uart";
  234. reg = <0x02020000 0x4000>;
  235. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  236. clocks = <&clks IMX6UL_CLK_UART1_IPG>,
  237. <&clks IMX6UL_CLK_UART1_SERIAL>;
  238. clock-names = "ipg", "per";
  239. status = "disabled";
  240. };
  241. uart8: serial@02024000 {
  242. compatible = "fsl,imx6ul-uart",
  243. "fsl,imx6q-uart";
  244. reg = <0x02024000 0x4000>;
  245. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  246. clocks = <&clks IMX6UL_CLK_UART8_IPG>,
  247. <&clks IMX6UL_CLK_UART8_SERIAL>;
  248. clock-names = "ipg", "per";
  249. status = "disabled";
  250. };
  251. sai1: sai@02028000 {
  252. #sound-dai-cells = <0>;
  253. compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
  254. reg = <0x02028000 0x4000>;
  255. interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  256. clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
  257. <&clks IMX6UL_CLK_SAI1>,
  258. <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
  259. clock-names = "bus", "mclk1", "mclk2", "mclk3";
  260. dmas = <&sdma 35 24 0>,
  261. <&sdma 36 24 0>;
  262. dma-names = "rx", "tx";
  263. status = "disabled";
  264. };
  265. sai2: sai@0202c000 {
  266. #sound-dai-cells = <0>;
  267. compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
  268. reg = <0x0202c000 0x4000>;
  269. interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  270. clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
  271. <&clks IMX6UL_CLK_SAI2>,
  272. <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
  273. clock-names = "bus", "mclk1", "mclk2", "mclk3";
  274. dmas = <&sdma 37 24 0>,
  275. <&sdma 38 24 0>;
  276. dma-names = "rx", "tx";
  277. status = "disabled";
  278. };
  279. sai3: sai@02030000 {
  280. #sound-dai-cells = <0>;
  281. compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
  282. reg = <0x02030000 0x4000>;
  283. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  284. clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
  285. <&clks IMX6UL_CLK_SAI3>,
  286. <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
  287. clock-names = "bus", "mclk1", "mclk2", "mclk3";
  288. dmas = <&sdma 39 24 0>,
  289. <&sdma 40 24 0>;
  290. dma-names = "rx", "tx";
  291. status = "disabled";
  292. };
  293. };
  294. tsc: tsc@02040000 {
  295. compatible = "fsl,imx6ul-tsc";
  296. reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
  297. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  298. <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  299. clocks = <&clks IMX6UL_CLK_IPG>,
  300. <&clks IMX6UL_CLK_ADC2>;
  301. clock-names = "tsc", "adc";
  302. status = "disabled";
  303. };
  304. pwm1: pwm@02080000 {
  305. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  306. reg = <0x02080000 0x4000>;
  307. interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  308. clocks = <&clks IMX6UL_CLK_PWM1>,
  309. <&clks IMX6UL_CLK_PWM1>;
  310. clock-names = "ipg", "per";
  311. #pwm-cells = <2>;
  312. status = "disabled";
  313. };
  314. pwm2: pwm@02084000 {
  315. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  316. reg = <0x02084000 0x4000>;
  317. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  318. clocks = <&clks IMX6UL_CLK_PWM2>,
  319. <&clks IMX6UL_CLK_PWM2>;
  320. clock-names = "ipg", "per";
  321. #pwm-cells = <2>;
  322. status = "disabled";
  323. };
  324. pwm3: pwm@02088000 {
  325. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  326. reg = <0x02088000 0x4000>;
  327. interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  328. clocks = <&clks IMX6UL_CLK_PWM3>,
  329. <&clks IMX6UL_CLK_PWM3>;
  330. clock-names = "ipg", "per";
  331. #pwm-cells = <2>;
  332. status = "disabled";
  333. };
  334. pwm4: pwm@0208c000 {
  335. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  336. reg = <0x0208c000 0x4000>;
  337. interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  338. clocks = <&clks IMX6UL_CLK_PWM4>,
  339. <&clks IMX6UL_CLK_PWM4>;
  340. clock-names = "ipg", "per";
  341. #pwm-cells = <2>;
  342. status = "disabled";
  343. };
  344. can1: flexcan@02090000 {
  345. compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
  346. reg = <0x02090000 0x4000>;
  347. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  348. clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
  349. <&clks IMX6UL_CLK_CAN1_SERIAL>;
  350. clock-names = "ipg", "per";
  351. status = "disabled";
  352. };
  353. can2: flexcan@02094000 {
  354. compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
  355. reg = <0x02094000 0x4000>;
  356. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  357. clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
  358. <&clks IMX6UL_CLK_CAN2_SERIAL>;
  359. clock-names = "ipg", "per";
  360. status = "disabled";
  361. };
  362. gpt1: gpt@02098000 {
  363. compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
  364. reg = <0x02098000 0x4000>;
  365. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  366. clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
  367. <&clks IMX6UL_CLK_GPT1_SERIAL>;
  368. clock-names = "ipg", "per";
  369. };
  370. gpio1: gpio@0209c000 {
  371. compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
  372. reg = <0x0209c000 0x4000>;
  373. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
  374. <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  375. gpio-controller;
  376. #gpio-cells = <2>;
  377. interrupt-controller;
  378. #interrupt-cells = <2>;
  379. gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
  380. <&iomuxc 16 33 16>;
  381. };
  382. gpio2: gpio@020a0000 {
  383. compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
  384. reg = <0x020a0000 0x4000>;
  385. interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  386. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  387. gpio-controller;
  388. #gpio-cells = <2>;
  389. interrupt-controller;
  390. #interrupt-cells = <2>;
  391. gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
  392. };
  393. gpio3: gpio@020a4000 {
  394. compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
  395. reg = <0x020a4000 0x4000>;
  396. interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
  397. <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  398. gpio-controller;
  399. #gpio-cells = <2>;
  400. interrupt-controller;
  401. #interrupt-cells = <2>;
  402. gpio-ranges = <&iomuxc 0 65 29>;
  403. };
  404. gpio4: gpio@020a8000 {
  405. compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
  406. reg = <0x020a8000 0x4000>;
  407. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  408. <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  409. gpio-controller;
  410. #gpio-cells = <2>;
  411. interrupt-controller;
  412. #interrupt-cells = <2>;
  413. gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
  414. };
  415. gpio5: gpio@020ac000 {
  416. compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
  417. reg = <0x020ac000 0x4000>;
  418. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
  419. <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  420. gpio-controller;
  421. #gpio-cells = <2>;
  422. interrupt-controller;
  423. #interrupt-cells = <2>;
  424. gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
  425. };
  426. fec2: ethernet@020b4000 {
  427. compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
  428. reg = <0x020b4000 0x4000>;
  429. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  430. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  431. clocks = <&clks IMX6UL_CLK_ENET>,
  432. <&clks IMX6UL_CLK_ENET_AHB>,
  433. <&clks IMX6UL_CLK_ENET_PTP>,
  434. <&clks IMX6UL_CLK_ENET2_REF_125M>,
  435. <&clks IMX6UL_CLK_ENET2_REF_125M>;
  436. clock-names = "ipg", "ahb", "ptp",
  437. "enet_clk_ref", "enet_out";
  438. fsl,num-tx-queues=<1>;
  439. fsl,num-rx-queues=<1>;
  440. status = "disabled";
  441. };
  442. kpp: kpp@020b8000 {
  443. compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
  444. reg = <0x020b8000 0x4000>;
  445. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  446. clocks = <&clks IMX6UL_CLK_KPP>;
  447. status = "disabled";
  448. };
  449. wdog1: wdog@020bc000 {
  450. compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
  451. reg = <0x020bc000 0x4000>;
  452. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  453. clocks = <&clks IMX6UL_CLK_WDOG1>;
  454. };
  455. wdog2: wdog@020c0000 {
  456. compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
  457. reg = <0x020c0000 0x4000>;
  458. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  459. clocks = <&clks IMX6UL_CLK_WDOG2>;
  460. status = "disabled";
  461. };
  462. clks: ccm@020c4000 {
  463. compatible = "fsl,imx6ul-ccm";
  464. reg = <0x020c4000 0x4000>;
  465. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  466. <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  467. #clock-cells = <1>;
  468. clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
  469. clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
  470. };
  471. anatop: anatop@020c8000 {
  472. compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
  473. "syscon", "simple-bus";
  474. reg = <0x020c8000 0x1000>;
  475. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
  476. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  477. <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  478. reg_3p0: regulator-3p0 {
  479. compatible = "fsl,anatop-regulator";
  480. regulator-name = "vdd3p0";
  481. regulator-min-microvolt = <2625000>;
  482. regulator-max-microvolt = <3400000>;
  483. anatop-reg-offset = <0x120>;
  484. anatop-vol-bit-shift = <8>;
  485. anatop-vol-bit-width = <5>;
  486. anatop-min-bit-val = <0>;
  487. anatop-min-voltage = <2625000>;
  488. anatop-max-voltage = <3400000>;
  489. anatop-enable-bit = <0>;
  490. };
  491. reg_arm: regulator-vddcore {
  492. compatible = "fsl,anatop-regulator";
  493. regulator-name = "cpu";
  494. regulator-min-microvolt = <725000>;
  495. regulator-max-microvolt = <1450000>;
  496. regulator-always-on;
  497. anatop-reg-offset = <0x140>;
  498. anatop-vol-bit-shift = <0>;
  499. anatop-vol-bit-width = <5>;
  500. anatop-delay-reg-offset = <0x170>;
  501. anatop-delay-bit-shift = <24>;
  502. anatop-delay-bit-width = <2>;
  503. anatop-min-bit-val = <1>;
  504. anatop-min-voltage = <725000>;
  505. anatop-max-voltage = <1450000>;
  506. };
  507. reg_soc: regulator-vddsoc {
  508. compatible = "fsl,anatop-regulator";
  509. regulator-name = "vddsoc";
  510. regulator-min-microvolt = <725000>;
  511. regulator-max-microvolt = <1450000>;
  512. regulator-always-on;
  513. anatop-reg-offset = <0x140>;
  514. anatop-vol-bit-shift = <18>;
  515. anatop-vol-bit-width = <5>;
  516. anatop-delay-reg-offset = <0x170>;
  517. anatop-delay-bit-shift = <28>;
  518. anatop-delay-bit-width = <2>;
  519. anatop-min-bit-val = <1>;
  520. anatop-min-voltage = <725000>;
  521. anatop-max-voltage = <1450000>;
  522. };
  523. };
  524. usbphy1: usbphy@020c9000 {
  525. compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
  526. reg = <0x020c9000 0x1000>;
  527. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  528. clocks = <&clks IMX6UL_CLK_USBPHY1>;
  529. phy-3p0-supply = <&reg_3p0>;
  530. fsl,anatop = <&anatop>;
  531. };
  532. usbphy2: usbphy@020ca000 {
  533. compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
  534. reg = <0x020ca000 0x1000>;
  535. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  536. clocks = <&clks IMX6UL_CLK_USBPHY2>;
  537. phy-3p0-supply = <&reg_3p0>;
  538. fsl,anatop = <&anatop>;
  539. };
  540. snvs: snvs@020cc000 {
  541. compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
  542. reg = <0x020cc000 0x4000>;
  543. snvs_rtc: snvs-rtc-lp {
  544. compatible = "fsl,sec-v4.0-mon-rtc-lp";
  545. regmap = <&snvs>;
  546. offset = <0x34>;
  547. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  548. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  549. };
  550. snvs_poweroff: snvs-poweroff {
  551. compatible = "syscon-poweroff";
  552. regmap = <&snvs>;
  553. offset = <0x38>;
  554. mask = <0x60>;
  555. status = "disabled";
  556. };
  557. snvs_pwrkey: snvs-powerkey {
  558. compatible = "fsl,sec-v4.0-pwrkey";
  559. regmap = <&snvs>;
  560. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  561. linux,keycode = <KEY_POWER>;
  562. wakeup-source;
  563. };
  564. };
  565. epit1: epit@020d0000 {
  566. reg = <0x020d0000 0x4000>;
  567. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  568. };
  569. epit2: epit@020d4000 {
  570. reg = <0x020d4000 0x4000>;
  571. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  572. };
  573. src: src@020d8000 {
  574. compatible = "fsl,imx6ul-src", "fsl,imx51-src";
  575. reg = <0x020d8000 0x4000>;
  576. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
  577. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  578. #reset-cells = <1>;
  579. };
  580. gpc: gpc@020dc000 {
  581. compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
  582. reg = <0x020dc000 0x4000>;
  583. interrupt-controller;
  584. #interrupt-cells = <3>;
  585. interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  586. interrupt-parent = <&intc>;
  587. };
  588. iomuxc: iomuxc@020e0000 {
  589. compatible = "fsl,imx6ul-iomuxc";
  590. reg = <0x020e0000 0x4000>;
  591. };
  592. gpr: iomuxc-gpr@020e4000 {
  593. compatible = "fsl,imx6ul-iomuxc-gpr",
  594. "fsl,imx6q-iomuxc-gpr", "syscon";
  595. reg = <0x020e4000 0x4000>;
  596. };
  597. gpt2: gpt@020e8000 {
  598. compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
  599. reg = <0x020e8000 0x4000>;
  600. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  601. clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
  602. <&clks IMX6UL_CLK_GPT2_SERIAL>;
  603. clock-names = "ipg", "per";
  604. };
  605. sdma: sdma@020ec000 {
  606. compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
  607. "fsl,imx35-sdma";
  608. reg = <0x020ec000 0x4000>;
  609. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  610. clocks = <&clks IMX6UL_CLK_SDMA>,
  611. <&clks IMX6UL_CLK_SDMA>;
  612. clock-names = "ipg", "ahb";
  613. #dma-cells = <3>;
  614. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
  615. };
  616. pwm5: pwm@020f0000 {
  617. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  618. reg = <0x020f0000 0x4000>;
  619. interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  620. clocks = <&clks IMX6UL_CLK_PWM5>,
  621. <&clks IMX6UL_CLK_PWM5>;
  622. clock-names = "ipg", "per";
  623. #pwm-cells = <2>;
  624. status = "disabled";
  625. };
  626. pwm6: pwm@020f4000 {
  627. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  628. reg = <0x020f4000 0x4000>;
  629. interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  630. clocks = <&clks IMX6UL_CLK_PWM6>,
  631. <&clks IMX6UL_CLK_PWM6>;
  632. clock-names = "ipg", "per";
  633. #pwm-cells = <2>;
  634. status = "disabled";
  635. };
  636. pwm7: pwm@020f8000 {
  637. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  638. reg = <0x020f8000 0x4000>;
  639. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  640. clocks = <&clks IMX6UL_CLK_PWM7>,
  641. <&clks IMX6UL_CLK_PWM7>;
  642. clock-names = "ipg", "per";
  643. #pwm-cells = <2>;
  644. status = "disabled";
  645. };
  646. pwm8: pwm@020fc000 {
  647. compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
  648. reg = <0x020fc000 0x4000>;
  649. interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  650. clocks = <&clks IMX6UL_CLK_PWM8>,
  651. <&clks IMX6UL_CLK_PWM8>;
  652. clock-names = "ipg", "per";
  653. #pwm-cells = <2>;
  654. status = "disabled";
  655. };
  656. };
  657. aips2: aips-bus@02100000 {
  658. compatible = "fsl,aips-bus", "simple-bus";
  659. #address-cells = <1>;
  660. #size-cells = <1>;
  661. reg = <0x02100000 0x100000>;
  662. ranges;
  663. usbotg1: usb@02184000 {
  664. compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
  665. reg = <0x02184000 0x200>;
  666. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  667. clocks = <&clks IMX6UL_CLK_USBOH3>;
  668. fsl,usbphy = <&usbphy1>;
  669. fsl,usbmisc = <&usbmisc 0>;
  670. fsl,anatop = <&anatop>;
  671. ahb-burst-config = <0x0>;
  672. tx-burst-size-dword = <0x10>;
  673. rx-burst-size-dword = <0x10>;
  674. status = "disabled";
  675. };
  676. usbotg2: usb@02184200 {
  677. compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
  678. reg = <0x02184200 0x200>;
  679. interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  680. clocks = <&clks IMX6UL_CLK_USBOH3>;
  681. fsl,usbphy = <&usbphy2>;
  682. fsl,usbmisc = <&usbmisc 1>;
  683. ahb-burst-config = <0x0>;
  684. tx-burst-size-dword = <0x10>;
  685. rx-burst-size-dword = <0x10>;
  686. status = "disabled";
  687. };
  688. usbmisc: usbmisc@02184800 {
  689. #index-cells = <1>;
  690. compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
  691. reg = <0x02184800 0x200>;
  692. };
  693. fec1: ethernet@02188000 {
  694. compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
  695. reg = <0x02188000 0x4000>;
  696. interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  697. <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  698. clocks = <&clks IMX6UL_CLK_ENET>,
  699. <&clks IMX6UL_CLK_ENET_AHB>,
  700. <&clks IMX6UL_CLK_ENET_PTP>,
  701. <&clks IMX6UL_CLK_ENET_REF>,
  702. <&clks IMX6UL_CLK_ENET_REF>;
  703. clock-names = "ipg", "ahb", "ptp",
  704. "enet_clk_ref", "enet_out";
  705. fsl,num-tx-queues=<1>;
  706. fsl,num-rx-queues=<1>;
  707. status = "disabled";
  708. };
  709. usdhc1: usdhc@02190000 {
  710. compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
  711. reg = <0x02190000 0x4000>;
  712. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  713. clocks = <&clks IMX6UL_CLK_USDHC1>,
  714. <&clks IMX6UL_CLK_USDHC1>,
  715. <&clks IMX6UL_CLK_USDHC1>;
  716. clock-names = "ipg", "ahb", "per";
  717. bus-width = <4>;
  718. status = "disabled";
  719. };
  720. usdhc2: usdhc@02194000 {
  721. compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
  722. reg = <0x02194000 0x4000>;
  723. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  724. clocks = <&clks IMX6UL_CLK_USDHC2>,
  725. <&clks IMX6UL_CLK_USDHC2>,
  726. <&clks IMX6UL_CLK_USDHC2>;
  727. clock-names = "ipg", "ahb", "per";
  728. bus-width = <4>;
  729. status = "disabled";
  730. };
  731. adc1: adc@02198000 {
  732. compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
  733. reg = <0x02198000 0x4000>;
  734. interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  735. clocks = <&clks IMX6UL_CLK_ADC1>;
  736. num-channels = <2>;
  737. clock-names = "adc";
  738. fsl,adck-max-frequency = <30000000>, <40000000>,
  739. <20000000>;
  740. status = "disabled";
  741. };
  742. i2c1: i2c@021a0000 {
  743. #address-cells = <1>;
  744. #size-cells = <0>;
  745. compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
  746. reg = <0x021a0000 0x4000>;
  747. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  748. clocks = <&clks IMX6UL_CLK_I2C1>;
  749. status = "disabled";
  750. };
  751. i2c2: i2c@021a4000 {
  752. #address-cells = <1>;
  753. #size-cells = <0>;
  754. compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
  755. reg = <0x021a4000 0x4000>;
  756. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  757. clocks = <&clks IMX6UL_CLK_I2C2>;
  758. status = "disabled";
  759. };
  760. i2c3: i2c@021a8000 {
  761. #address-cells = <1>;
  762. #size-cells = <0>;
  763. compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
  764. reg = <0x021a8000 0x4000>;
  765. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  766. clocks = <&clks IMX6UL_CLK_I2C3>;
  767. status = "disabled";
  768. };
  769. mmdc: mmdc@021b0000 {
  770. compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
  771. reg = <0x021b0000 0x4000>;
  772. };
  773. lcdif: lcdif@021c8000 {
  774. compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
  775. reg = <0x021c8000 0x4000>;
  776. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  777. clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
  778. <&clks IMX6UL_CLK_LCDIF_APB>,
  779. <&clks IMX6UL_CLK_DUMMY>;
  780. clock-names = "pix", "axi", "disp_axi";
  781. status = "disabled";
  782. };
  783. qspi: qspi@021e0000 {
  784. #address-cells = <1>;
  785. #size-cells = <0>;
  786. compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
  787. reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
  788. reg-names = "QuadSPI", "QuadSPI-memory";
  789. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  790. clocks = <&clks IMX6UL_CLK_QSPI>,
  791. <&clks IMX6UL_CLK_QSPI>;
  792. clock-names = "qspi_en", "qspi";
  793. status = "disabled";
  794. };
  795. uart2: serial@021e8000 {
  796. compatible = "fsl,imx6ul-uart",
  797. "fsl,imx6q-uart";
  798. reg = <0x021e8000 0x4000>;
  799. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  800. clocks = <&clks IMX6UL_CLK_UART2_IPG>,
  801. <&clks IMX6UL_CLK_UART2_SERIAL>;
  802. clock-names = "ipg", "per";
  803. status = "disabled";
  804. };
  805. uart3: serial@021ec000 {
  806. compatible = "fsl,imx6ul-uart",
  807. "fsl,imx6q-uart";
  808. reg = <0x021ec000 0x4000>;
  809. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  810. clocks = <&clks IMX6UL_CLK_UART3_IPG>,
  811. <&clks IMX6UL_CLK_UART3_SERIAL>;
  812. clock-names = "ipg", "per";
  813. status = "disabled";
  814. };
  815. uart4: serial@021f0000 {
  816. compatible = "fsl,imx6ul-uart",
  817. "fsl,imx6q-uart";
  818. reg = <0x021f0000 0x4000>;
  819. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  820. clocks = <&clks IMX6UL_CLK_UART4_IPG>,
  821. <&clks IMX6UL_CLK_UART4_SERIAL>;
  822. clock-names = "ipg", "per";
  823. status = "disabled";
  824. };
  825. uart5: serial@021f4000 {
  826. compatible = "fsl,imx6ul-uart",
  827. "fsl,imx6q-uart";
  828. reg = <0x021f4000 0x4000>;
  829. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  830. clocks = <&clks IMX6UL_CLK_UART5_IPG>,
  831. <&clks IMX6UL_CLK_UART5_SERIAL>;
  832. clock-names = "ipg", "per";
  833. status = "disabled";
  834. };
  835. i2c4: i2c@021f8000 {
  836. #address-cells = <1>;
  837. #size-cells = <0>;
  838. compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
  839. reg = <0x021f8000 0x4000>;
  840. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  841. clocks = <&clks IMX6UL_CLK_I2C4>;
  842. status = "disabled";
  843. };
  844. uart6: serial@021fc000 {
  845. compatible = "fsl,imx6ul-uart",
  846. "fsl,imx6q-uart";
  847. reg = <0x021fc000 0x4000>;
  848. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  849. clocks = <&clks IMX6UL_CLK_UART6_IPG>,
  850. <&clks IMX6UL_CLK_UART6_SERIAL>;
  851. clock-names = "ipg", "per";
  852. status = "disabled";
  853. };
  854. };
  855. };
  856. };