imx53.dtsi 2.7 KB

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  1. /*
  2. * Copyright 2016 Beckhoff Automation
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. * Copyright 2011 Linaro Ltd.
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. #include "skeleton.dtsi"
  14. #include "imx53-pinfunc.h"
  15. #include <dt-bindings/clock/imx5-clock.h>
  16. #include <dt-bindings/gpio/gpio.h>
  17. #include <dt-bindings/input/input.h>
  18. #include <dt-bindings/interrupt-controller/irq.h>
  19. / {
  20. aliases {
  21. serial1 = &uart2;
  22. };
  23. soc {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "simple-bus";
  27. ranges;
  28. aips@50000000 { /* AIPS1 */
  29. compatible = "fsl,aips-bus", "simple-bus";
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. reg = <0x50000000 0x10000000>;
  33. ranges;
  34. iomuxc: iomuxc@53fa8000 {
  35. compatible = "fsl,imx53-iomuxc";
  36. reg = <0x53fa8000 0x4000>;
  37. };
  38. gpr: iomuxc-gpr@53fa8000 {
  39. compatible = "fsl,imx53-iomuxc-gpr", "syscon";
  40. reg = <0x53fa8000 0xc>;
  41. };
  42. uart2: serial@53fc0000 {
  43. compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
  44. reg = <0x53fc0000 0x4000>;
  45. interrupts = <32>;
  46. clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
  47. <&clks IMX5_CLK_UART2_PER_GATE>;
  48. clock-names = "ipg", "per";
  49. dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
  50. dma-names = "rx", "tx";
  51. status = "disabled";
  52. };
  53. clks: ccm@53fd4000{
  54. compatible = "fsl,imx53-ccm";
  55. reg = <0x53fd4000 0x4000>;
  56. interrupts = <0 71 0x04 0 72 0x04>;
  57. #clock-cells = <1>;
  58. };
  59. gpio7: gpio@53fe4000 {
  60. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  61. reg = <0x53fe4000 0x4000>;
  62. interrupts = <107 108>;
  63. gpio-controller;
  64. #gpio-cells = <2>;
  65. interrupt-controller;
  66. #interrupt-cells = <2>;
  67. };
  68. };
  69. aips@60000000 { /* AIPS2 */
  70. compatible = "fsl,aips-bus", "simple-bus";
  71. #address-cells = <1>;
  72. #size-cells = <1>;
  73. reg = <0x60000000 0x10000000>;
  74. ranges;
  75. sdma: sdma@63fb0000 {
  76. compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  77. reg = <0x63fb0000 0x4000>;
  78. interrupts = <6>;
  79. clocks = <&clks IMX5_CLK_SDMA_GATE>,
  80. <&clks IMX5_CLK_SDMA_GATE>;
  81. clock-names = "ipg", "ahb";
  82. #dma-cells = <3>;
  83. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
  84. };
  85. fec: ethernet@63fec000 {
  86. compatible = "fsl,imx53-fec", "fsl,imx25-fec";
  87. reg = <0x63fec000 0x4000>;
  88. interrupts = <87>;
  89. clocks = <&clks IMX5_CLK_FEC_GATE>,
  90. <&clks IMX5_CLK_FEC_GATE>,
  91. <&clks IMX5_CLK_FEC_GATE>;
  92. clock-names = "ipg", "ahb", "ptp";
  93. status = "disabled";
  94. };
  95. };
  96. };
  97. };