fsl-ls2080a.dtsi 2.3 KB

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  1. /*
  2. * Freescale ls2080a SOC common device tree source
  3. *
  4. * Copyright 2013-2015 Freescale Semiconductor, Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. / {
  9. compatible = "fsl,ls2080a";
  10. interrupt-parent = <&gic>;
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. memory@80000000 {
  14. device_type = "memory";
  15. reg = <0x00000000 0x80000000 0 0x80000000>;
  16. /* DRAM space - 1, size : 2 GB DRAM */
  17. };
  18. gic: interrupt-controller@6000000 {
  19. compatible = "arm,gic-v3";
  20. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  21. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  22. #interrupt-cells = <3>;
  23. interrupt-controller;
  24. interrupts = <1 9 0x4>;
  25. };
  26. timer {
  27. compatible = "arm,armv8-timer";
  28. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  29. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  30. <1 11 0x8>, /* Virtual PPI, active-low */
  31. <1 10 0x8>; /* Hypervisor PPI, active-low */
  32. };
  33. serial0: serial@21c0500 {
  34. device_type = "serial";
  35. compatible = "fsl,ns16550", "ns16550a";
  36. reg = <0x0 0x21c0500 0x0 0x100>;
  37. clock-frequency = <0>; /* Updated by bootloader */
  38. interrupts = <0 32 0x1>; /* edge triggered */
  39. };
  40. serial1: serial@21c0600 {
  41. device_type = "serial";
  42. compatible = "fsl,ns16550", "ns16550a";
  43. reg = <0x0 0x21c0600 0x0 0x100>;
  44. clock-frequency = <0>; /* Updated by bootloader */
  45. interrupts = <0 32 0x1>; /* edge triggered */
  46. };
  47. fsl_mc: fsl-mc@80c000000 {
  48. compatible = "fsl,qoriq-mc";
  49. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  50. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  51. };
  52. dspi: dspi@2100000 {
  53. compatible = "fsl,vf610-dspi";
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. reg = <0x0 0x2100000 0x0 0x10000>;
  57. interrupts = <0 26 0x4>; /* Level high type */
  58. num-cs = <6>;
  59. };
  60. qspi: quadspi@1550000 {
  61. compatible = "fsl,vf610-qspi";
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. reg = <0x0 0x20c0000 0x0 0x10000>,
  65. <0x0 0x20000000 0x0 0x10000000>;
  66. reg-names = "QuadSPI", "QuadSPI-memory";
  67. num-cs = <4>;
  68. };
  69. usb0: usb3@3100000 {
  70. compatible = "fsl,layerscape-dwc3";
  71. reg = <0x0 0x3100000 0x0 0x10000>;
  72. interrupts = <0 80 0x4>; /* Level high type */
  73. dr_mode = "host";
  74. };
  75. usb1: usb3@3110000 {
  76. compatible = "fsl,layerscape-dwc3";
  77. reg = <0x0 0x3110000 0x0 0x10000>;
  78. interrupts = <0 81 0x4>; /* Level high type */
  79. dr_mode = "host";
  80. };
  81. };