exynos54xx.dtsi 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218
  1. /*
  2. * (C) Copyright 2013 SAMSUNG Electronics
  3. * SAMSUNG EXYNOS5420 SoC device tree source
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include "exynos5.dtsi"
  8. #include "exynos54xx-pinctrl.dtsi"
  9. / {
  10. config {
  11. machine-arch-id = <4151>;
  12. };
  13. aliases {
  14. i2c0 = "/i2c@12C60000";
  15. i2c1 = "/i2c@12C70000";
  16. i2c2 = "/i2c@12C80000";
  17. i2c3 = "/i2c@12C90000";
  18. i2c4 = "/i2c@12CA0000";
  19. i2c5 = "/i2c@12CB0000";
  20. i2c6 = "/i2c@12CC0000";
  21. i2c7 = "/i2c@12CD0000";
  22. i2c8 = "/i2c@12E00000";
  23. i2c9 = "/i2c@12E10000";
  24. i2c10 = "/i2c@12E20000";
  25. pinctrl0 = &pinctrl_0;
  26. pinctrl1 = &pinctrl_1;
  27. pinctrl2 = &pinctrl_2;
  28. pinctrl3 = &pinctrl_3;
  29. pinctrl4 = &pinctrl_4;
  30. spi0 = "/spi@12d20000";
  31. spi1 = "/spi@12d30000";
  32. spi2 = "/spi@12d40000";
  33. spi3 = "/spi@131a0000";
  34. spi4 = "/spi@131b0000";
  35. mmc0 = "/mmc@12200000";
  36. mmc1 = "/mmc@12210000";
  37. mmc2 = "/mmc@12220000";
  38. xhci0 = "/xhci@12000000";
  39. xhci1 = "/xhci@12400000";
  40. };
  41. adc@12D10000 {
  42. compatible = "samsung,exynos-adc-v2";
  43. reg = <0x12D10000 0x100>;
  44. interrupts = <0 106 0>;
  45. status = "disabled";
  46. };
  47. hsi2c_4: i2c@12CA0000 {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. compatible = "samsung,exynos5-hsi2c";
  51. reg = <0x12CA0000 0x100>;
  52. interrupts = <0 60 0>;
  53. };
  54. i2c@12CB0000 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. compatible = "samsung,exynos5-hsi2c";
  58. reg = <0x12CB0000 0x100>;
  59. interrupts = <0 61 0>;
  60. };
  61. i2c@12CC0000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. compatible = "samsung,exynos5-hsi2c";
  65. reg = <0x12CC0000 0x100>;
  66. interrupts = <0 62 0>;
  67. };
  68. i2c@12CD0000 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. compatible = "samsung,exynos5-hsi2c";
  72. reg = <0x12CD0000 0x100>;
  73. interrupts = <0 63 0>;
  74. };
  75. i2c@12E00000 {
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. compatible = "samsung,exynos5-hsi2c";
  79. reg = <0x12E00000 0x100>;
  80. interrupts = <0 87 0>;
  81. };
  82. i2c@12E10000 {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. compatible = "samsung,exynos5-hsi2c";
  86. reg = <0x12E10000 0x100>;
  87. interrupts = <0 88 0>;
  88. };
  89. i2c@12E20000 {
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. compatible = "samsung,exynos5-hsi2c";
  93. reg = <0x12E20000 0x100>;
  94. interrupts = <0 203 0>;
  95. };
  96. mmc@12200000 {
  97. samsung,bus-width = <8>;
  98. samsung,timing = <1 3 3>;
  99. samsung,removable = <0>;
  100. samsung,pre-init;
  101. };
  102. mmc@12210000 {
  103. status = "disabled";
  104. };
  105. mmc@12220000 {
  106. samsung,bus-width = <4>;
  107. samsung,timing = <1 2 3>;
  108. samsung,removable = <1>;
  109. };
  110. mmc@12230000 {
  111. status = "disabled";
  112. };
  113. fimdm0_sysmmu@0x14640000 {
  114. compatible = "samsung,sysmmu-v3.3";
  115. reg = <0x14640000 0x100>;
  116. };
  117. fimdm1_sysmmu@0x14680000 {
  118. compatible = "samsung,sysmmu-v3.3";
  119. reg = <0x14680000 0x100>;
  120. };
  121. pinctrl_0: pinctrl@13400000 {
  122. compatible = "samsung,exynos5420-pinctrl";
  123. reg = <0x13400000 0x1000>;
  124. interrupts = <0 45 0>;
  125. wakeup-interrupt-controller {
  126. compatible = "samsung,exynos4210-wakeup-eint";
  127. interrupt-parent = <&gic>;
  128. interrupts = <0 32 0>;
  129. };
  130. };
  131. pinctrl_1: pinctrl@13410000 {
  132. compatible = "samsung,exynos5420-pinctrl";
  133. reg = <0x13410000 0x1000>;
  134. interrupts = <0 78 0>;
  135. };
  136. pinctrl_2: pinctrl@14000000 {
  137. compatible = "samsung,exynos5420-pinctrl";
  138. reg = <0x14000000 0x1000>;
  139. interrupts = <0 46 0>;
  140. };
  141. pinctrl_3: pinctrl@14010000 {
  142. compatible = "samsung,exynos5420-pinctrl";
  143. reg = <0x14010000 0x1000>;
  144. interrupts = <0 50 0>;
  145. };
  146. pinctrl_4: pinctrl@03860000 {
  147. compatible = "samsung,exynos5420-pinctrl";
  148. reg = <0x03860000 0x1000>;
  149. interrupts = <0 47 0>;
  150. };
  151. fimd@14400000 {
  152. /* sysmmu is not used in U-Boot */
  153. samsung,disable-sysmmu;
  154. samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
  155. };
  156. dp: dp@145b0000 {
  157. samsung,lt-status = <0>;
  158. samsung,master-mode = <0>;
  159. samsung,bist-mode = <0>;
  160. samsung,bist-pattern = <0>;
  161. samsung,h-sync-polarity = <0>;
  162. samsung,v-sync-polarity = <0>;
  163. samsung,interlaced = <0>;
  164. samsung,color-space = <0>;
  165. samsung,dynamic-range = <0>;
  166. samsung,ycbcr-coeff = <0>;
  167. samsung,color-depth = <1>;
  168. };
  169. dmc {
  170. mem-type = "ddr3";
  171. };
  172. pwm: pwm@12dd0000 {
  173. compatible = "samsung,exynos4210-pwm";
  174. reg = <0x12dd0000 0x100>;
  175. samsung,pwm-outputs = <0>, <1>, <2>, <3>;
  176. #pwm-cells = <3>;
  177. };
  178. xhci1: xhci@12400000 {
  179. compatible = "samsung,exynos5250-xhci";
  180. reg = <0x12400000 0x10000>;
  181. #address-cells = <1>;
  182. #size-cells = <1>;
  183. phy {
  184. compatible = "samsung,exynos5250-usb3-phy";
  185. reg = <0x12500000 0x100>;
  186. };
  187. };
  188. };