exynos4x12.dtsi 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115
  1. /*
  2. * Samsung's Exynos4x12 SoCs device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
  8. * based board files can include this file and provide values for board specfic
  9. * bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13. * nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. ` * published by the Free Software Foundation.
  18. */
  19. #include "exynos4.dtsi"
  20. #include "exynos4x12-pinctrl.dtsi"
  21. #include "exynos4x12-pinctrl-uboot.dtsi"
  22. / {
  23. aliases {
  24. pinctrl0 = &pinctrl_0;
  25. pinctrl1 = &pinctrl_1;
  26. pinctrl2 = &pinctrl_2;
  27. pinctrl3 = &pinctrl_3;
  28. mshc0 = &mshc_0;
  29. };
  30. pd_isp: isp-power-domain@10023CA0 {
  31. compatible = "samsung,exynos4210-pd";
  32. reg = <0x10023CA0 0x20>;
  33. };
  34. clock: clock-controller@10030000 {
  35. compatible = "samsung,exynos4412-clock";
  36. reg = <0x10030000 0x20000>;
  37. #clock-cells = <1>;
  38. };
  39. mct@10050000 {
  40. compatible = "samsung,exynos4412-mct";
  41. reg = <0x10050000 0x800>;
  42. interrupt-parent = <&mct_map>;
  43. interrupts = <0>, <1>, <2>, <3>, <4>;
  44. clocks = <&clock 3>, <&clock 344>;
  45. clock-names = "fin_pll", "mct";
  46. mct_map: mct-map {
  47. #interrupt-cells = <1>;
  48. #address-cells = <0>;
  49. #size-cells = <0>;
  50. interrupt-map = <0 &gic 0 57 0>,
  51. <1 &combiner 12 5>,
  52. <2 &combiner 12 6>,
  53. <3 &combiner 12 7>,
  54. <4 &gic 1 12 0>;
  55. };
  56. };
  57. pinctrl_0: pinctrl@11400000 {
  58. compatible = "samsung,exynos4x12-pinctrl";
  59. reg = <0x11400000 0x1000>;
  60. interrupts = <0 47 0>;
  61. };
  62. pinctrl_1: pinctrl@11000000 {
  63. compatible = "samsung,exynos4x12-pinctrl";
  64. reg = <0x11000000 0x1000>;
  65. interrupts = <0 46 0>;
  66. wakup_eint: wakeup-interrupt-controller {
  67. compatible = "samsung,exynos4210-wakeup-eint";
  68. interrupt-parent = <&gic>;
  69. interrupts = <0 32 0>;
  70. };
  71. };
  72. pinctrl_2: pinctrl@03860000 {
  73. compatible = "samsung,exynos4x12-pinctrl";
  74. reg = <0x03860000 0x1000>;
  75. interrupt-parent = <&combiner>;
  76. interrupts = <10 0>;
  77. };
  78. pinctrl_3: pinctrl@106E0000 {
  79. compatible = "samsung,exynos4x12-pinctrl";
  80. reg = <0x106E0000 0x1000>;
  81. interrupts = <0 72 0>;
  82. };
  83. g2d@10800000 {
  84. compatible = "samsung,exynos4212-g2d";
  85. reg = <0x10800000 0x1000>;
  86. interrupts = <0 89 0>;
  87. clocks = <&clock 177>, <&clock 277>;
  88. clock-names = "sclk_fimg2d", "fimg2d";
  89. status = "disabled";
  90. };
  91. mshc_0: mmc@12550000 {
  92. compatible = "samsung,exynos4412-dw-mshc";
  93. reg = <0x12550000 0x1000>;
  94. interrupts = <0 77 0>;
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. fifo-depth = <0x80>;
  98. clocks = <&clock 301>, <&clock 149>;
  99. clock-names = "biu", "ciu";
  100. status = "disabled";
  101. };
  102. };