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SoftwareDesign
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csu3_am335x
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شاخه: master
شاخه‌ها تگ‌ها
csu3_am335x
/
board-support
/
u-boot-2017.01+gitAUTOINC+340fb36f04-g340fb36f04
/
arch
/
arm
/
dts
/
dra72-evm-revc.dts

dra72-evm-revc.dts 15 KB
لینک دائمی تاريخچه خام

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  1. /*
    2. 

  2.  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 as
    6. 

  6.  * published by the Free Software Foundation.
    7. 

  7.  */
    8. 

  8. #include "dra72-evm-common.dtsi"
    9. 

  9. #include <dt-bindings/net/ti-dp83867.h>
    10. 

  10. 

  11. / {
    12. 

  12. 	model = "TI DRA722 Rev C EVM";
    13. 

  13. 

  14. 	memory@0 {
    15. 

  15. 		device_type = "memory";
    16. 

  16. 		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
    17. 

  17. 	};
    18. 

  18. };
    19. 

  19. 

  20. &i2c1 {
    21. 

  21. 	tps65917: tps65917@58 {
    22. 

  22. 		reg = <0x58>;
    23. 

  23. 

  24. 		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
    25. 

  25. 	};
    26. 

  26. };
    27. 

  27. 

  28. #include "dra72-evm-tps65917.dtsi"
    29. 

  29. 

  30. &dra7_pmx_core {
    31. 

  31. 	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
    32. 

  32. 		pinctrl-single,pins = <
    33. 

  33. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    34. 

  34. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    35. 

  35. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    36. 

  36. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    37. 

  37. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    38. 

  38. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    39. 

  39. 		>;
    40. 

  40. 	};
    41. 

  41. 

  42. 	mmc1_pins_hs: mmc1_pins_hs {
    43. 

  43. 		pinctrl-single,pins = <
    44. 

  44. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
    45. 

  45. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
    46. 

  46. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
    47. 

  47. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
    48. 

  48. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
    49. 

  49. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
    50. 

  50. 		>;
    51. 

  51. 	};
    52. 

  52. 

  53. 	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
    54. 

  54. 		pinctrl-single,pins = <
    55. 

  55. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    56. 

  56. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    57. 

  57. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    58. 

  58. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    59. 

  59. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    60. 

  60. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    61. 

  61. 		>;
    62. 

  62. 	};
    63. 

  63. 

  64. 	mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
    65. 

  65. 		pinctrl-single,pins = <
    66. 

  66. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_clk.clk */
    67. 

  67. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_cmd.cmd */
    68. 

  68. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    69. 

  69. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    70. 

  70. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    71. 

  71. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    72. 

  72. 		>;
    73. 

  73. 	};
    74. 

  74. 

  75. 	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
    76. 

  76. 		pinctrl-single,pins = <
    77. 

  77. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
    78. 

  78. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
    79. 

  79. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
    80. 

  80. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
    81. 

  81. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
    82. 

  82. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
    83. 

  83. 		>;
    84. 

  84. 	};
    85. 

  85. 

  86. 	mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
    87. 

  87. 		pinctrl-single,pins = <
    88. 

  88. 			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
    89. 

  89. 			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
    90. 

  90. 			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
    91. 

  91. 			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
    92. 

  92. 			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
    93. 

  93. 			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
    94. 

  94. 		>;
    95. 

  95. 	};
    96. 

  96. 

  97. 	mmc2_pins_default: mmc2_pins_default {
    98. 

  98. 		pinctrl-single,pins = <
    99. 

  99. 			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    100. 

  100. 			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    101. 

  101. 			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    102. 

  102. 			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    103. 

  103. 			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    104. 

  104. 			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    105. 

  105. 			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    106. 

  106. 			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    107. 

  107. 			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    108. 

  108. 			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    109. 

  109. 		>;
    110. 

  110. 	};
    111. 

  111. 

  112. 	mmc2_pins_hs: mmc2_pins_hs {
    113. 

  113. 		pinctrl-single,pins = <
    114. 

  114. 			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    115. 

  115. 			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    116. 

  116. 			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    117. 

  117. 			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    118. 

  118. 			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    119. 

  119. 			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    120. 

  120. 			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    121. 

  121. 			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    122. 

  122. 			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    123. 

  123. 			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    124. 

  124. 		>;
    125. 

  125. 	};
    126. 

  126. 

  127. 	mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
    128. 

  128. 		pinctrl-single,pins = <
    129. 

  129. 			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    130. 

  130. 			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    131. 

  131. 			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    132. 

  132. 			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    133. 

  133. 			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    134. 

  134. 			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    135. 

  135. 			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    136. 

  136. 			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    137. 

  137. 			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    138. 

  138. 			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    139. 

  139. 		>;
    140. 

  140. 	};
    141. 

  141. 

  142. 	mmc2_pins_hs200_1_8v: mmc2_pins_hs200_1_8v {
    143. 

  143. 		pinctrl-single,pins = <
    144. 

  144. 			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    145. 

  145. 			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    146. 

  146. 			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    147. 

  147. 			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    148. 

  148. 			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    149. 

  149. 			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    150. 

  150. 			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    151. 

  151. 			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    152. 

  152. 			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    153. 

  153. 			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    154. 

  154. 		>;
    155. 

  155. 	};
    156. 

  156. };
    157. 

  157. 

  158. &dra7_iodelay_core {
    159. 

  159. 	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
    160. 

  160. 		pinctrl-pin-array = <
    161. 

  161. 			0x618 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CLK_IN */
    162. 

  162. 			0x624 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_IN */
    163. 

  163. 			0x630 A_DELAY_PS(495) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_IN */
    164. 

  164. 			0x63C A_DELAY_PS(116) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_IN */
    165. 

  165. 			0x648 A_DELAY_PS(117) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_IN */
    166. 

  166. 			0x654 A_DELAY_PS(32) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_IN */
    167. 

  167. 			0x620 A_DELAY_PS(1224) G_DELAY_PS(0)	/* CFG_MMC1_CLK_OUT */
    168. 

  168. 			0x62C A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OUT */
    169. 

  169. 			0x638 A_DELAY_PS(44) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
    170. 

  170. 			0x644 A_DELAY_PS(64) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
    171. 

  171. 			0x650 A_DELAY_PS(79) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
    172. 

  172. 			0x65C A_DELAY_PS(87) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
    173. 

  173. 			0x628 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
    174. 

  174. 			0x634 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OEN */
    175. 

  175. 			0x640 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
    176. 

  176. 			0x64C A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
    177. 

  177. 			0x658 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
    178. 

  178. 		>;
    179. 

  179. 	};
    180. 

  180. 

  181. 	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
    182. 

  182. 		pinctrl-pin-array = <
    183. 

  183. 			0x620 A_DELAY_PS(520) G_DELAY_PS(320)	/* CFG_MMC1_CLK_OUT */
    184. 

  184. 			0x62c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OUT */
    185. 

  185. 			0x638 A_DELAY_PS(40) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
    186. 

  186. 			0x644 A_DELAY_PS(83) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
    187. 

  187. 			0x650 A_DELAY_PS(98) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
    188. 

  188. 			0x65c A_DELAY_PS(106) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
    189. 

  189. 			0x628 A_DELAY_PS(51) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
    190. 

  190. 			0x634 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OEN */
    191. 

  191. 			0x640 A_DELAY_PS(363) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
    192. 

  192. 			0x64c A_DELAY_PS(199) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
    193. 

  193. 			0x658 A_DELAY_PS(273) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
    194. 

  194. 		>;
    195. 

  195. 	};
    196. 

  196. 

  197. 	mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
    198. 

  198. 		pinctrl-pin-array = <
    199. 

  199. 			0x18c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_IN */
    200. 

  200. 			0x1a4 A_DELAY_PS(121) G_DELAY_PS(0)	/* CFG_GPMC_A20_IN */
    201. 

  201. 			0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A21_IN */
    202. 

  202. 			0x1bc A_DELAY_PS(20) G_DELAY_PS(0)	/* CFG_GPMC_A22_IN */
    203. 

  203. 			0x1c8 A_DELAY_PS(108) G_DELAY_PS(0)	/* CFG_GPMC_A23_IN */
    204. 

  204. 			0x1d4 A_DELAY_PS(31) G_DELAY_PS(0)	/* CFG_GPMC_A24_IN */
    205. 

  205. 			0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_IN */
    206. 

  206. 			0x1ec A_DELAY_PS(24) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
    207. 

  207. 			0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_IN */
    208. 

  208. 			0x360 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_IN */
    209. 

  209. 			0x194 A_DELAY_PS(152) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
    210. 

  210. 			0x1ac A_DELAY_PS(206) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
    211. 

  211. 			0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
    212. 

  212. 			0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)	/* CFG_GPMC_A22_OUT */
    213. 

  213. 			0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)	/* CFG_GPMC_A23_OUT */
    214. 

  214. 			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OUT */
    215. 

  215. 			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OUT */
    216. 

  216. 			0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
    217. 

  217. 			0x200 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OUT */
    218. 

  218. 			0x368 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OUT */
    219. 

  219. 			0x190 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_OEN */
    220. 

  220. 			0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A20_OEN */
    221. 

  221. 			0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A21_OEN */
    222. 

  222. 			0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A22_OEN */
    223. 

  223. 			0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OEN */
    224. 

  224. 			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OEN */
    225. 

  225. 			0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A26_OEN */
    226. 

  226. 			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OEN */
    227. 

  227. 			0x364 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OEN */
    228. 

  228. 		>;
    229. 

  229. 	};
    230. 

  230. 

  231. 	mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf {
    232. 

  232. 		pinctrl-pin-array = <
    233. 

  233. 			0x194 A_DELAY_PS(135) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
    234. 

  234. 			0x1ac A_DELAY_PS(189) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
    235. 

  235. 			0x1b8 A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_A21_OUT */
    236. 

  236. 			0x1c4 A_DELAY_PS(0) G_DELAY_PS(70)	/* CFG_GPMC_A22_OUT */
    237. 

  237. 			0x1d0 A_DELAY_PS(730) G_DELAY_PS(360)	/* CFG_GPMC_A23_OUT */
    238. 

  238. 			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OUT */
    239. 

  239. 			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OUT */
    240. 

  240. 			0x1f4 A_DELAY_PS(70) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
    241. 

  241. 			0x200 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OUT */
    242. 

  242. 			0x368 A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_CS1_OUT */
    243. 

  243. 			0x190 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_OEN */
    244. 

  244. 			0x1a8 A_DELAY_PS(231) G_DELAY_PS(0)	/* CFG_GPMC_A20_OEN */
    245. 

  245. 			0x1b4 A_DELAY_PS(39) G_DELAY_PS(0)	/* CFG_GPMC_A21_OEN */
    246. 

  246. 			0x1c0 A_DELAY_PS(91) G_DELAY_PS(0)	/* CFG_GPMC_A22_OEN */
    247. 

  247. 			0x1d8 A_DELAY_PS(176) G_DELAY_PS(0)	/* CFG_GPMC_A24_OEN */
    248. 

  248. 			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OEN */
    249. 

  249. 			0x1f0 A_DELAY_PS(101) G_DELAY_PS(0)	/* CFG_GPMC_A26_OEN */
    250. 

  250. 			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OEN */
    251. 

  251. 			0x364 A_DELAY_PS(360) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OEN */
    252. 

  252. 		>;
    253. 

  253. 	};
    254. 

  254. };
    255. 

  255. 

  256. &ldo2_reg {
    257. 

  257. 	/* LDO2_OUT --> VDDA_1V8_PHY2 */
    258. 

  258. 	regulator-always-on;
    259. 

  259. 	regulator-boot-on;
    260. 

  260. };
    261. 

  261. 

  262. &hdmi {
    263. 

  263. 	vdda-supply = <&ldo2_reg>;
    264. 

  264. };
    265. 

  265. 

  266. &pcf_gpio_21 {
    267. 

  267. 	interrupt-parent = <&gpio3>;
    268. 

  268. 	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
    269. 

  269. };
    270. 

  270. 

  271. &mac {
    272. 

  272. 	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
    273. 

  273. 		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
    274. 

  274. 		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
    275. 

  275. 	dual_emac;
    276. 

  276. };
    277. 

  277. 

  278. &cpsw_emac0 {
    279. 

  279. 	phy-handle = <&dp83867_0>;
    280. 

  280. 	phy-mode = "rgmii-id";
    281. 

  281. 	dual_emac_res_vlan = <1>;
    282. 

  282. };
    283. 

  283. 

  284. &cpsw_emac1 {
    285. 

  285. 	phy-handle = <&dp83867_1>;
    286. 

  286. 	phy-mode = "rgmii-id";
    287. 

  287. 	dual_emac_res_vlan = <2>;
    288. 

  288. };
    289. 

  289. 

  290. &davinci_mdio {
    291. 

  291. 	dp83867_0: ethernet-phy@2 {
    292. 

  292. 		reg = <2>;
    293. 

  293. 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
    294. 

  294. 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
    295. 

  295. 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
    296. 

  296. 		ti,min-output-impedance;
    297. 

  297. 	};
    298. 

  298. 

  299. 	dp83867_1: ethernet-phy@3 {
    300. 

  300. 		reg = <3>;
    301. 

  301. 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
    302. 

  302. 		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
    303. 

  303. 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
    304. 

  304. 		ti,min-output-impedance;
    305. 

  305. 	};
    306. 

  306. };
    307. 

  307. 

  308. &mmc1 {
    309. 

  309. 	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
    310. 

  310. 	pinctrl-0 = <&mmc1_pins_default>;
    311. 

  311. 	pinctrl-1 = <&mmc1_pins_hs>;
    312. 

  312. 	pinctrl-2 = <&mmc1_pins_sdr12>;
    313. 

  313. 	pinctrl-3 = <&mmc1_pins_sdr25>;
    314. 

  314. 	pinctrl-4 = <&mmc1_pins_sdr50>;
    315. 

  315. 	pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
    316. 

  316. 	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;
    317. 

  317. 	vmmc_aux-supply = <&ldo1_reg>;
    318. 

  318. };
    319. 

  319. 

  320. &mmc2 {
    321. 

  321. 	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
    322. 

  322. 	pinctrl-0 = <&mmc2_pins_default>;
    323. 

  323. 	pinctrl-1 = <&mmc2_pins_hs>;
    324. 

  324. 	pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
    325. 

  325. 	pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;
    326. 

  326. };
    327.