at91sam9g45.dtsi 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335
  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/dma/at91.h>
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include <dt-bindings/clock/at91.h>
  17. / {
  18. model = "Atmel AT91SAM9G45 family SoC";
  19. compatible = "atmel,at91sam9g45";
  20. interrupt-parent = <&aic>;
  21. aliases {
  22. serial0 = &dbgu;
  23. serial1 = &usart0;
  24. serial2 = &usart1;
  25. serial3 = &usart2;
  26. serial4 = &usart3;
  27. gpio0 = &pioA;
  28. gpio1 = &pioB;
  29. gpio2 = &pioC;
  30. gpio3 = &pioD;
  31. gpio4 = &pioE;
  32. tcb0 = &tcb0;
  33. tcb1 = &tcb1;
  34. i2c0 = &i2c0;
  35. i2c1 = &i2c1;
  36. ssc0 = &ssc0;
  37. ssc1 = &ssc1;
  38. pwm0 = &pwm0;
  39. };
  40. cpus {
  41. #address-cells = <0>;
  42. #size-cells = <0>;
  43. cpu {
  44. compatible = "arm,arm926ej-s";
  45. device_type = "cpu";
  46. };
  47. };
  48. memory {
  49. reg = <0x70000000 0x10000000>;
  50. };
  51. clocks {
  52. slow_xtal: slow_xtal {
  53. compatible = "fixed-clock";
  54. #clock-cells = <0>;
  55. clock-frequency = <0>;
  56. };
  57. main_xtal: main_xtal {
  58. compatible = "fixed-clock";
  59. #clock-cells = <0>;
  60. clock-frequency = <0>;
  61. };
  62. adc_op_clk: adc_op_clk{
  63. compatible = "fixed-clock";
  64. #clock-cells = <0>;
  65. clock-frequency = <300000>;
  66. };
  67. };
  68. sram: sram@00300000 {
  69. compatible = "mmio-sram";
  70. reg = <0x00300000 0x10000>;
  71. };
  72. ahb {
  73. compatible = "simple-bus";
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. ranges;
  77. apb {
  78. compatible = "simple-bus";
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. ranges;
  82. aic: interrupt-controller@fffff000 {
  83. #interrupt-cells = <3>;
  84. compatible = "atmel,at91rm9200-aic";
  85. interrupt-controller;
  86. reg = <0xfffff000 0x200>;
  87. atmel,external-irqs = <31>;
  88. };
  89. ramc0: ramc@ffffe400 {
  90. compatible = "atmel,at91sam9g45-ddramc";
  91. reg = <0xffffe400 0x200>;
  92. clocks = <&ddrck>;
  93. clock-names = "ddrck";
  94. };
  95. ramc1: ramc@ffffe600 {
  96. compatible = "atmel,at91sam9g45-ddramc";
  97. reg = <0xffffe600 0x200>;
  98. clocks = <&ddrck>;
  99. clock-names = "ddrck";
  100. };
  101. pmc: pmc@fffffc00 {
  102. compatible = "atmel,at91sam9g45-pmc", "syscon";
  103. reg = <0xfffffc00 0x100>;
  104. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  105. interrupt-controller;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. #interrupt-cells = <1>;
  109. main_osc: main_osc {
  110. compatible = "atmel,at91rm9200-clk-main-osc";
  111. #clock-cells = <0>;
  112. interrupts-extended = <&pmc AT91_PMC_MOSCS>;
  113. clocks = <&main_xtal>;
  114. };
  115. main: mainck {
  116. compatible = "atmel,at91rm9200-clk-main";
  117. #clock-cells = <0>;
  118. clocks = <&main_osc>;
  119. };
  120. plla: pllack {
  121. compatible = "atmel,at91rm9200-clk-pll";
  122. #clock-cells = <0>;
  123. interrupts-extended = <&pmc AT91_PMC_LOCKA>;
  124. clocks = <&main>;
  125. reg = <0>;
  126. atmel,clk-input-range = <2000000 32000000>;
  127. #atmel,pll-clk-output-range-cells = <4>;
  128. atmel,pll-clk-output-ranges = <745000000 800000000 0 0
  129. 695000000 750000000 1 0
  130. 645000000 700000000 2 0
  131. 595000000 650000000 3 0
  132. 545000000 600000000 0 1
  133. 495000000 555000000 1 1
  134. 445000000 500000000 2 1
  135. 400000000 450000000 3 1>;
  136. };
  137. plladiv: plladivck {
  138. compatible = "atmel,at91sam9x5-clk-plldiv";
  139. #clock-cells = <0>;
  140. clocks = <&plla>;
  141. };
  142. utmi: utmick {
  143. compatible = "atmel,at91sam9x5-clk-utmi";
  144. #clock-cells = <0>;
  145. interrupts-extended = <&pmc AT91_PMC_LOCKU>;
  146. clocks = <&main>;
  147. };
  148. mck: masterck {
  149. compatible = "atmel,at91rm9200-clk-master";
  150. #clock-cells = <0>;
  151. interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
  152. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
  153. atmel,clk-output-range = <0 133333333>;
  154. atmel,clk-divisors = <1 2 4 3>;
  155. };
  156. usb: usbck {
  157. compatible = "atmel,at91sam9x5-clk-usb";
  158. #clock-cells = <0>;
  159. clocks = <&plladiv>, <&utmi>;
  160. };
  161. prog: progck {
  162. compatible = "atmel,at91sam9g45-clk-programmable";
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. interrupt-parent = <&pmc>;
  166. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
  167. prog0: prog0 {
  168. #clock-cells = <0>;
  169. reg = <0>;
  170. interrupts = <AT91_PMC_PCKRDY(0)>;
  171. };
  172. prog1: prog1 {
  173. #clock-cells = <0>;
  174. reg = <1>;
  175. interrupts = <AT91_PMC_PCKRDY(1)>;
  176. };
  177. };
  178. systemck {
  179. compatible = "atmel,at91rm9200-clk-system";
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. ddrck: ddrck {
  183. #clock-cells = <0>;
  184. reg = <2>;
  185. clocks = <&mck>;
  186. };
  187. uhpck: uhpck {
  188. #clock-cells = <0>;
  189. reg = <6>;
  190. clocks = <&usb>;
  191. };
  192. pck0: pck0 {
  193. #clock-cells = <0>;
  194. reg = <8>;
  195. clocks = <&prog0>;
  196. };
  197. pck1: pck1 {
  198. #clock-cells = <0>;
  199. reg = <9>;
  200. clocks = <&prog1>;
  201. };
  202. };
  203. periphck {
  204. compatible = "atmel,at91rm9200-clk-peripheral";
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. clocks = <&mck>;
  208. pioA_clk: pioA_clk {
  209. #clock-cells = <0>;
  210. reg = <2>;
  211. };
  212. pioB_clk: pioB_clk {
  213. #clock-cells = <0>;
  214. reg = <3>;
  215. };
  216. pioC_clk: pioC_clk {
  217. #clock-cells = <0>;
  218. reg = <4>;
  219. };
  220. pioDE_clk: pioDE_clk {
  221. #clock-cells = <0>;
  222. reg = <5>;
  223. };
  224. trng_clk: trng_clk {
  225. #clock-cells = <0>;
  226. reg = <6>;
  227. };
  228. usart0_clk: usart0_clk {
  229. #clock-cells = <0>;
  230. reg = <7>;
  231. };
  232. usart1_clk: usart1_clk {
  233. #clock-cells = <0>;
  234. reg = <8>;
  235. };
  236. usart2_clk: usart2_clk {
  237. #clock-cells = <0>;
  238. reg = <9>;
  239. };
  240. usart3_clk: usart3_clk {
  241. #clock-cells = <0>;
  242. reg = <10>;
  243. };
  244. mci0_clk: mci0_clk {
  245. #clock-cells = <0>;
  246. reg = <11>;
  247. };
  248. twi0_clk: twi0_clk {
  249. #clock-cells = <0>;
  250. reg = <12>;
  251. };
  252. twi1_clk: twi1_clk {
  253. #clock-cells = <0>;
  254. reg = <13>;
  255. };
  256. spi0_clk: spi0_clk {
  257. #clock-cells = <0>;
  258. reg = <14>;
  259. };
  260. spi1_clk: spi1_clk {
  261. #clock-cells = <0>;
  262. reg = <15>;
  263. };
  264. ssc0_clk: ssc0_clk {
  265. #clock-cells = <0>;
  266. reg = <16>;
  267. };
  268. ssc1_clk: ssc1_clk {
  269. #clock-cells = <0>;
  270. reg = <17>;
  271. };
  272. tcb0_clk: tcb0_clk {
  273. #clock-cells = <0>;
  274. reg = <18>;
  275. };
  276. pwm_clk: pwm_clk {
  277. #clock-cells = <0>;
  278. reg = <19>;
  279. };
  280. adc_clk: adc_clk {
  281. #clock-cells = <0>;
  282. reg = <20>;
  283. };
  284. dma0_clk: dma0_clk {
  285. #clock-cells = <0>;
  286. reg = <21>;
  287. };
  288. uhphs_clk: uhphs_clk {
  289. #clock-cells = <0>;
  290. reg = <22>;
  291. };
  292. lcd_clk: lcd_clk {
  293. #clock-cells = <0>;
  294. reg = <23>;
  295. };
  296. ac97_clk: ac97_clk {
  297. #clock-cells = <0>;
  298. reg = <24>;
  299. };
  300. macb0_clk: macb0_clk {
  301. #clock-cells = <0>;
  302. reg = <25>;
  303. };
  304. isi_clk: isi_clk {
  305. #clock-cells = <0>;
  306. reg = <26>;
  307. };
  308. udphs_clk: udphs_clk {
  309. #clock-cells = <0>;
  310. reg = <27>;
  311. };
  312. aestdessha_clk: aestdessha_clk {
  313. #clock-cells = <0>;
  314. reg = <28>;
  315. };
  316. mci1_clk: mci1_clk {
  317. #clock-cells = <0>;
  318. reg = <29>;
  319. };
  320. vdec_clk: vdec_clk {
  321. #clock-cells = <0>;
  322. reg = <30>;
  323. };
  324. };
  325. };
  326. rstc@fffffd00 {
  327. compatible = "atmel,at91sam9g45-rstc";
  328. reg = <0xfffffd00 0x10>;
  329. clocks = <&clk32k>;
  330. };
  331. pit: timer@fffffd30 {
  332. compatible = "atmel,at91sam9260-pit";
  333. reg = <0xfffffd30 0xf>;
  334. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  335. clocks = <&mck>;
  336. };
  337. shdwc@fffffd10 {
  338. compatible = "atmel,at91sam9rl-shdwc";
  339. reg = <0xfffffd10 0x10>;
  340. clocks = <&clk32k>;
  341. };
  342. tcb0: timer@fff7c000 {
  343. compatible = "atmel,at91rm9200-tcb";
  344. reg = <0xfff7c000 0x100>;
  345. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  346. clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
  347. clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
  348. };
  349. tcb1: timer@fffd4000 {
  350. compatible = "atmel,at91rm9200-tcb";
  351. reg = <0xfffd4000 0x100>;
  352. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  353. clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
  354. clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
  355. };
  356. dma: dma-controller@ffffec00 {
  357. compatible = "atmel,at91sam9g45-dma";
  358. reg = <0xffffec00 0x200>;
  359. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  360. #dma-cells = <2>;
  361. clocks = <&dma0_clk>;
  362. clock-names = "dma_clk";
  363. };
  364. pinctrl@fffff200 {
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  368. ranges = <0xfffff200 0xfffff200 0xa00>;
  369. atmel,mux-mask = <
  370. /* A B */
  371. 0xffffffff 0xffc003ff /* pioA */
  372. 0xffffffff 0x800f8f00 /* pioB */
  373. 0xffffffff 0x00000e00 /* pioC */
  374. 0xffffffff 0xff0c1381 /* pioD */
  375. 0xffffffff 0x81ffff81 /* pioE */
  376. >;
  377. /* shared pinctrl settings */
  378. adc0 {
  379. pinctrl_adc0_adtrg: adc0_adtrg {
  380. atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  381. };
  382. pinctrl_adc0_ad0: adc0_ad0 {
  383. atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  384. };
  385. pinctrl_adc0_ad1: adc0_ad1 {
  386. atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  387. };
  388. pinctrl_adc0_ad2: adc0_ad2 {
  389. atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  390. };
  391. pinctrl_adc0_ad3: adc0_ad3 {
  392. atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  393. };
  394. pinctrl_adc0_ad4: adc0_ad4 {
  395. atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  396. };
  397. pinctrl_adc0_ad5: adc0_ad5 {
  398. atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  399. };
  400. pinctrl_adc0_ad6: adc0_ad6 {
  401. atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  402. };
  403. pinctrl_adc0_ad7: adc0_ad7 {
  404. atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
  405. };
  406. };
  407. dbgu {
  408. pinctrl_dbgu: dbgu-0 {
  409. atmel,pins =
  410. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  411. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  412. };
  413. };
  414. i2c0 {
  415. pinctrl_i2c0: i2c0-0 {
  416. atmel,pins =
  417. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
  418. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
  419. };
  420. };
  421. i2c1 {
  422. pinctrl_i2c1: i2c1-0 {
  423. atmel,pins =
  424. <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
  425. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
  426. };
  427. };
  428. isi {
  429. pinctrl_isi_data_0_7: isi-0-data-0-7 {
  430. atmel,pins =
  431. <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
  432. AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
  433. AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
  434. AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
  435. AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
  436. AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
  437. AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
  438. AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
  439. AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
  440. AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
  441. AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
  442. };
  443. pinctrl_isi_data_8_9: isi-0-data-8-9 {
  444. atmel,pins =
  445. <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
  446. AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
  447. };
  448. pinctrl_isi_data_10_11: isi-0-data-10-11 {
  449. atmel,pins =
  450. <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
  451. AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
  452. };
  453. };
  454. usart0 {
  455. pinctrl_usart0: usart0-0 {
  456. atmel,pins =
  457. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
  458. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  459. };
  460. pinctrl_usart0_rts: usart0_rts-0 {
  461. atmel,pins =
  462. <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
  463. };
  464. pinctrl_usart0_cts: usart0_cts-0 {
  465. atmel,pins =
  466. <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
  467. };
  468. };
  469. uart1 {
  470. pinctrl_usart1: usart1-0 {
  471. atmel,pins =
  472. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
  473. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  474. };
  475. pinctrl_usart1_rts: usart1_rts-0 {
  476. atmel,pins =
  477. <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
  478. };
  479. pinctrl_usart1_cts: usart1_cts-0 {
  480. atmel,pins =
  481. <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
  482. };
  483. };
  484. usart2 {
  485. pinctrl_usart2: usart2-0 {
  486. atmel,pins =
  487. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  488. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  489. };
  490. pinctrl_usart2_rts: usart2_rts-0 {
  491. atmel,pins =
  492. <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
  493. };
  494. pinctrl_usart2_cts: usart2_cts-0 {
  495. atmel,pins =
  496. <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
  497. };
  498. };
  499. usart3 {
  500. pinctrl_usart3: usart3-0 {
  501. atmel,pins =
  502. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
  503. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  504. };
  505. pinctrl_usart3_rts: usart3_rts-0 {
  506. atmel,pins =
  507. <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
  508. };
  509. pinctrl_usart3_cts: usart3_cts-0 {
  510. atmel,pins =
  511. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
  512. };
  513. };
  514. nand {
  515. pinctrl_nand: nand-0 {
  516. atmel,pins =
  517. <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
  518. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  519. };
  520. };
  521. macb {
  522. pinctrl_macb_rmii: macb_rmii-0 {
  523. atmel,pins =
  524. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  525. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  526. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  527. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  528. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  529. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  530. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  531. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  532. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  533. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
  534. };
  535. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  536. atmel,pins =
  537. <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
  538. AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
  539. AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
  540. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
  541. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  542. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  543. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
  544. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  545. };
  546. };
  547. mmc0 {
  548. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  549. atmel,pins =
  550. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
  551. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  552. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
  553. };
  554. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  555. atmel,pins =
  556. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  557. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  558. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  559. };
  560. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  561. atmel,pins =
  562. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  563. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  564. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  565. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
  566. };
  567. };
  568. mmc1 {
  569. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  570. atmel,pins =
  571. <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
  572. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
  573. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  574. };
  575. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  576. atmel,pins =
  577. <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  578. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
  579. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
  580. };
  581. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  582. atmel,pins =
  583. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
  584. AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  585. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
  586. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
  587. };
  588. };
  589. ssc0 {
  590. pinctrl_ssc0_tx: ssc0_tx-0 {
  591. atmel,pins =
  592. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
  593. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
  594. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
  595. };
  596. pinctrl_ssc0_rx: ssc0_rx-0 {
  597. atmel,pins =
  598. <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
  599. AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
  600. AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
  601. };
  602. };
  603. ssc1 {
  604. pinctrl_ssc1_tx: ssc1_tx-0 {
  605. atmel,pins =
  606. <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
  607. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
  608. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
  609. };
  610. pinctrl_ssc1_rx: ssc1_rx-0 {
  611. atmel,pins =
  612. <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
  613. AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
  614. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
  615. };
  616. };
  617. spi0 {
  618. pinctrl_spi0: spi0-0 {
  619. atmel,pins =
  620. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
  621. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
  622. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
  623. };
  624. };
  625. spi1 {
  626. pinctrl_spi1: spi1-0 {
  627. atmel,pins =
  628. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
  629. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
  630. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
  631. };
  632. };
  633. tcb0 {
  634. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  635. atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  636. };
  637. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  638. atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  639. };
  640. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  641. atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  642. };
  643. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  644. atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  645. };
  646. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  647. atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  648. };
  649. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  650. atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  651. };
  652. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  653. atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  654. };
  655. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  656. atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  657. };
  658. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  659. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  660. };
  661. };
  662. tcb1 {
  663. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  664. atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  665. };
  666. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  667. atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  668. };
  669. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  670. atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  671. };
  672. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  673. atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  674. };
  675. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  676. atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  677. };
  678. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  679. atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  680. };
  681. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  682. atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  683. };
  684. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  685. atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  686. };
  687. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  688. atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  689. };
  690. };
  691. fb {
  692. pinctrl_fb: fb-0 {
  693. atmel,pins =
  694. <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
  695. AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
  696. AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
  697. AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
  698. AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
  699. AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
  700. AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
  701. AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
  702. AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
  703. AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
  704. AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
  705. AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
  706. AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
  707. AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
  708. AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
  709. AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
  710. AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
  711. AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
  712. AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
  713. AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
  714. AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
  715. AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
  716. AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
  717. AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
  718. AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
  719. AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
  720. AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
  721. AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
  722. AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
  723. AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
  724. };
  725. };
  726. pioA: gpio@fffff200 {
  727. compatible = "atmel,at91rm9200-gpio";
  728. reg = <0xfffff200 0x200>;
  729. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  730. #gpio-cells = <2>;
  731. gpio-controller;
  732. interrupt-controller;
  733. #interrupt-cells = <2>;
  734. clocks = <&pioA_clk>;
  735. };
  736. pioB: gpio@fffff400 {
  737. compatible = "atmel,at91rm9200-gpio";
  738. reg = <0xfffff400 0x200>;
  739. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  740. #gpio-cells = <2>;
  741. gpio-controller;
  742. interrupt-controller;
  743. #interrupt-cells = <2>;
  744. clocks = <&pioB_clk>;
  745. };
  746. pioC: gpio@fffff600 {
  747. compatible = "atmel,at91rm9200-gpio";
  748. reg = <0xfffff600 0x200>;
  749. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  750. #gpio-cells = <2>;
  751. gpio-controller;
  752. interrupt-controller;
  753. #interrupt-cells = <2>;
  754. clocks = <&pioC_clk>;
  755. };
  756. pioD: gpio@fffff800 {
  757. compatible = "atmel,at91rm9200-gpio";
  758. reg = <0xfffff800 0x200>;
  759. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  760. #gpio-cells = <2>;
  761. gpio-controller;
  762. interrupt-controller;
  763. #interrupt-cells = <2>;
  764. clocks = <&pioDE_clk>;
  765. };
  766. pioE: gpio@fffffa00 {
  767. compatible = "atmel,at91rm9200-gpio";
  768. reg = <0xfffffa00 0x200>;
  769. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  770. #gpio-cells = <2>;
  771. gpio-controller;
  772. interrupt-controller;
  773. #interrupt-cells = <2>;
  774. clocks = <&pioDE_clk>;
  775. };
  776. };
  777. dbgu: serial@ffffee00 {
  778. compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  779. reg = <0xffffee00 0x200>;
  780. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  781. pinctrl-names = "default";
  782. pinctrl-0 = <&pinctrl_dbgu>;
  783. clocks = <&mck>;
  784. clock-names = "usart";
  785. status = "disabled";
  786. };
  787. usart0: serial@fff8c000 {
  788. compatible = "atmel,at91sam9260-usart";
  789. reg = <0xfff8c000 0x200>;
  790. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  791. atmel,use-dma-rx;
  792. atmel,use-dma-tx;
  793. pinctrl-names = "default";
  794. pinctrl-0 = <&pinctrl_usart0>;
  795. clocks = <&usart0_clk>;
  796. clock-names = "usart";
  797. status = "disabled";
  798. };
  799. usart1: serial@fff90000 {
  800. compatible = "atmel,at91sam9260-usart";
  801. reg = <0xfff90000 0x200>;
  802. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  803. atmel,use-dma-rx;
  804. atmel,use-dma-tx;
  805. pinctrl-names = "default";
  806. pinctrl-0 = <&pinctrl_usart1>;
  807. clocks = <&usart1_clk>;
  808. clock-names = "usart";
  809. status = "disabled";
  810. };
  811. usart2: serial@fff94000 {
  812. compatible = "atmel,at91sam9260-usart";
  813. reg = <0xfff94000 0x200>;
  814. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  815. atmel,use-dma-rx;
  816. atmel,use-dma-tx;
  817. pinctrl-names = "default";
  818. pinctrl-0 = <&pinctrl_usart2>;
  819. clocks = <&usart2_clk>;
  820. clock-names = "usart";
  821. status = "disabled";
  822. };
  823. usart3: serial@fff98000 {
  824. compatible = "atmel,at91sam9260-usart";
  825. reg = <0xfff98000 0x200>;
  826. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
  827. atmel,use-dma-rx;
  828. atmel,use-dma-tx;
  829. pinctrl-names = "default";
  830. pinctrl-0 = <&pinctrl_usart3>;
  831. clocks = <&usart3_clk>;
  832. clock-names = "usart";
  833. status = "disabled";
  834. };
  835. macb0: ethernet@fffbc000 {
  836. compatible = "cdns,at91sam9260-macb", "cdns,macb";
  837. reg = <0xfffbc000 0x100>;
  838. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
  839. pinctrl-names = "default";
  840. pinctrl-0 = <&pinctrl_macb_rmii>;
  841. clocks = <&macb0_clk>, <&macb0_clk>;
  842. clock-names = "hclk", "pclk";
  843. status = "disabled";
  844. };
  845. trng@fffcc000 {
  846. compatible = "atmel,at91sam9g45-trng";
  847. reg = <0xfffcc000 0x4000>;
  848. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
  849. clocks = <&trng_clk>;
  850. };
  851. i2c0: i2c@fff84000 {
  852. compatible = "atmel,at91sam9g10-i2c";
  853. reg = <0xfff84000 0x100>;
  854. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
  855. pinctrl-names = "default";
  856. pinctrl-0 = <&pinctrl_i2c0>;
  857. #address-cells = <1>;
  858. #size-cells = <0>;
  859. clocks = <&twi0_clk>;
  860. status = "disabled";
  861. };
  862. i2c1: i2c@fff88000 {
  863. compatible = "atmel,at91sam9g10-i2c";
  864. reg = <0xfff88000 0x100>;
  865. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
  866. pinctrl-names = "default";
  867. pinctrl-0 = <&pinctrl_i2c1>;
  868. #address-cells = <1>;
  869. #size-cells = <0>;
  870. clocks = <&twi1_clk>;
  871. status = "disabled";
  872. };
  873. ssc0: ssc@fff9c000 {
  874. compatible = "atmel,at91sam9g45-ssc";
  875. reg = <0xfff9c000 0x4000>;
  876. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  877. pinctrl-names = "default";
  878. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  879. clocks = <&ssc0_clk>;
  880. clock-names = "pclk";
  881. status = "disabled";
  882. };
  883. ssc1: ssc@fffa0000 {
  884. compatible = "atmel,at91sam9g45-ssc";
  885. reg = <0xfffa0000 0x4000>;
  886. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
  887. pinctrl-names = "default";
  888. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  889. clocks = <&ssc1_clk>;
  890. clock-names = "pclk";
  891. status = "disabled";
  892. };
  893. adc0: adc@fffb0000 {
  894. #address-cells = <1>;
  895. #size-cells = <0>;
  896. compatible = "atmel,at91sam9g45-adc";
  897. reg = <0xfffb0000 0x100>;
  898. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  899. clocks = <&adc_clk>, <&adc_op_clk>;
  900. clock-names = "adc_clk", "adc_op_clk";
  901. atmel,adc-channels-used = <0xff>;
  902. atmel,adc-vref = <3300>;
  903. atmel,adc-startup-time = <40>;
  904. atmel,adc-res = <8 10>;
  905. atmel,adc-res-names = "lowres", "highres";
  906. atmel,adc-use-res = "highres";
  907. trigger@0 {
  908. reg = <0>;
  909. trigger-name = "external-rising";
  910. trigger-value = <0x1>;
  911. trigger-external;
  912. };
  913. trigger@1 {
  914. reg = <1>;
  915. trigger-name = "external-falling";
  916. trigger-value = <0x2>;
  917. trigger-external;
  918. };
  919. trigger@2 {
  920. reg = <2>;
  921. trigger-name = "external-any";
  922. trigger-value = <0x3>;
  923. trigger-external;
  924. };
  925. trigger@3 {
  926. reg = <3>;
  927. trigger-name = "continuous";
  928. trigger-value = <0x6>;
  929. };
  930. };
  931. isi@fffb4000 {
  932. compatible = "atmel,at91sam9g45-isi";
  933. reg = <0xfffb4000 0x4000>;
  934. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
  935. clocks = <&isi_clk>;
  936. clock-names = "isi_clk";
  937. status = "disabled";
  938. port {
  939. #address-cells = <1>;
  940. #size-cells = <0>;
  941. };
  942. };
  943. pwm0: pwm@fffb8000 {
  944. compatible = "atmel,at91sam9rl-pwm";
  945. reg = <0xfffb8000 0x300>;
  946. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
  947. #pwm-cells = <3>;
  948. clocks = <&pwm_clk>;
  949. status = "disabled";
  950. };
  951. mmc0: mmc@fff80000 {
  952. compatible = "atmel,hsmci";
  953. reg = <0xfff80000 0x600>;
  954. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  955. pinctrl-names = "default";
  956. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
  957. dma-names = "rxtx";
  958. #address-cells = <1>;
  959. #size-cells = <0>;
  960. clocks = <&mci0_clk>;
  961. clock-names = "mci_clk";
  962. status = "disabled";
  963. };
  964. mmc1: mmc@fffd0000 {
  965. compatible = "atmel,hsmci";
  966. reg = <0xfffd0000 0x600>;
  967. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
  968. pinctrl-names = "default";
  969. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
  970. dma-names = "rxtx";
  971. #address-cells = <1>;
  972. #size-cells = <0>;
  973. clocks = <&mci1_clk>;
  974. clock-names = "mci_clk";
  975. status = "disabled";
  976. };
  977. watchdog@fffffd40 {
  978. compatible = "atmel,at91sam9260-wdt";
  979. reg = <0xfffffd40 0x10>;
  980. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  981. clocks = <&clk32k>;
  982. atmel,watchdog-type = "hardware";
  983. atmel,reset-type = "all";
  984. atmel,dbg-halt;
  985. status = "disabled";
  986. };
  987. spi0: spi@fffa4000 {
  988. #address-cells = <1>;
  989. #size-cells = <0>;
  990. compatible = "atmel,at91rm9200-spi";
  991. reg = <0xfffa4000 0x200>;
  992. interrupts = <14 4 3>;
  993. pinctrl-names = "default";
  994. pinctrl-0 = <&pinctrl_spi0>;
  995. clocks = <&spi0_clk>;
  996. clock-names = "spi_clk";
  997. status = "disabled";
  998. };
  999. spi1: spi@fffa8000 {
  1000. #address-cells = <1>;
  1001. #size-cells = <0>;
  1002. compatible = "atmel,at91rm9200-spi";
  1003. reg = <0xfffa8000 0x200>;
  1004. interrupts = <15 4 3>;
  1005. pinctrl-names = "default";
  1006. pinctrl-0 = <&pinctrl_spi1>;
  1007. clocks = <&spi1_clk>;
  1008. clock-names = "spi_clk";
  1009. status = "disabled";
  1010. };
  1011. usb2: gadget@fff78000 {
  1012. #address-cells = <1>;
  1013. #size-cells = <0>;
  1014. compatible = "atmel,at91sam9g45-udc";
  1015. reg = <0x00600000 0x80000
  1016. 0xfff78000 0x400>;
  1017. interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
  1018. clocks = <&udphs_clk>, <&utmi>;
  1019. clock-names = "pclk", "hclk";
  1020. status = "disabled";
  1021. ep0 {
  1022. reg = <0>;
  1023. atmel,fifo-size = <64>;
  1024. atmel,nb-banks = <1>;
  1025. };
  1026. ep1 {
  1027. reg = <1>;
  1028. atmel,fifo-size = <1024>;
  1029. atmel,nb-banks = <2>;
  1030. atmel,can-dma;
  1031. atmel,can-isoc;
  1032. };
  1033. ep2 {
  1034. reg = <2>;
  1035. atmel,fifo-size = <1024>;
  1036. atmel,nb-banks = <2>;
  1037. atmel,can-dma;
  1038. atmel,can-isoc;
  1039. };
  1040. ep3 {
  1041. reg = <3>;
  1042. atmel,fifo-size = <1024>;
  1043. atmel,nb-banks = <3>;
  1044. atmel,can-dma;
  1045. };
  1046. ep4 {
  1047. reg = <4>;
  1048. atmel,fifo-size = <1024>;
  1049. atmel,nb-banks = <3>;
  1050. atmel,can-dma;
  1051. };
  1052. ep5 {
  1053. reg = <5>;
  1054. atmel,fifo-size = <1024>;
  1055. atmel,nb-banks = <3>;
  1056. atmel,can-dma;
  1057. atmel,can-isoc;
  1058. };
  1059. ep6 {
  1060. reg = <6>;
  1061. atmel,fifo-size = <1024>;
  1062. atmel,nb-banks = <3>;
  1063. atmel,can-dma;
  1064. atmel,can-isoc;
  1065. };
  1066. };
  1067. sckc@fffffd50 {
  1068. compatible = "atmel,at91sam9x5-sckc";
  1069. reg = <0xfffffd50 0x4>;
  1070. slow_osc: slow_osc {
  1071. compatible = "atmel,at91sam9x5-clk-slow-osc";
  1072. #clock-cells = <0>;
  1073. atmel,startup-time-usec = <1200000>;
  1074. clocks = <&slow_xtal>;
  1075. };
  1076. slow_rc_osc: slow_rc_osc {
  1077. compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
  1078. #clock-cells = <0>;
  1079. atmel,startup-time-usec = <75>;
  1080. clock-frequency = <32768>;
  1081. clock-accuracy = <50000000>;
  1082. };
  1083. clk32k: slck {
  1084. compatible = "atmel,at91sam9x5-clk-slow";
  1085. #clock-cells = <0>;
  1086. clocks = <&slow_rc_osc &slow_osc>;
  1087. };
  1088. };
  1089. rtc@fffffd20 {
  1090. compatible = "atmel,at91sam9260-rtt";
  1091. reg = <0xfffffd20 0x10>;
  1092. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  1093. clocks = <&clk32k>;
  1094. status = "disabled";
  1095. };
  1096. rtc@fffffdb0 {
  1097. compatible = "atmel,at91rm9200-rtc";
  1098. reg = <0xfffffdb0 0x30>;
  1099. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  1100. clocks = <&clk32k>;
  1101. status = "disabled";
  1102. };
  1103. gpbr: syscon@fffffd60 {
  1104. compatible = "atmel,at91sam9260-gpbr", "syscon";
  1105. reg = <0xfffffd60 0x10>;
  1106. status = "disabled";
  1107. };
  1108. };
  1109. fb0: fb@0x00500000 {
  1110. compatible = "atmel,at91sam9g45-lcdc";
  1111. reg = <0x00500000 0x1000>;
  1112. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
  1113. pinctrl-names = "default";
  1114. pinctrl-0 = <&pinctrl_fb>;
  1115. clocks = <&lcd_clk>, <&lcd_clk>;
  1116. clock-names = "hclk", "lcdc_clk";
  1117. status = "disabled";
  1118. };
  1119. nand0: nand@40000000 {
  1120. compatible = "atmel,at91rm9200-nand";
  1121. #address-cells = <1>;
  1122. #size-cells = <1>;
  1123. reg = <0x40000000 0x10000000
  1124. 0xffffe200 0x200
  1125. >;
  1126. atmel,nand-addr-offset = <21>;
  1127. atmel,nand-cmd-offset = <22>;
  1128. atmel,nand-has-dma;
  1129. pinctrl-names = "default";
  1130. pinctrl-0 = <&pinctrl_nand>;
  1131. gpios = <&pioC 8 GPIO_ACTIVE_HIGH
  1132. &pioC 14 GPIO_ACTIVE_HIGH
  1133. 0
  1134. >;
  1135. status = "disabled";
  1136. };
  1137. usb0: ohci@00700000 {
  1138. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  1139. reg = <0x00700000 0x100000>;
  1140. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  1141. clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  1142. clock-names = "ohci_clk", "hclk", "uhpck";
  1143. status = "disabled";
  1144. };
  1145. usb1: ehci@00800000 {
  1146. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  1147. reg = <0x00800000 0x100000>;
  1148. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  1149. clocks = <&utmi>, <&uhphs_clk>;
  1150. clock-names = "usb_clk", "ehci_clk";
  1151. status = "disabled";
  1152. };
  1153. };
  1154. i2c@0 {
  1155. compatible = "i2c-gpio";
  1156. gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
  1157. &pioA 21 GPIO_ACTIVE_HIGH /* scl */
  1158. >;
  1159. i2c-gpio,sda-open-drain;
  1160. i2c-gpio,scl-open-drain;
  1161. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  1162. #address-cells = <1>;
  1163. #size-cells = <0>;
  1164. status = "disabled";
  1165. };
  1166. };