armada-cp110-slave.dtsi 8.4 KB

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  1. /*
  2. * Copyright (C) 2016 Marvell Technology Group Ltd.
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPLv2 or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. /*
  43. * Device Tree file for Marvell Armada CP110 Slave.
  44. */
  45. #include <dt-bindings/comphy/comphy_data.h>
  46. / {
  47. cp110-slave {
  48. #address-cells = <2>;
  49. #size-cells = <2>;
  50. compatible = "simple-bus";
  51. interrupt-parent = <&gic>;
  52. ranges;
  53. config-space {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. compatible = "simple-bus";
  57. interrupt-parent = <&gic>;
  58. ranges = <0x0 0x0 0xf4000000 0x2000000>;
  59. cps_syscon0: system-controller@440000 {
  60. compatible = "marvell,cp110-system-controller0",
  61. "syscon";
  62. reg = <0x440000 0x1000>;
  63. #clock-cells = <2>;
  64. core-clock-output-names =
  65. "cps-apll", "cps-ppv2-core", "cps-eip",
  66. "cps-core", "cps-nand-core";
  67. gate-clock-output-names =
  68. "cps-audio", "cps-communit", "cps-nand",
  69. "cps-ppv2", "cps-sdio", "cps-mg-domain",
  70. "cps-mg-core", "cps-xor1", "cps-xor0",
  71. "cps-gop-dp", "none", "cps-pcie_x10",
  72. "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
  73. "cps-sata", "cps-sata-usb", "cps-main",
  74. "cps-sd-mmc", "none", "none",
  75. "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
  76. "cps-usb3dev", "cps-eip150", "cps-eip197";
  77. };
  78. cps_pinctl: cps-pinctl@440000 {
  79. compatible = "marvell,mvebu-pinctrl",
  80. "marvell,a80x0-cp1-pinctrl";
  81. bank-name ="cp1-110";
  82. reg = <0x440000 0x20>;
  83. pin-count = <63>;
  84. max-func = <0xf>;
  85. cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
  86. marvell,pins = < 0 1 2 3 4 5 6 7
  87. 8 9 10 11 >;
  88. marvell,function = <3>;
  89. };
  90. cps_spi1_pins: cps-spi-pins-1 {
  91. marvell,pins = < 13 14 15 16 >;
  92. marvell,function = <3>;
  93. };
  94. };
  95. cps_sata0: sata@540000 {
  96. compatible = "marvell,armada-8k-ahci";
  97. reg = <0x540000 0x30000>;
  98. interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  99. clocks = <&cps_syscon0 1 15>;
  100. status = "disabled";
  101. };
  102. cps_usb3_0: usb3@500000 {
  103. compatible = "marvell,armada-8k-xhci",
  104. "generic-xhci";
  105. reg = <0x500000 0x4000>;
  106. dma-coherent;
  107. interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
  108. clocks = <&cps_syscon0 1 22>;
  109. status = "disabled";
  110. };
  111. cps_usb3_1: usb3@510000 {
  112. compatible = "marvell,armada-8k-xhci",
  113. "generic-xhci";
  114. reg = <0x510000 0x4000>;
  115. dma-coherent;
  116. interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
  117. clocks = <&cps_syscon0 1 23>;
  118. status = "disabled";
  119. };
  120. cps_xor0: xor@6a0000 {
  121. compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
  122. reg = <0x6a0000 0x1000>,
  123. <0x6b0000 0x1000>;
  124. dma-coherent;
  125. msi-parent = <&gic_v2m0>;
  126. clocks = <&cps_syscon0 1 8>;
  127. };
  128. cps_xor1: xor@6c0000 {
  129. compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
  130. reg = <0x6c0000 0x1000>,
  131. <0x6d0000 0x1000>;
  132. dma-coherent;
  133. msi-parent = <&gic_v2m0>;
  134. clocks = <&cps_syscon0 1 7>;
  135. };
  136. cps_spi0: spi@700600 {
  137. compatible = "marvell,armada-380-spi";
  138. reg = <0x700600 0x50>;
  139. #address-cells = <0x1>;
  140. #size-cells = <0x0>;
  141. cell-index = <1>;
  142. clocks = <&cps_syscon0 0 3>;
  143. status = "disabled";
  144. };
  145. cps_spi1: spi@700680 {
  146. compatible = "marvell,armada-380-spi";
  147. reg = <0x700680 0x50>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. cell-index = <2>;
  151. clocks = <&cps_syscon0 1 21>;
  152. status = "disabled";
  153. };
  154. cps_i2c0: i2c@701000 {
  155. compatible = "marvell,mv78230-i2c";
  156. reg = <0x701000 0x20>;
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
  160. clocks = <&cps_syscon0 1 21>;
  161. status = "disabled";
  162. };
  163. cps_i2c1: i2c@701100 {
  164. compatible = "marvell,mv78230-i2c";
  165. reg = <0x701100 0x20>;
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
  169. clocks = <&cps_syscon0 1 21>;
  170. status = "disabled";
  171. };
  172. cps_comphy: comphy@441000 {
  173. compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
  174. reg = <0x441000 0x8>,
  175. <0x120000 0x8>;
  176. mux-bitcount = <4>;
  177. max-lanes = <6>;
  178. };
  179. cps_utmi0: utmi@580000 {
  180. compatible = "marvell,mvebu-utmi-2.6.0";
  181. reg = <0x580000 0x1000>, /* utmi-unit */
  182. <0x440420 0x4>, /* usb-cfg */
  183. <0x440440 0x4>; /* utmi-cfg */
  184. utmi-port = <UTMI_PHY_TO_USB_HOST0>;
  185. status = "disabled";
  186. };
  187. };
  188. cps_pcie0: pcie@f4600000 {
  189. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  190. reg = <0 0xf4600000 0 0x10000>,
  191. <0 0xfaf00000 0 0x80000>;
  192. reg-names = "ctrl", "config";
  193. #address-cells = <3>;
  194. #size-cells = <2>;
  195. #interrupt-cells = <1>;
  196. device_type = "pci";
  197. dma-coherent;
  198. msi-parent = <&gic_v2m0>;
  199. bus-range = <0 0xff>;
  200. ranges =
  201. /* downstream I/O */
  202. <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
  203. /* non-prefetchable memory */
  204. 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
  205. interrupt-map-mask = <0 0 0 0>;
  206. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
  207. interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
  208. num-lanes = <1>;
  209. clocks = <&cps_syscon0 1 13>;
  210. status = "disabled";
  211. };
  212. cps_pcie1: pcie@f4620000 {
  213. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  214. reg = <0 0xf4620000 0 0x10000>,
  215. <0 0xfbf00000 0 0x80000>;
  216. reg-names = "ctrl", "config";
  217. #address-cells = <3>;
  218. #size-cells = <2>;
  219. #interrupt-cells = <1>;
  220. device_type = "pci";
  221. dma-coherent;
  222. msi-parent = <&gic_v2m0>;
  223. bus-range = <0 0xff>;
  224. ranges =
  225. /* downstream I/O */
  226. <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
  227. /* non-prefetchable memory */
  228. 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
  229. interrupt-map-mask = <0 0 0 0>;
  230. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
  231. interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
  232. num-lanes = <1>;
  233. clocks = <&cps_syscon0 1 11>;
  234. status = "disabled";
  235. };
  236. cps_pcie2: pcie@f4640000 {
  237. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  238. reg = <0 0xf4640000 0 0x10000>,
  239. <0 0xfcf00000 0 0x80000>;
  240. reg-names = "ctrl", "config";
  241. #address-cells = <3>;
  242. #size-cells = <2>;
  243. #interrupt-cells = <1>;
  244. device_type = "pci";
  245. dma-coherent;
  246. msi-parent = <&gic_v2m0>;
  247. bus-range = <0 0xff>;
  248. ranges =
  249. /* downstream I/O */
  250. <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
  251. /* non-prefetchable memory */
  252. 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
  253. interrupt-map-mask = <0 0 0 0>;
  254. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
  255. interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
  256. num-lanes = <1>;
  257. clocks = <&cps_syscon0 1 12>;
  258. status = "disabled";
  259. };
  260. };
  261. };