armada-cp110-master.dtsi 8.5 KB

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  1. /*
  2. * Copyright (C) 2016 Marvell Technology Group Ltd.
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPLv2 or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. /*
  43. * Device Tree file for Marvell Armada CP110 Master.
  44. */
  45. #include <dt-bindings/comphy/comphy_data.h>
  46. / {
  47. cp110-master {
  48. #address-cells = <2>;
  49. #size-cells = <2>;
  50. compatible = "simple-bus";
  51. interrupt-parent = <&gic>;
  52. ranges;
  53. config-space {
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. compatible = "simple-bus";
  57. interrupt-parent = <&gic>;
  58. ranges = <0x0 0x0 0xf2000000 0x2000000>;
  59. cpm_syscon0: system-controller@440000 {
  60. compatible = "marvell,cp110-system-controller0",
  61. "syscon";
  62. reg = <0x440000 0x1000>;
  63. #clock-cells = <2>;
  64. core-clock-output-names =
  65. "cpm-apll", "cpm-ppv2-core", "cpm-eip",
  66. "cpm-core", "cpm-nand-core";
  67. gate-clock-output-names =
  68. "cpm-audio", "cpm-communit", "cpm-nand",
  69. "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
  70. "cpm-mg-core", "cpm-xor1", "cpm-xor0",
  71. "cpm-gop-dp", "none", "cpm-pcie_x10",
  72. "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
  73. "cpm-sata", "cpm-sata-usb", "cpm-main",
  74. "cpm-sd-mmc", "none", "none",
  75. "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
  76. "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
  77. };
  78. cpm_pinctl: cpm-pinctl@440000 {
  79. compatible = "marvell,mvebu-pinctrl",
  80. "marvell,a70x0-pinctrl",
  81. "marvell,a80x0-cp0-pinctrl";
  82. bank-name ="cp0-110";
  83. reg = <0x440000 0x20>;
  84. pin-count = <63>;
  85. max-func = <0xf>;
  86. cpm_i2c0_pins: cpm-i2c-pins-0 {
  87. marvell,pins = < 37 38 >;
  88. marvell,function = <2>;
  89. };
  90. cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
  91. marvell,pins = < 44 45 46 47 48 49 50 51
  92. 52 53 54 55 >;
  93. marvell,function = <1>;
  94. };
  95. pca0_pins: cpm-pca0_pins {
  96. marvell,pins = <62>;
  97. marvell,function = <0>;
  98. };
  99. cpm_sdhci_pins: cpm-sdhi-pins-0 {
  100. marvell,pins = < 56 57 58 59 60 61 >;
  101. marvell,function = <14>;
  102. };
  103. cpm_spi0_pins: cpm-spi-pins-0 {
  104. marvell,pins = < 13 14 15 16 >;
  105. marvell,function = <3>;
  106. };
  107. };
  108. cpm_sata0: sata@540000 {
  109. compatible = "marvell,armada-8k-ahci";
  110. reg = <0x540000 0x30000>;
  111. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  112. clocks = <&cpm_syscon0 1 15>;
  113. status = "disabled";
  114. };
  115. cpm_usb3_0: usb3@500000 {
  116. compatible = "marvell,armada-8k-xhci",
  117. "generic-xhci";
  118. reg = <0x500000 0x4000>;
  119. dma-coherent;
  120. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  121. clocks = <&cpm_syscon0 1 22>;
  122. status = "disabled";
  123. };
  124. cpm_usb3_1: usb3@510000 {
  125. compatible = "marvell,armada-8k-xhci",
  126. "generic-xhci";
  127. reg = <0x510000 0x4000>;
  128. dma-coherent;
  129. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  130. clocks = <&cpm_syscon0 1 23>;
  131. status = "disabled";
  132. };
  133. cpm_spi0: spi@700600 {
  134. compatible = "marvell,armada-380-spi";
  135. reg = <0x700600 0x50>;
  136. #address-cells = <0x1>;
  137. #size-cells = <0x0>;
  138. cell-index = <1>;
  139. clocks = <&cpm_syscon0 0 3>;
  140. status = "disabled";
  141. };
  142. cpm_spi1: spi@700680 {
  143. compatible = "marvell,armada-380-spi";
  144. reg = <0x700680 0x50>;
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. cell-index = <2>;
  148. clocks = <&cpm_syscon0 1 21>;
  149. status = "disabled";
  150. };
  151. cpm_i2c0: i2c@701000 {
  152. compatible = "marvell,mv78230-i2c";
  153. reg = <0x701000 0x20>;
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  157. clocks = <&cpm_syscon0 1 21>;
  158. status = "disabled";
  159. };
  160. cpm_i2c1: i2c@701100 {
  161. compatible = "marvell,mv78230-i2c";
  162. reg = <0x701100 0x20>;
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  166. clocks = <&cpm_syscon0 1 21>;
  167. status = "disabled";
  168. };
  169. cpm_comphy: comphy@441000 {
  170. compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
  171. reg = <0x441000 0x8>,
  172. <0x120000 0x8>;
  173. mux-bitcount = <4>;
  174. max-lanes = <6>;
  175. };
  176. cpm_utmi0: utmi@580000 {
  177. compatible = "marvell,mvebu-utmi-2.6.0";
  178. reg = <0x580000 0x1000>, /* utmi-unit */
  179. <0x440420 0x4>, /* usb-cfg */
  180. <0x440440 0x4>; /* utmi-cfg */
  181. utmi-port = <UTMI_PHY_TO_USB_HOST0>;
  182. status = "disabled";
  183. };
  184. cpm_utmi1: utmi@581000 {
  185. compatible = "marvell,mvebu-utmi-2.6.0";
  186. reg = <0x581000 0x1000>, /* utmi-unit */
  187. <0x440420 0x4>, /* usb-cfg */
  188. <0x440444 0x4>; /* utmi-cfg */
  189. utmi-port = <UTMI_PHY_TO_USB_HOST1>;
  190. status = "disabled";
  191. };
  192. };
  193. cpm_pcie0: pcie@f2600000 {
  194. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  195. reg = <0 0xf2600000 0 0x10000>,
  196. <0 0xf6f00000 0 0x80000>;
  197. reg-names = "ctrl", "config";
  198. #address-cells = <3>;
  199. #size-cells = <2>;
  200. #interrupt-cells = <1>;
  201. device_type = "pci";
  202. dma-coherent;
  203. bus-range = <0 0xff>;
  204. ranges =
  205. /* downstream I/O */
  206. <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
  207. /* non-prefetchable memory */
  208. 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
  209. interrupt-map-mask = <0 0 0 0>;
  210. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  211. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  212. num-lanes = <1>;
  213. clocks = <&cpm_syscon0 1 13>;
  214. status = "disabled";
  215. };
  216. cpm_pcie1: pcie@f2620000 {
  217. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  218. reg = <0 0xf2620000 0 0x10000>,
  219. <0 0xf7f00000 0 0x80000>;
  220. reg-names = "ctrl", "config";
  221. #address-cells = <3>;
  222. #size-cells = <2>;
  223. #interrupt-cells = <1>;
  224. device_type = "pci";
  225. dma-coherent;
  226. bus-range = <0 0xff>;
  227. ranges =
  228. /* downstream I/O */
  229. <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
  230. /* non-prefetchable memory */
  231. 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
  232. interrupt-map-mask = <0 0 0 0>;
  233. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  234. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  235. num-lanes = <1>;
  236. clocks = <&cpm_syscon0 1 11>;
  237. status = "disabled";
  238. };
  239. cpm_pcie2: pcie@f2640000 {
  240. compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
  241. reg = <0 0xf2640000 0 0x10000>,
  242. <0 0xf8f00000 0 0x80000>;
  243. reg-names = "ctrl", "config";
  244. #address-cells = <3>;
  245. #size-cells = <2>;
  246. #interrupt-cells = <1>;
  247. device_type = "pci";
  248. dma-coherent;
  249. bus-range = <0 0xff>;
  250. ranges =
  251. /* downstream I/O */
  252. <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
  253. /* non-prefetchable memory */
  254. 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
  255. interrupt-map-mask = <0 0 0 0>;
  256. interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  257. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  258. num-lanes = <1>;
  259. clocks = <&cpm_syscon0 1 12>;
  260. status = "disabled";
  261. };
  262. };
  263. };