armada-8040-db.dts 6.2 KB

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  1. /*
  2. * Copyright (C) 2016 Marvell Technology Group Ltd.
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPLv2 or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. /*
  43. * Device Tree file for Marvell Armada 8040 Development board platform
  44. */
  45. #include "armada-8040.dtsi"
  46. / {
  47. model = "Marvell Armada 8040 DB board";
  48. compatible = "marvell,armada8040-db", "marvell,armada8040",
  49. "marvell,armada-ap806-quad", "marvell,armada-ap806";
  50. chosen {
  51. stdout-path = "serial0:115200n8";
  52. };
  53. aliases {
  54. i2c0 = &cpm_i2c0;
  55. spi0 = &cps_spi1;
  56. };
  57. memory@00000000 {
  58. device_type = "memory";
  59. reg = <0x0 0x0 0x0 0x80000000>;
  60. };
  61. };
  62. /* Accessible over the mini-USB CON9 connector on the main board */
  63. &uart0 {
  64. status = "okay";
  65. };
  66. &ap_pinctl {
  67. /* MPP Bus:
  68. * SDIO [0-10]
  69. * UART0 [11,19]
  70. */
  71. /* 0 1 2 3 4 5 6 7 8 9 */
  72. pin-func = < 1 1 1 1 1 1 1 1 1 1
  73. 1 3 0 0 0 0 0 0 0 3 >;
  74. };
  75. &cpm_pinctl {
  76. /* MPP Bus:
  77. * [0-31] = 0xff: Keep default CP0_shared_pins:
  78. * [11] CLKOUT_MPP_11 (out)
  79. * [23] LINK_RD_IN_CP2CP (in)
  80. * [25] CLKOUT_MPP_25 (out)
  81. * [29] AVS_FB_IN_CP2CP (in)
  82. * [32,34] SMI
  83. * [31] GPIO: push button/Wake
  84. * [35-36] GPIO
  85. * [37-38] I2C
  86. * [40-41] SATA[0/1]_PRESENT_ACTIVEn
  87. * [42-43] XSMI
  88. * [44-55] RGMII1
  89. * [56-62] SD
  90. */
  91. /* 0 1 2 3 4 5 6 7 8 9 */
  92. pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  93. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  94. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  95. 0xff 0 7 0 7 0 0 2 2 0
  96. 0 0 8 8 1 1 1 1 1 1
  97. 1 1 1 1 1 1 0xe 0xe 0xe 0xe
  98. 0xe 0xe 0xe >;
  99. };
  100. /* CON5 on CP0 expansion */
  101. &cpm_pcie2 {
  102. status = "okay";
  103. };
  104. &cpm_i2c0 {
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&cpm_i2c0_pins>;
  107. status = "okay";
  108. clock-frequency = <100000>;
  109. };
  110. /* CON4 on CP0 expansion */
  111. &cpm_sata0 {
  112. status = "okay";
  113. };
  114. /* CON9 on CP0 expansion */
  115. &cpm_usb3_0 {
  116. status = "okay";
  117. };
  118. /* CON10 on CP0 expansion */
  119. &cpm_usb3_1 {
  120. status = "okay";
  121. };
  122. &cps_pinctl {
  123. /* MPP Bus:
  124. * [0-11] RGMII0
  125. * [13-16] SPI1
  126. * [27,31] GE_MDIO/MDC
  127. * [32-62] = 0xff: Keep default CP1_shared_pins:
  128. */
  129. /* 0 1 2 3 4 5 6 7 8 9 */
  130. pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
  131. 0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
  132. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
  133. 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  134. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  135. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  136. 0xff 0xff 0xff >;
  137. };
  138. /* CON5 on CP1 expansion */
  139. &cps_pcie2 {
  140. status = "okay";
  141. };
  142. &cps_spi1 {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&cps_spi1_pins>;
  145. status = "okay";
  146. spi-flash@0 {
  147. #address-cells = <1>;
  148. #size-cells = <1>;
  149. compatible = "jedec,spi-nor";
  150. reg = <0>;
  151. spi-max-frequency = <10000000>;
  152. partitions {
  153. compatible = "fixed-partitions";
  154. #address-cells = <1>;
  155. #size-cells = <1>;
  156. partition@0 {
  157. label = "U-Boot";
  158. reg = <0 0x200000>;
  159. };
  160. partition@400000 {
  161. label = "Filesystem";
  162. reg = <0x200000 0xce0000>;
  163. };
  164. };
  165. };
  166. };
  167. /* CON4 on CP1 expansion */
  168. &cps_sata0 {
  169. status = "okay";
  170. };
  171. /* CON9 on CP1 expansion */
  172. &cps_usb3_0 {
  173. status = "okay";
  174. };
  175. /* CON10 on CP1 expansion */
  176. &cps_usb3_1 {
  177. status = "okay";
  178. };
  179. &cpm_comphy {
  180. /*
  181. * Serdes Configuration:
  182. * Lane 0: SGMII2
  183. * Lane 1: USB3_HOST0
  184. * Lane 2: KR (10G)
  185. * Lane 3: SATA1
  186. * Lane 4: USB3_HOST1
  187. * Lane 5: PEX2x1
  188. */
  189. phy0 {
  190. phy-type = <PHY_TYPE_SGMII2>;
  191. phy-speed = <PHY_SPEED_3_125G>;
  192. };
  193. phy1 {
  194. phy-type = <PHY_TYPE_USB3_HOST0>;
  195. };
  196. phy2 {
  197. phy-type = <PHY_TYPE_KR>;
  198. };
  199. phy3 {
  200. phy-type = <PHY_TYPE_SATA1>;
  201. };
  202. phy4 {
  203. phy-type = <PHY_TYPE_USB3_HOST1>;
  204. };
  205. phy5 {
  206. phy-type = <PHY_TYPE_PEX2>;
  207. };
  208. };
  209. &cps_comphy {
  210. /*
  211. * Serdes Configuration:
  212. * Lane 0: SGMII2
  213. * Lane 1: USB3_HOST0
  214. * Lane 2: KR (10G)
  215. * Lane 3: SATA1
  216. * Lane 4: Unconnected
  217. * Lane 5: PEX2x1
  218. */
  219. phy0 {
  220. phy-type = <PHY_TYPE_SGMII2>;
  221. phy-speed = <PHY_SPEED_3_125G>;
  222. };
  223. phy1 {
  224. phy-type = <PHY_TYPE_USB3_HOST0>;
  225. };
  226. phy2 {
  227. phy-type = <PHY_TYPE_KR>;
  228. };
  229. phy3 {
  230. phy-type = <PHY_TYPE_SATA1>;
  231. };
  232. phy4 {
  233. phy-type = <PHY_TYPE_UNCONNECTED>;
  234. };
  235. phy5 {
  236. phy-type = <PHY_TYPE_PEX2>;
  237. };
  238. };
  239. &cpm_utmi0 {
  240. status = "okay";
  241. };
  242. &cpm_utmi1 {
  243. status = "okay";
  244. };
  245. &cps_utmi0 {
  246. status = "okay";
  247. };