armada-388-gp.dts 9.8 KB

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  1. /*
  2. * Device Tree file for Marvell Armada 385 development board
  3. * (RD-88F6820-GP)
  4. *
  5. * Copyright (C) 2014 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. *
  9. * This file is dual-licensed: you can use it either under the terms
  10. * of the GPL or the X11 license, at your option. Note that this dual
  11. * licensing only applies to this file, and not this project as a
  12. * whole.
  13. *
  14. * a) This file is licensed under the terms of the GNU General Public
  15. * License version 2. This program is licensed "as is" without
  16. * any warranty of any kind, whether express or implied.
  17. *
  18. * Or, alternatively,
  19. *
  20. * b) Permission is hereby granted, free of charge, to any person
  21. * obtaining a copy of this software and associated documentation
  22. * files (the "Software"), to deal in the Software without
  23. * restriction, including without limitation the rights to use,
  24. * copy, modify, merge, publish, distribute, sublicense, and/or
  25. * sell copies of the Software, and to permit persons to whom the
  26. * Software is furnished to do so, subject to the following
  27. * conditions:
  28. *
  29. * The above copyright notice and this permission notice shall be
  30. * included in all copies or substantial portions of the Software.
  31. *
  32. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39. * OTHER DEALINGS IN THE SOFTWARE.
  40. */
  41. /dts-v1/;
  42. #include "armada-388.dtsi"
  43. #include <dt-bindings/gpio/gpio.h>
  44. / {
  45. model = "Marvell Armada 385 GP";
  46. compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
  47. chosen {
  48. stdout-path = "serial0:115200n8";
  49. };
  50. aliases {
  51. ethernet0 = &eth0;
  52. ethernet1 = &eth1;
  53. spi0 = &spi0;
  54. };
  55. memory {
  56. device_type = "memory";
  57. reg = <0x00000000 0x80000000>; /* 2 GB */
  58. };
  59. soc {
  60. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  61. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  62. internal-regs {
  63. spi@10600 {
  64. pinctrl-names = "default";
  65. pinctrl-0 = <&spi0_pins>;
  66. status = "okay";
  67. u-boot,dm-pre-reloc;
  68. spi-flash@0 {
  69. u-boot,dm-pre-reloc;
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. compatible = "st,m25p128", "jedec,spi-nor";
  73. reg = <0>; /* Chip select 0 */
  74. spi-max-frequency = <50000000>;
  75. m25p,fast-read;
  76. };
  77. };
  78. i2c@11000 {
  79. pinctrl-names = "default";
  80. pinctrl-0 = <&i2c0_pins>;
  81. status = "okay";
  82. clock-frequency = <100000>;
  83. /*
  84. * The EEPROM located at adresse 54 is needed
  85. * for the boot - DO NOT ERASE IT -
  86. */
  87. expander0: pca9555@20 {
  88. compatible = "nxp,pca9555";
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pca0_pins>;
  91. interrupt-parent = <&gpio0>;
  92. interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. interrupt-controller;
  96. #interrupt-cells = <2>;
  97. reg = <0x20>;
  98. };
  99. expander1: pca9555@21 {
  100. compatible = "nxp,pca9555";
  101. pinctrl-names = "default";
  102. interrupt-parent = <&gpio0>;
  103. interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
  104. gpio-controller;
  105. #gpio-cells = <2>;
  106. interrupt-controller;
  107. #interrupt-cells = <2>;
  108. reg = <0x21>;
  109. };
  110. };
  111. serial@12000 {
  112. /*
  113. * Exported on the micro USB connector CON16
  114. * through an FTDI
  115. */
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&uart0_pins>;
  118. status = "okay";
  119. u-boot,dm-pre-reloc;
  120. };
  121. /* GE1 CON15 */
  122. ethernet@30000 {
  123. pinctrl-names = "default";
  124. pinctrl-0 = <&ge1_rgmii_pins>;
  125. status = "okay";
  126. phy = <&phy1>;
  127. phy-mode = "rgmii-id";
  128. };
  129. /* CON4 */
  130. usb@58000 {
  131. vcc-supply = <&reg_usb2_0_vbus>;
  132. status = "okay";
  133. };
  134. /* GE0 CON1 */
  135. ethernet@70000 {
  136. pinctrl-names = "default";
  137. /*
  138. * The Reference Clock 0 is used to provide a
  139. * clock to the PHY
  140. */
  141. pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
  142. status = "okay";
  143. phy = <&phy0>;
  144. phy-mode = "rgmii-id";
  145. };
  146. mdio@72004 {
  147. pinctrl-names = "default";
  148. pinctrl-0 = <&mdio_pins>;
  149. phy0: ethernet-phy@1 {
  150. reg = <1>;
  151. };
  152. phy1: ethernet-phy@0 {
  153. reg = <0>;
  154. };
  155. };
  156. sata@a8000 {
  157. pinctrl-names = "default";
  158. pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
  159. status = "okay";
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162. sata0: sata-port@0 {
  163. reg = <0>;
  164. target-supply = <&reg_5v_sata0>;
  165. };
  166. sata1: sata-port@1 {
  167. reg = <1>;
  168. target-supply = <&reg_5v_sata1>;
  169. };
  170. };
  171. sata@e0000 {
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
  174. status = "okay";
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. sata2: sata-port@0 {
  178. reg = <0>;
  179. target-supply = <&reg_5v_sata2>;
  180. };
  181. sata3: sata-port@1 {
  182. reg = <1>;
  183. target-supply = <&reg_5v_sata3>;
  184. };
  185. };
  186. sdhci@d8000 {
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&sdhci_pins>;
  189. cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
  190. no-1-8-v;
  191. wp-inverted;
  192. bus-width = <8>;
  193. status = "okay";
  194. };
  195. /* CON5 */
  196. usb3@f0000 {
  197. vcc-supply = <&reg_usb2_1_vbus>;
  198. status = "okay";
  199. };
  200. /* CON7 */
  201. usb3@f8000 {
  202. vcc-supply = <&reg_usb3_vbus>;
  203. status = "okay";
  204. };
  205. };
  206. pcie-controller {
  207. status = "okay";
  208. /*
  209. * One PCIe units is accessible through
  210. * standard PCIe slot on the board.
  211. */
  212. pcie@1,0 {
  213. /* Port 0, Lane 0 */
  214. status = "okay";
  215. };
  216. /*
  217. * The two other PCIe units are accessible
  218. * through mini PCIe slot on the board.
  219. */
  220. pcie@2,0 {
  221. /* Port 1, Lane 0 */
  222. status = "okay";
  223. };
  224. pcie@3,0 {
  225. /* Port 2, Lane 0 */
  226. status = "okay";
  227. };
  228. };
  229. gpio-fan {
  230. compatible = "gpio-fan";
  231. gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
  232. gpio-fan,speed-map = < 0 0
  233. 3000 1>;
  234. };
  235. };
  236. reg_usb3_vbus: usb3-vbus {
  237. compatible = "regulator-fixed";
  238. regulator-name = "usb3-vbus";
  239. regulator-min-microvolt = <5000000>;
  240. regulator-max-microvolt = <5000000>;
  241. enable-active-high;
  242. regulator-always-on;
  243. gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
  244. };
  245. reg_usb2_0_vbus: v5-vbus0 {
  246. compatible = "regulator-fixed";
  247. regulator-name = "v5.0-vbus0";
  248. regulator-min-microvolt = <5000000>;
  249. regulator-max-microvolt = <5000000>;
  250. enable-active-high;
  251. regulator-always-on;
  252. gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
  253. };
  254. reg_usb2_1_vbus: v5-vbus1 {
  255. compatible = "regulator-fixed";
  256. regulator-name = "v5.0-vbus1";
  257. regulator-min-microvolt = <5000000>;
  258. regulator-max-microvolt = <5000000>;
  259. enable-active-high;
  260. regulator-always-on;
  261. gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
  262. };
  263. reg_usb2_1_vbus: v5-vbus1 {
  264. compatible = "regulator-fixed";
  265. regulator-name = "v5.0-vbus1";
  266. regulator-min-microvolt = <5000000>;
  267. regulator-max-microvolt = <5000000>;
  268. enable-active-high;
  269. regulator-always-on;
  270. gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
  271. };
  272. reg_sata0: pwr-sata0 {
  273. compatible = "regulator-fixed";
  274. regulator-name = "pwr_en_sata0";
  275. enable-active-high;
  276. regulator-always-on;
  277. };
  278. reg_5v_sata0: v5-sata0 {
  279. compatible = "regulator-fixed";
  280. regulator-name = "v5.0-sata0";
  281. regulator-min-microvolt = <5000000>;
  282. regulator-max-microvolt = <5000000>;
  283. regulator-always-on;
  284. vin-supply = <&reg_sata0>;
  285. };
  286. reg_12v_sata0: v12-sata0 {
  287. compatible = "regulator-fixed";
  288. regulator-name = "v12.0-sata0";
  289. regulator-min-microvolt = <12000000>;
  290. regulator-max-microvolt = <12000000>;
  291. regulator-always-on;
  292. vin-supply = <&reg_sata0>;
  293. };
  294. reg_sata1: pwr-sata1 {
  295. regulator-name = "pwr_en_sata1";
  296. compatible = "regulator-fixed";
  297. regulator-min-microvolt = <12000000>;
  298. regulator-max-microvolt = <12000000>;
  299. enable-active-high;
  300. regulator-always-on;
  301. gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
  302. };
  303. reg_5v_sata1: v5-sata1 {
  304. compatible = "regulator-fixed";
  305. regulator-name = "v5.0-sata1";
  306. regulator-min-microvolt = <5000000>;
  307. regulator-max-microvolt = <5000000>;
  308. regulator-always-on;
  309. vin-supply = <&reg_sata1>;
  310. };
  311. reg_12v_sata1: v12-sata1 {
  312. compatible = "regulator-fixed";
  313. regulator-name = "v12.0-sata1";
  314. regulator-min-microvolt = <12000000>;
  315. regulator-max-microvolt = <12000000>;
  316. regulator-always-on;
  317. vin-supply = <&reg_sata1>;
  318. };
  319. reg_sata2: pwr-sata2 {
  320. compatible = "regulator-fixed";
  321. regulator-name = "pwr_en_sata2";
  322. enable-active-high;
  323. regulator-always-on;
  324. gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
  325. };
  326. reg_5v_sata2: v5-sata2 {
  327. compatible = "regulator-fixed";
  328. regulator-name = "v5.0-sata2";
  329. regulator-min-microvolt = <5000000>;
  330. regulator-max-microvolt = <5000000>;
  331. regulator-always-on;
  332. vin-supply = <&reg_sata2>;
  333. };
  334. reg_12v_sata2: v12-sata2 {
  335. compatible = "regulator-fixed";
  336. regulator-name = "v12.0-sata2";
  337. regulator-min-microvolt = <12000000>;
  338. regulator-max-microvolt = <12000000>;
  339. regulator-always-on;
  340. vin-supply = <&reg_sata2>;
  341. };
  342. reg_sata3: pwr-sata3 {
  343. compatible = "regulator-fixed";
  344. regulator-name = "pwr_en_sata3";
  345. enable-active-high;
  346. regulator-always-on;
  347. gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
  348. };
  349. reg_5v_sata3: v5-sata3 {
  350. compatible = "regulator-fixed";
  351. regulator-name = "v5.0-sata3";
  352. regulator-min-microvolt = <5000000>;
  353. regulator-max-microvolt = <5000000>;
  354. regulator-always-on;
  355. vin-supply = <&reg_sata3>;
  356. };
  357. reg_12v_sata3: v12-sata3 {
  358. compatible = "regulator-fixed";
  359. regulator-name = "v12.0-sata3";
  360. regulator-min-microvolt = <12000000>;
  361. regulator-max-microvolt = <12000000>;
  362. regulator-always-on;
  363. vin-supply = <&reg_sata3>;
  364. };
  365. };
  366. &pinctrl {
  367. pca0_pins: pca0_pins {
  368. marvell,pins = "mpp18";
  369. marvell,function = "gpio";
  370. };
  371. };