am571x-idk.dts 13 KB

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  1. /*
  2. * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "dra72x.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include "am57xx-idk-common.dtsi"
  13. / {
  14. model = "TI AM5718 IDK";
  15. compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
  16. memory@80000000 {
  17. device_type = "memory";
  18. reg = <0x0 0x80000000 0x0 0x40000000>;
  19. };
  20. leds {
  21. compatible = "gpio-leds";
  22. cpu0-led {
  23. label = "status0:red:cpu0";
  24. gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  25. default-state = "off";
  26. linux,default-trigger = "cpu0";
  27. };
  28. usr0-led {
  29. label = "status0:green:usr";
  30. gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  31. default-state = "off";
  32. };
  33. heartbeat-led {
  34. label = "status0:blue:heartbeat";
  35. gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
  36. default-state = "off";
  37. linux,default-trigger = "heartbeat";
  38. };
  39. usr1-led {
  40. label = "status1:red:usr";
  41. gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
  42. default-state = "off";
  43. };
  44. usr2-led {
  45. label = "status1:green:usr";
  46. gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
  47. default-state = "off";
  48. };
  49. mmc0-led {
  50. label = "status1:blue:mmc0";
  51. gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  52. default-state = "off";
  53. linux,default-trigger = "mmc0";
  54. };
  55. };
  56. extcon_usb2: extcon_usb2 {
  57. compatible = "linux,extcon-usb-gpio";
  58. id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  59. };
  60. };
  61. &dra7_pmx_core {
  62. mmc1_pins_default: mmc1_pins_default {
  63. pinctrl-single,pins = <
  64. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  65. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  66. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  67. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  68. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  69. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  70. >;
  71. };
  72. mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
  73. pinctrl-single,pins = <
  74. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  75. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  76. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  77. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  78. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  79. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  80. >;
  81. };
  82. mmc1_pins_hs: mmc1_pins_hs {
  83. pinctrl-single,pins = <
  84. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  85. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  86. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  87. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  88. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  89. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  90. >;
  91. };
  92. mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
  93. pinctrl-single,pins = <
  94. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  95. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  96. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  97. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  98. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  99. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  100. >;
  101. };
  102. mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
  103. pinctrl-single,pins = <
  104. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */
  105. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */
  106. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */
  107. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */
  108. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */
  109. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */
  110. >;
  111. };
  112. mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
  113. pinctrl-single,pins = <
  114. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
  115. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
  116. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
  117. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
  118. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
  119. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
  120. >;
  121. };
  122. mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
  123. pinctrl-single,pins = <
  124. DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
  125. DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
  126. DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
  127. DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
  128. DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
  129. DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
  130. >;
  131. };
  132. mmc2_pins_default: mmc2_pins_default {
  133. pinctrl-single,pins = <
  134. DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  135. DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  136. DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  137. DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  138. DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  139. DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  140. DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  141. DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  142. DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
  143. DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
  144. >;
  145. };
  146. mmc2_pins_hs: mmc2_pins_hs {
  147. pinctrl-single,pins = <
  148. DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  149. DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  150. DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  151. DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  152. DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  153. DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  154. DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  155. DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  156. DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
  157. DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
  158. >;
  159. };
  160. mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
  161. pinctrl-single,pins = <
  162. DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  163. DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  164. DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  165. DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  166. DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  167. DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  168. DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  169. DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  170. DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
  171. DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
  172. >;
  173. };
  174. };
  175. &dra7_iodelay_core {
  176. mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
  177. pinctrl-pin-array = <
  178. 0x618 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
  179. 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
  180. 0x630 A_DELAY_PS(495) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
  181. 0x63C A_DELAY_PS(116) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
  182. 0x648 A_DELAY_PS(117) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
  183. 0x654 A_DELAY_PS(32) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
  184. 0x620 A_DELAY_PS(1224) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
  185. 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
  186. 0x638 A_DELAY_PS(44) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
  187. 0x644 A_DELAY_PS(64) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
  188. 0x650 A_DELAY_PS(79) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
  189. 0x65C A_DELAY_PS(87) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
  190. 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
  191. 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
  192. 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
  193. 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
  194. 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
  195. >;
  196. };
  197. mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
  198. pinctrl-pin-array = <
  199. 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */
  200. 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
  201. 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
  202. 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
  203. 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
  204. 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
  205. 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
  206. 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
  207. 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
  208. 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
  209. 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
  210. >;
  211. };
  212. mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
  213. pinctrl-pin-array = <
  214. 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
  215. 0x1a4 A_DELAY_PS(121) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */
  216. 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */
  217. 0x1bc A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */
  218. 0x1c8 A_DELAY_PS(108) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */
  219. 0x1d4 A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */
  220. 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
  221. 0x1ec A_DELAY_PS(24) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
  222. 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */
  223. 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
  224. 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
  225. 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
  226. 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
  227. 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
  228. 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
  229. 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
  230. 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
  231. 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
  232. 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
  233. 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
  234. 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
  235. 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
  236. 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
  237. 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
  238. 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
  239. 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
  240. 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
  241. 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
  242. 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
  243. >;
  244. };
  245. };
  246. &mmc1 {
  247. pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
  248. pinctrl-0 = <&mmc1_pins_default>;
  249. pinctrl-1 = <&mmc1_pins_hs>;
  250. pinctrl-2 = <&mmc1_pins_sdr12>;
  251. pinctrl-3 = <&mmc1_pins_sdr25>;
  252. pinctrl-4 = <&mmc1_pins_sdr50>;
  253. pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
  254. pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;
  255. };
  256. &mmc2 {
  257. pinctrl-names = "default", "hs", "ddr_1_8v";
  258. pinctrl-0 = <&mmc2_pins_default>;
  259. pinctrl-1 = <&mmc2_pins_hs>;
  260. pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
  261. };
  262. &omap_dwc3_2 {
  263. extcon = <&extcon_usb2>;
  264. };