am437x-gp-evm.dts 22 KB

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  1. /*
  2. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /* AM437x GP EVM */
  9. /dts-v1/;
  10. #include "am4372.dtsi"
  11. #include <dt-bindings/pinctrl/am43xx.h>
  12. #include <dt-bindings/pwm/pwm.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "TI AM437x GP EVM";
  16. compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  17. aliases {
  18. display0 = &lcd0;
  19. serial3 = &uart3;
  20. };
  21. chosen {
  22. stdout-path = &uart0;
  23. tick-timer = &timer2;
  24. };
  25. vmmcsd_fixed: fixedregulator-sd {
  26. compatible = "regulator-fixed";
  27. regulator-name = "vmmcsd_fixed";
  28. regulator-min-microvolt = <3300000>;
  29. regulator-max-microvolt = <3300000>;
  30. enable-active-high;
  31. };
  32. vtt_fixed: fixedregulator-vtt {
  33. compatible = "regulator-fixed";
  34. regulator-name = "vtt_fixed";
  35. regulator-min-microvolt = <1500000>;
  36. regulator-max-microvolt = <1500000>;
  37. regulator-always-on;
  38. regulator-boot-on;
  39. enable-active-high;
  40. gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  41. };
  42. vmmcwl_fixed: fixedregulator-mmcwl {
  43. compatible = "regulator-fixed";
  44. regulator-name = "vmmcwl_fixed";
  45. regulator-min-microvolt = <1800000>;
  46. regulator-max-microvolt = <1800000>;
  47. gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  48. enable-active-high;
  49. };
  50. backlight {
  51. compatible = "pwm-backlight";
  52. pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  53. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  54. default-brightness-level = <8>;
  55. };
  56. matrix_keypad: matrix_keypad@0 {
  57. compatible = "gpio-matrix-keypad";
  58. debounce-delay-ms = <5>;
  59. col-scan-delay-us = <2>;
  60. row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  61. &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  62. &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  63. col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  64. &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  65. linux,keymap = <0x00000201 /* P1 */
  66. 0x00010202 /* P2 */
  67. 0x01000067 /* UP */
  68. 0x0101006a /* RIGHT */
  69. 0x02000069 /* LEFT */
  70. 0x0201006c>; /* DOWN */
  71. };
  72. lcd0: display {
  73. compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  74. label = "lcd";
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&lcd_pins>;
  77. /*
  78. * SelLCDorHDMI, LOW to select HDMI. This is not really the
  79. * panel's enable GPIO, but we don't have HDMI driver support nor
  80. * support to switch between two displays, so using this gpio as
  81. * panel's enable should be safe.
  82. */
  83. enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
  84. panel-timing {
  85. clock-frequency = <33000000>;
  86. hactive = <800>;
  87. vactive = <480>;
  88. hfront-porch = <210>;
  89. hback-porch = <16>;
  90. hsync-len = <30>;
  91. vback-porch = <10>;
  92. vfront-porch = <22>;
  93. vsync-len = <13>;
  94. hsync-active = <0>;
  95. vsync-active = <0>;
  96. de-active = <1>;
  97. pixelclk-active = <1>;
  98. };
  99. port {
  100. lcd_in: endpoint {
  101. remote-endpoint = <&dpi_out>;
  102. };
  103. };
  104. };
  105. /* fixed 12MHz oscillator */
  106. refclk: oscillator {
  107. #clock-cells = <0>;
  108. compatible = "fixed-clock";
  109. clock-frequency = <12000000>;
  110. };
  111. };
  112. &am43xx_pinmux {
  113. pinctrl-names = "default", "sleep";
  114. pinctrl-0 = <&wlan_pins_default>;
  115. pinctrl-1 = <&wlan_pins_sleep>;
  116. i2c0_pins: i2c0_pins {
  117. pinctrl-single,pins = <
  118. 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  119. 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  120. >;
  121. };
  122. i2c1_pins: i2c1_pins {
  123. pinctrl-single,pins = <
  124. 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  125. 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
  126. >;
  127. };
  128. mmc1_pins: pinmux_mmc1_pins {
  129. pinctrl-single,pins = <
  130. 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  131. >;
  132. };
  133. ecap0_pins: backlight_pins {
  134. pinctrl-single,pins = <
  135. 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  136. >;
  137. };
  138. pixcir_ts_pins: pixcir_ts_pins {
  139. pinctrl-single,pins = <
  140. 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
  141. >;
  142. };
  143. cpsw_default: cpsw_default {
  144. pinctrl-single,pins = <
  145. /* Slave 1 */
  146. 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
  147. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
  148. 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
  149. 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
  150. 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
  151. 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
  152. 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
  153. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
  154. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
  155. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
  156. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
  157. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
  158. >;
  159. };
  160. cpsw_sleep: cpsw_sleep {
  161. pinctrl-single,pins = <
  162. /* Slave 1 reset value */
  163. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  164. 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  165. 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  166. 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  167. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  168. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  169. 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  170. 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  171. 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  172. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  173. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  174. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  175. >;
  176. };
  177. davinci_mdio_default: davinci_mdio_default {
  178. pinctrl-single,pins = <
  179. /* MDIO */
  180. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  181. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  182. >;
  183. };
  184. davinci_mdio_sleep: davinci_mdio_sleep {
  185. pinctrl-single,pins = <
  186. /* MDIO reset value */
  187. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  188. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  189. >;
  190. };
  191. nand_flash_x8: nand_flash_x8 {
  192. pinctrl-single,pins = <
  193. 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
  194. 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  195. 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  196. 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  197. 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  198. 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  199. 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  200. 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  201. 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  202. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  203. 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
  204. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  205. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  206. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  207. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  208. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  209. >;
  210. };
  211. dss_pins: dss_pins {
  212. pinctrl-single,pins = <
  213. 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
  214. 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  215. 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  216. 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
  217. 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  218. 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  219. 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
  220. 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
  221. 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
  222. 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  223. 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  224. 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
  225. 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  226. 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  227. 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  228. 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
  229. 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  230. 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  231. 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  232. 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
  233. 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  234. 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  235. 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
  236. 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
  237. 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
  238. 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
  239. 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
  240. 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
  241. >;
  242. };
  243. lcd_pins: lcd_pins {
  244. pinctrl-single,pins = <
  245. /* GPIO 5_8 to select LCD / HDMI */
  246. 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
  247. >;
  248. };
  249. dcan0_default: dcan0_default_pins {
  250. pinctrl-single,pins = <
  251. 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
  252. 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
  253. >;
  254. };
  255. dcan1_default: dcan1_default_pins {
  256. pinctrl-single,pins = <
  257. 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
  258. 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
  259. >;
  260. };
  261. vpfe0_pins_default: vpfe0_pins_default {
  262. pinctrl-single,pins = <
  263. 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
  264. 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
  265. 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
  266. 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
  267. 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
  268. 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
  269. 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
  270. 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
  271. 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
  272. 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
  273. 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
  274. 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
  275. 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
  276. >;
  277. };
  278. vpfe0_pins_sleep: vpfe0_pins_sleep {
  279. pinctrl-single,pins = <
  280. 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
  281. 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
  282. 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
  283. 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
  284. 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
  285. 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
  286. 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
  287. 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
  288. 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
  289. 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
  290. 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
  291. 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
  292. 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
  293. >;
  294. };
  295. vpfe1_pins_default: vpfe1_pins_default {
  296. pinctrl-single,pins = <
  297. 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
  298. 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
  299. 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
  300. 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
  301. 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
  302. 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
  303. 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
  304. 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
  305. 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
  306. 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
  307. 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
  308. 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
  309. 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
  310. >;
  311. };
  312. vpfe1_pins_sleep: vpfe1_pins_sleep {
  313. pinctrl-single,pins = <
  314. 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
  315. 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
  316. 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
  317. 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
  318. 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
  319. 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
  320. 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
  321. 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
  322. 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
  323. 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
  324. 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
  325. 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
  326. 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
  327. >;
  328. };
  329. mmc3_pins_default: pinmux_mmc3_pins_default {
  330. pinctrl-single,pins = <
  331. 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
  332. 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
  333. 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
  334. 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
  335. 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
  336. 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
  337. >;
  338. };
  339. mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
  340. pinctrl-single,pins = <
  341. 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
  342. 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
  343. 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
  344. 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
  345. 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
  346. 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
  347. >;
  348. };
  349. wlan_pins_default: pinmux_wlan_pins_default {
  350. pinctrl-single,pins = <
  351. 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
  352. 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
  353. 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
  354. >;
  355. };
  356. wlan_pins_sleep: pinmux_wlan_pins_sleep {
  357. pinctrl-single,pins = <
  358. 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
  359. 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
  360. 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
  361. >;
  362. };
  363. uart3_pins: uart3_pins {
  364. pinctrl-single,pins = <
  365. 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
  366. 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
  367. 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
  368. 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
  369. >;
  370. };
  371. };
  372. &i2c0 {
  373. status = "okay";
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&i2c0_pins>;
  376. clock-frequency = <100000>;
  377. tps65218: tps65218@24 {
  378. reg = <0x24>;
  379. compatible = "ti,tps65218";
  380. interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
  381. interrupt-controller;
  382. #interrupt-cells = <2>;
  383. dcdc1: regulator-dcdc1 {
  384. compatible = "ti,tps65218-dcdc1";
  385. regulator-name = "vdd_core";
  386. regulator-min-microvolt = <912000>;
  387. regulator-max-microvolt = <1144000>;
  388. regulator-boot-on;
  389. regulator-always-on;
  390. };
  391. dcdc2: regulator-dcdc2 {
  392. compatible = "ti,tps65218-dcdc2";
  393. regulator-name = "vdd_mpu";
  394. regulator-min-microvolt = <912000>;
  395. regulator-max-microvolt = <1378000>;
  396. regulator-boot-on;
  397. regulator-always-on;
  398. };
  399. dcdc3: regulator-dcdc3 {
  400. compatible = "ti,tps65218-dcdc3";
  401. regulator-name = "vdcdc3";
  402. regulator-min-microvolt = <1500000>;
  403. regulator-max-microvolt = <1500000>;
  404. regulator-boot-on;
  405. regulator-always-on;
  406. };
  407. dcdc5: regulator-dcdc5 {
  408. compatible = "ti,tps65218-dcdc5";
  409. regulator-name = "v1_0bat";
  410. regulator-min-microvolt = <1000000>;
  411. regulator-max-microvolt = <1000000>;
  412. };
  413. dcdc6: regulator-dcdc6 {
  414. compatible = "ti,tps65218-dcdc6";
  415. regulator-name = "v1_8bat";
  416. regulator-min-microvolt = <1800000>;
  417. regulator-max-microvolt = <1800000>;
  418. };
  419. ldo1: regulator-ldo1 {
  420. compatible = "ti,tps65218-ldo1";
  421. regulator-min-microvolt = <1800000>;
  422. regulator-max-microvolt = <1800000>;
  423. regulator-boot-on;
  424. regulator-always-on;
  425. };
  426. };
  427. ov2659@30 {
  428. compatible = "ovti,ov2659";
  429. reg = <0x30>;
  430. clocks = <&refclk 0>;
  431. clock-names = "xvclk";
  432. port {
  433. ov2659_0: endpoint {
  434. remote-endpoint = <&vpfe1_ep>;
  435. link-frequencies = /bits/ 64 <70000000>;
  436. };
  437. };
  438. };
  439. };
  440. &i2c1 {
  441. status = "okay";
  442. pinctrl-names = "default";
  443. pinctrl-0 = <&i2c1_pins>;
  444. pixcir_ts@5c {
  445. compatible = "pixcir,pixcir_tangoc";
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&pixcir_ts_pins>;
  448. reg = <0x5c>;
  449. interrupt-parent = <&gpio3>;
  450. interrupts = <22 0>;
  451. attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  452. touchscreen-size-x = <1024>;
  453. touchscreen-size-y = <600>;
  454. };
  455. ov2659@30 {
  456. compatible = "ovti,ov2659";
  457. reg = <0x30>;
  458. clocks = <&refclk 0>;
  459. clock-names = "xvclk";
  460. port {
  461. ov2659_1: endpoint {
  462. remote-endpoint = <&vpfe0_ep>;
  463. link-frequencies = /bits/ 64 <70000000>;
  464. };
  465. };
  466. };
  467. };
  468. &epwmss0 {
  469. status = "okay";
  470. };
  471. &tscadc {
  472. status = "okay";
  473. adc {
  474. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  475. };
  476. };
  477. &ecap0 {
  478. status = "okay";
  479. pinctrl-names = "default";
  480. pinctrl-0 = <&ecap0_pins>;
  481. };
  482. &gpio0 {
  483. status = "okay";
  484. };
  485. &gpio1 {
  486. status = "okay";
  487. };
  488. &gpio3 {
  489. status = "okay";
  490. };
  491. &gpio4 {
  492. status = "okay";
  493. };
  494. &gpio5 {
  495. status = "okay";
  496. ti,no-reset-on-init;
  497. };
  498. &mmc1 {
  499. status = "okay";
  500. vmmc-supply = <&vmmcsd_fixed>;
  501. bus-width = <4>;
  502. pinctrl-names = "default";
  503. pinctrl-0 = <&mmc1_pins>;
  504. cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  505. };
  506. &mmc3 {
  507. /* disable MMC3 as SDIO is not supported in U-Boot */
  508. status = "disabled";
  509. /* these are on the crossbar and are outlined in the
  510. xbar-event-map element */
  511. dmas = <&edma 30
  512. &edma 31>;
  513. dma-names = "tx", "rx";
  514. vmmc-supply = <&vmmcwl_fixed>;
  515. bus-width = <4>;
  516. pinctrl-names = "default", "sleep";
  517. pinctrl-0 = <&mmc3_pins_default>;
  518. pinctrl-1 = <&mmc3_pins_sleep>;
  519. cap-power-off-card;
  520. keep-power-in-suspend;
  521. ti,non-removable;
  522. #address-cells = <1>;
  523. #size-cells = <0>;
  524. wlcore: wlcore@0 {
  525. compatible = "ti,wl1835";
  526. reg = <2>;
  527. interrupt-parent = <&gpio1>;
  528. interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
  529. };
  530. };
  531. &edma {
  532. ti,edma-xbar-event-map = /bits/ 16 <1 30
  533. 2 31>;
  534. };
  535. &uart3 {
  536. status = "okay";
  537. pinctrl-names = "default";
  538. pinctrl-0 = <&uart3_pins>;
  539. };
  540. &usb2_phy1 {
  541. status = "okay";
  542. };
  543. &usb1 {
  544. dr_mode = "peripheral";
  545. status = "okay";
  546. };
  547. &usb2_phy2 {
  548. status = "okay";
  549. };
  550. &usb2 {
  551. dr_mode = "host";
  552. status = "okay";
  553. };
  554. &mac {
  555. slaves = <1>;
  556. pinctrl-names = "default", "sleep";
  557. pinctrl-0 = <&cpsw_default>;
  558. pinctrl-1 = <&cpsw_sleep>;
  559. status = "okay";
  560. };
  561. &davinci_mdio {
  562. pinctrl-names = "default", "sleep";
  563. pinctrl-0 = <&davinci_mdio_default>;
  564. pinctrl-1 = <&davinci_mdio_sleep>;
  565. status = "okay";
  566. };
  567. &cpsw_emac0 {
  568. phy_id = <&davinci_mdio>, <0>;
  569. phy-mode = "rgmii";
  570. };
  571. &elm {
  572. status = "okay";
  573. };
  574. &gpmc {
  575. status = "okay";
  576. pinctrl-names = "default";
  577. pinctrl-0 = <&nand_flash_x8>;
  578. ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
  579. nand@0,0 {
  580. reg = <0 0 4>; /* device IO registers */
  581. ti,nand-ecc-opt = "bch16";
  582. ti,elm-id = <&elm>;
  583. nand-bus-width = <8>;
  584. gpmc,device-width = <1>;
  585. gpmc,sync-clk-ps = <0>;
  586. gpmc,cs-on-ns = <0>;
  587. gpmc,cs-rd-off-ns = <40>;
  588. gpmc,cs-wr-off-ns = <40>;
  589. gpmc,adv-on-ns = <0>;
  590. gpmc,adv-rd-off-ns = <25>;
  591. gpmc,adv-wr-off-ns = <25>;
  592. gpmc,we-on-ns = <0>;
  593. gpmc,we-off-ns = <20>;
  594. gpmc,oe-on-ns = <3>;
  595. gpmc,oe-off-ns = <30>;
  596. gpmc,access-ns = <30>;
  597. gpmc,rd-cycle-ns = <40>;
  598. gpmc,wr-cycle-ns = <40>;
  599. gpmc,wait-pin = <0>;
  600. gpmc,bus-turnaround-ns = <0>;
  601. gpmc,cycle2cycle-delay-ns = <0>;
  602. gpmc,clk-activation-ns = <0>;
  603. gpmc,wait-monitoring-ns = <0>;
  604. gpmc,wr-access-ns = <40>;
  605. gpmc,wr-data-mux-bus-ns = <0>;
  606. /* MTD partition table */
  607. /* All SPL-* partitions are sized to minimal length
  608. * which can be independently programmable. For
  609. * NAND flash this is equal to size of erase-block */
  610. #address-cells = <1>;
  611. #size-cells = <1>;
  612. partition@0 {
  613. label = "NAND.SPL";
  614. reg = <0x00000000 0x00040000>;
  615. };
  616. partition@1 {
  617. label = "NAND.SPL.backup1";
  618. reg = <0x00040000 0x00040000>;
  619. };
  620. partition@2 {
  621. label = "NAND.SPL.backup2";
  622. reg = <0x00080000 0x00040000>;
  623. };
  624. partition@3 {
  625. label = "NAND.SPL.backup3";
  626. reg = <0x000c0000 0x00040000>;
  627. };
  628. partition@4 {
  629. label = "NAND.u-boot-spl-os";
  630. reg = <0x00100000 0x00080000>;
  631. };
  632. partition@5 {
  633. label = "NAND.u-boot";
  634. reg = <0x00180000 0x00100000>;
  635. };
  636. partition@6 {
  637. label = "NAND.u-boot-env";
  638. reg = <0x00280000 0x00040000>;
  639. };
  640. partition@7 {
  641. label = "NAND.u-boot-env.backup1";
  642. reg = <0x002c0000 0x00040000>;
  643. };
  644. partition@8 {
  645. label = "NAND.kernel";
  646. reg = <0x00300000 0x00700000>;
  647. };
  648. partition@9 {
  649. label = "NAND.file-system";
  650. reg = <0x00a00000 0x1f600000>;
  651. };
  652. };
  653. };
  654. &dss {
  655. status = "ok";
  656. pinctrl-names = "default";
  657. pinctrl-0 = <&dss_pins>;
  658. port {
  659. dpi_out: endpoint@0 {
  660. remote-endpoint = <&lcd_in>;
  661. data-lines = <24>;
  662. };
  663. };
  664. };
  665. &dcan0 {
  666. pinctrl-names = "default";
  667. pinctrl-0 = <&dcan0_default>;
  668. status = "okay";
  669. };
  670. &dcan1 {
  671. pinctrl-names = "default";
  672. pinctrl-0 = <&dcan1_default>;
  673. status = "okay";
  674. };
  675. &vpfe0 {
  676. status = "okay";
  677. pinctrl-names = "default", "sleep";
  678. pinctrl-0 = <&vpfe0_pins_default>;
  679. pinctrl-1 = <&vpfe0_pins_sleep>;
  680. port {
  681. vpfe0_ep: endpoint {
  682. remote-endpoint = <&ov2659_1>;
  683. ti,am437x-vpfe-interface = <0>;
  684. bus-width = <8>;
  685. hsync-active = <0>;
  686. vsync-active = <0>;
  687. };
  688. };
  689. };
  690. &vpfe1 {
  691. status = "okay";
  692. pinctrl-names = "default", "sleep";
  693. pinctrl-0 = <&vpfe1_pins_default>;
  694. pinctrl-1 = <&vpfe1_pins_sleep>;
  695. port {
  696. vpfe1_ep: endpoint {
  697. remote-endpoint = <&ov2659_0>;
  698. ti,am437x-vpfe-interface = <0>;
  699. bus-width = <8>;
  700. hsync-active = <0>;
  701. vsync-active = <0>;
  702. };
  703. };
  704. };