am335x-rut.dts 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611
  1. /*
  2. * Copyright (C) 2014 DENX Software Engineering GmbH
  3. * Heiko Schocher <hs@denx.de>
  4. *
  5. * Based on:
  6. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /dts-v1/;
  13. #include "am33xx.dtsi"
  14. #include <dt-bindings/input/input.h>
  15. / {
  16. model = "RUT";
  17. compatible = "ti,am335x-evm", "ti,am33xx";
  18. buzzer {
  19. compatible = "pwm-beeper";
  20. pwms = <&ecap0 0 16000 0>;
  21. };
  22. chosen {
  23. stdout-path = &uart0;
  24. tick-timer = &timer2;
  25. };
  26. cpus {
  27. cpu@0 {
  28. cpu0-supply = <&dcdc2_reg>;
  29. };
  30. };
  31. gpio_keys: powerfail-keys {
  32. compatible = "gpio-keys";
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. autorepeat;
  36. pwr-fail0 {
  37. label = "power-fail";
  38. linux,code = <KEY_POWER>;
  39. gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
  40. gpio-key,wakeup;
  41. };
  42. pwr-fail1 {
  43. label = "power-fail-redundant";
  44. linux,code = <KEY_POWER>;
  45. gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  46. gpio-key,wakeup;
  47. };
  48. };
  49. leds {
  50. compatible = "gpio-leds";
  51. led_green {
  52. label = "rut:green:debug:run_mode";
  53. gpios = <&gpio3 20 1>;
  54. /* activelow = 1, default trigger heartbeat */
  55. };
  56. led_yellow {
  57. label = "rut:debug:yellow:osc_ch1";
  58. gpios = <&gpio0 17 1>;
  59. /* activelow = 1, default trigger mmc0 */
  60. };
  61. led_red {
  62. label = "rut:debug:red:osc_ch2";
  63. gpios = <&gpio0 16 1>;
  64. /* activelow = 1, default trigger debug_osc_ch2 */
  65. };
  66. /* optional */
  67. led_alive {
  68. label = "rut:alive";
  69. gpios = <&gpio0 15 1>;
  70. linux,default-trigger = "heartbeat";
  71. /* activelow = 1, default trigger heartbeat */
  72. };
  73. };
  74. memory {
  75. device_type = "memory";
  76. reg = <0x80000000 0x10000000>; /* 256 MB */
  77. };
  78. panel {
  79. compatible = "ti,tilcdc,panel";
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&lcd_pins_s0>;
  82. status = "okay";
  83. /* FORMIKE_KWH043ST20_F01 */
  84. panel-info {
  85. ac-bias = <255>;
  86. ac-bias-intrpt = <0>;
  87. dma-burst-sz = <16>;
  88. bpp = <16>;
  89. fdd = <0x80>;
  90. sync-edge = <0>;
  91. sync-ctrl = <1>;
  92. raster-order = <0>;
  93. fifo-th = <0>;
  94. tft-alt-mode = <0>;
  95. invert-pxl-clk = <1>;
  96. };
  97. display-timings {
  98. native-mode = <&timing1>;
  99. timing1: 480x800p60 {
  100. clock-frequency = <29925000>;
  101. hactive = <480>;
  102. vactive = <800>;
  103. hfront-porch = <50>;
  104. hback-porch = <50>;
  105. hsync-len = <50>;
  106. vback-porch = <50>;
  107. vfront-porch = <50>;
  108. vsync-len = <50>;
  109. hsync-active = <1>;
  110. vsync-active = <1>;
  111. };
  112. };
  113. };
  114. vmmc: fixedregulator3 {
  115. compatible = "regulator-fixed";
  116. regulator-name = "vmmc";
  117. regulator-min-microvolt = <3300000>;
  118. regulator-max-microvolt = <3300000>;
  119. };
  120. watchdog {
  121. compatible = "linux,wdt-gpio";
  122. gpios = <&gpio0 14 0>;
  123. hw_algo = "level";
  124. hw_margin_ms = <30000>;
  125. };
  126. };
  127. &aes {
  128. status = "okay";
  129. };
  130. &cppi41dma {
  131. status = "okay";
  132. };
  133. &cpsw_emac0 {
  134. phy_id = <&davinci_mdio>, <1>;
  135. phy-mode = "rmii";
  136. };
  137. &cpsw_emac1 {
  138. phy_id = <&davinci_mdio>, <0>;
  139. phy-mode = "rmii";
  140. };
  141. &davinci_mdio {
  142. pinctrl-names = "default", "sleep";
  143. pinctrl-0 = <&davinci_mdio_default>;
  144. pinctrl-1 = <&davinci_mdio_sleep>;
  145. status = "okay";
  146. gpios = <&gpio2 18 0>;
  147. ethernet_phy: ethernet-phy@1 {
  148. compatible = "ethernet-phy-id2000.5ce1";
  149. reg = <1>;
  150. natsemi,master_mode_fixup;
  151. };
  152. };
  153. &elm {
  154. status = "okay";
  155. };
  156. &epwmss0 {
  157. status = "okay";
  158. ecap0: ecap@48300100 {
  159. status = "okay";
  160. pinctrl-names = "default";
  161. pinctrl-0 = <&ecap0_pins>;
  162. };
  163. };
  164. &epwmss1 {
  165. status = "okay";
  166. ehrpwm1: ehrpwm@48302200 {
  167. status = "okay";
  168. pinctrl-names = "default";
  169. pinctrl-0 = <&epwmss1_pins>;
  170. };
  171. };
  172. &gpmc {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&nandflash_pins>;
  175. status = "okay";
  176. ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
  177. nand@0,0 {
  178. reg = <0 0 0>; /* CS0, offset 0 */
  179. nand-bus-width = <8>;
  180. ti,nand-ecc-opt = "bch8";
  181. gpmc,device-nand = "true";
  182. gpmc,device-width = <1>;
  183. gpmc,sync-clk-ps = <0>;
  184. gpmc,cs-on-ns = <0>;
  185. gpmc,cs-rd-off-ns = <57>;
  186. gpmc,cs-wr-off-ns = <57>;
  187. gpmc,adv-on-ns = <0>;
  188. gpmc,adv-rd-off-ns = <57>;
  189. gpmc,adv-wr-off-ns = <57>;
  190. gpmc,we-on-ns = <0>;
  191. gpmc,we-off-ns = <48>;
  192. gpmc,oe-on-ns = <0>;
  193. gpmc,oe-off-ns = <57>;
  194. gpmc,access-ns = <38>;
  195. gpmc,rd-cycle-ns = <67>;
  196. gpmc,wr-cycle-ns = <67>;
  197. gpmc,wait-on-read = "true";
  198. gpmc,wait-on-write = "true";
  199. gpmc,bus-turnaround-ns = <0>;
  200. gpmc,cycle2cycle-delay-ns = <0>;
  201. gpmc,clk-activation-ns = <0>;
  202. gpmc,wait-monitoring-ns = <0>;
  203. gpmc,wr-access-ns = <96>;
  204. gpmc,wr-data-mux-bus-ns = <0>;
  205. #address-cells = <1>;
  206. #size-cells = <1>;
  207. elm_id = <&elm>;
  208. };
  209. };
  210. &i2c0 {
  211. pinctrl-names = "default";
  212. pinctrl-0 = <&i2c0_pins>;
  213. clock-frequency = <400000>;
  214. status = "okay";
  215. eeprom: eeprom@50 {
  216. compatible = "atmel,24c128";
  217. reg = <0x50>;
  218. pagesize = <32>;
  219. };
  220. tps: tps@24 {
  221. reg = <0x24>;
  222. };
  223. };
  224. &i2c1 {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&i2c1_pins>;
  227. clock-frequency = <100000>;
  228. status = "okay";
  229. atmel: atmel_mxt_ts@4a {
  230. compatible = "atmel,maxtouch";
  231. reg = <0x4a>;
  232. interrupt-parent = <&gpio1>;
  233. interrupts = <28 8>;
  234. gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
  235. };
  236. temp@48 {
  237. compatible = "st,ds75";
  238. reg = <0x4c>;
  239. };
  240. };
  241. &lcdc {
  242. status = "okay";
  243. };
  244. &mac {
  245. pinctrl-names = "default", "sleep";
  246. pinctrl-0 = <&cpsw_default>;
  247. pinctrl-1 = <&cpsw_sleep>;
  248. status = "okay";
  249. };
  250. &mmc1 {
  251. vmmc-supply = <&vmmc>;
  252. pinctrl-names = "default";
  253. pinctrl-0 = <&mmc1_pins>;
  254. status = "okay";
  255. };
  256. &phy_sel {
  257. rmii-clock-ext;
  258. };
  259. &sham {
  260. status = "okay";
  261. };
  262. &spi0 {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&spi0_pins>;
  265. status = "okay";
  266. spi-flash@0 {
  267. #address-cells = <1>;
  268. #size-cells = <1>;
  269. compatible = "mx25l25635e";
  270. reg = <0>; /* Chip select 0 */
  271. spi-max-frequency = <24000000>;
  272. partition@0 {
  273. label = "dummy";
  274. reg = <0x0000000 0x8000>;
  275. };
  276. };
  277. };
  278. &spi1 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&spi1_pins>;
  281. status = "okay";
  282. lcd_init: lcd@0 {
  283. compatible = "formike,kwh043st20";
  284. reg = <0>;
  285. reset-gpios = <&gpio3 19 0>;
  286. spi-max-frequency = <1200000>;
  287. spi-cpol;
  288. spi-cpha;
  289. power-on-delay = <10>;
  290. reset-delay = <10>;
  291. };
  292. };
  293. /include/ "tps65217.dtsi"
  294. &tps {
  295. backlight0: backlight {
  296. isel = <1>; /* 1 - ISET1, 2 ISET2 */
  297. fdim = <1000>; /* TPS65217_BL_FDIM_100HZ */
  298. default-brightness = <80>;
  299. };
  300. regulators {
  301. dcdc1_reg: regulator@0 {
  302. regulator-always-on;
  303. };
  304. dcdc2_reg: regulator@1 {
  305. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  306. regulator-name = "vdd_mpu";
  307. regulator-min-microvolt = <925000>;
  308. regulator-max-microvolt = <1325000>;
  309. regulator-boot-on;
  310. regulator-always-on;
  311. };
  312. dcdc3_reg: regulator@2 {
  313. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  314. regulator-name = "vdd_core";
  315. regulator-min-microvolt = <925000>;
  316. regulator-max-microvolt = <1150000>;
  317. regulator-boot-on;
  318. regulator-always-on;
  319. };
  320. ldo1_reg: regulator@3 {
  321. regulator-always-on;
  322. };
  323. ldo2_reg: regulator@4 {
  324. regulator-always-on;
  325. };
  326. ldo3_reg: regulator@5 {
  327. regulator-always-on;
  328. };
  329. ldo4_reg: regulator@6 {
  330. regulator-always-on;
  331. };
  332. };
  333. };
  334. &tscadc {
  335. status = "okay";
  336. adc {
  337. ti,adc-channels = <4 5 6 7>;
  338. };
  339. };
  340. &uart0 {
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&uart0_pins>;
  343. status = "okay";
  344. };
  345. &usb {
  346. status = "okay";
  347. };
  348. &usb_ctrl_mod {
  349. status = "okay";
  350. };
  351. &usb0 {
  352. dr_mode = "device";
  353. status = "okay";
  354. };
  355. &usb0_phy {
  356. status = "okay";
  357. };
  358. &am33xx_pinmux {
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&clkout2_pin &gpio_pin>;
  361. clkout2_pin: pinmux_clkout2_pin {
  362. pinctrl-single,pins = <
  363. 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  364. >;
  365. };
  366. cpsw_default: cpsw_default {
  367. pinctrl-single,pins = <
  368. /* Slave 1 */
  369. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
  370. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.mii1_rxerr */
  371. 0x114 (MUX_MODE1) /* mii1_txen.mii1_txen */
  372. 0x124 (MUX_MODE1) /* mii1_txd1.mii1_txd1 */
  373. 0x128 (MUX_MODE1) /* mii1_txd0.mii1_txd0 */
  374. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.mii1_rxd1 */
  375. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.mii1_rxd0 */
  376. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
  377. >;
  378. };
  379. cpsw_sleep: cpsw_sleep {
  380. pinctrl-single,pins = <
  381. /* Slave 1 reset value */
  382. 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  383. 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  384. 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  385. 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  386. 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  387. 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  388. 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  389. 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  390. >;
  391. };
  392. davinci_mdio_default: davinci_mdio_default {
  393. pinctrl-single,pins = <
  394. /* MDIO */
  395. 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  396. 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  397. >;
  398. };
  399. davinci_mdio_sleep: davinci_mdio_sleep {
  400. pinctrl-single,pins = <
  401. /* MDIO reset value */
  402. 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  403. 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  404. >;
  405. };
  406. ecap0_pins: ecap_pins {
  407. pinctrl-single,pins = <
  408. 0x164 (MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 buzzer frequency: ecap.0 */
  409. >;
  410. };
  411. epwmss1_pins: epwmss_pins {
  412. pinctrl-single,pins = <
  413. 0x48 (PIN_INPUT | MUX_MODE7) /* gpmc_a2.gpio1_18 buzzer frequency: ehrpwm1A high-Z due to connected to ecap0 by R0469 */
  414. 0x4c (MUX_MODE6) /* gpmc_a3.ehrpwm1B buzzer volume pwm */
  415. >;
  416. };
  417. gpio_pin: gpio_pin {
  418. pinctrl-single,pins = <
  419. 0x6c (PIN_INPUT | MUX_MODE7) /* gpmc_a11.gpio1_27 PWR_FAIL_GPIO_SPARE */
  420. 0x78 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) /* gpmc_be1n.gpio1_28 TOUCH_CHANGE_N */
  421. 0x88 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) /* gpmc_csn3.gpio2_0 RUT_GPIO0_GPIO */
  422. 0x118 (PIN_INPUT | MUX_MODE7) /* gmii1_rxdv.gpio3_4 PWR_FAIL_GPIO */
  423. 0x11c (MUX_MODE7) /* mii1_txd3.gpio0_16 DEBUG_OSC_CH2_GPIO */
  424. 0x120 (MUX_MODE7) /* mii1_txd2.gpio0_17 DEBUG_OSC_CH1_GPIO */
  425. 0x134 (MUX_MODE7) /* gmii1_rxd3.gpio2_18 PHY_RSTn_GPIO */
  426. 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rxd2.gpio2_19 PHY_INT_GPIO */
  427. 0x180 (MUX_MODE7) /* uart1_rxd.gpio0_14 WATCHDOG_TRIGGER_GPIO */
  428. 0x184 (MUX_MODE7) /* uart1_txd.gpio0_15 ALIVE_LED_N_GPIO */
  429. 0x1a0 (MUX_MODE7) /* mcasp0_aclkr.gpio3_18 MAXTOUCH_RESET_GPIO */
  430. 0x1a4 (MUX_MODE7) /* mcasp0_fsr.gpio3_19 DISPLAY_RESET_GPIO */
  431. 0x1a8 (MUX_MODE7) /* mcasp0_axr1.gpio3_20 DEBUG_RUN_MODE_GPIO */
  432. 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 NORFLASH_WP_GPIO */
  433. 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
  434. >;
  435. };
  436. i2c0_pins: pinmux_i2c0_pins {
  437. pinctrl-single,pins = <
  438. 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  439. 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  440. >;
  441. };
  442. i2c1_pins: pinmux_i2c1_pins {
  443. pinctrl-single,pins = <
  444. 0x168 (PIN_INPUT | MUX_MODE3) /* uart0_ctsn.i2c1_sda */
  445. 0x16c (PIN_INPUT | MUX_MODE3) /* uart0.rtsn.i2c1_scl */
  446. >;
  447. };
  448. lcd_pins_s0: lcd_pins_s0 {
  449. pinctrl-single,pins = <
  450. 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
  451. 0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
  452. 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
  453. 0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
  454. 0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
  455. 0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
  456. 0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
  457. 0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
  458. 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  459. 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  460. 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  461. 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  462. 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  463. 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  464. 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  465. 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  466. 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  467. 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  468. 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  469. 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  470. 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  471. 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  472. 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  473. 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  474. 0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  475. 0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  476. 0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  477. 0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  478. >;
  479. };
  480. mmc1_pins: mmc1_pins {
  481. pinctrl-single,pins = <
  482. 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
  483. 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
  484. 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
  485. 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
  486. 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
  487. 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
  488. >;
  489. };
  490. nandflash_pins: pinmux_nandflash_pins {
  491. pinctrl-single,pins = <
  492. 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  493. 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  494. 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  495. 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  496. 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  497. 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  498. 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  499. 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  500. 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  501. 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
  502. 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  503. 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  504. 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  505. 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  506. 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  507. >;
  508. };
  509. spi0_pins: pinmux_spi0_pins {
  510. pinctrl-single,pins = <
  511. 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_sclk.spi0_sclk */
  512. 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
  513. 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d1.spi0_d1 */
  514. 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_CS0.spi0_CS0 */
  515. >;
  516. };
  517. spi1_pins: pinmux_spi1_pins {
  518. pinctrl-single,pins = <
  519. 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
  520. 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
  521. 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
  522. 0x19c (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
  523. >;
  524. };
  525. uart0_pins: pinmux_uart0_pins {
  526. pinctrl-single,pins = <
  527. 0x170 (PIN_INPUT | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  528. 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
  529. >;
  530. };
  531. };