imxfb.c 25 KB

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  1. /*
  2. * Freescale i.MX Frame Buffer device driver
  3. *
  4. * Copyright (C) 2004 Sascha Hauer, Pengutronix
  5. * Based on acornfb.c Copyright (C) Russell King.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive for
  9. * more details.
  10. *
  11. * Please direct your questions and comments on this driver to the following
  12. * email address:
  13. *
  14. * linux-arm-kernel@lists.arm.linux.org.uk
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/string.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/slab.h>
  22. #include <linux/mm.h>
  23. #include <linux/fb.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/cpufreq.h>
  28. #include <linux/clk.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/io.h>
  32. #include <linux/lcd.h>
  33. #include <linux/math64.h>
  34. #include <linux/of.h>
  35. #include <linux/of_device.h>
  36. #include <linux/regulator/consumer.h>
  37. #include <video/of_display_timing.h>
  38. #include <video/of_videomode.h>
  39. #include <video/videomode.h>
  40. #include <linux/platform_data/video-imxfb.h>
  41. /*
  42. * Complain if VAR is out of range.
  43. */
  44. #define DEBUG_VAR 1
  45. #define DRIVER_NAME "imx-fb"
  46. #define LCDC_SSA 0x00
  47. #define LCDC_SIZE 0x04
  48. #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
  49. #define YMAX_MASK_IMX1 0x1ff
  50. #define YMAX_MASK_IMX21 0x3ff
  51. #define LCDC_VPW 0x08
  52. #define VPW_VPW(x) ((x) & 0x3ff)
  53. #define LCDC_CPOS 0x0C
  54. #define CPOS_CC1 (1<<31)
  55. #define CPOS_CC0 (1<<30)
  56. #define CPOS_OP (1<<28)
  57. #define CPOS_CXP(x) (((x) & 3ff) << 16)
  58. #define LCDC_LCWHB 0x10
  59. #define LCWHB_BK_EN (1<<31)
  60. #define LCWHB_CW(w) (((w) & 0x1f) << 24)
  61. #define LCWHB_CH(h) (((h) & 0x1f) << 16)
  62. #define LCWHB_BD(x) ((x) & 0xff)
  63. #define LCDC_LCHCC 0x14
  64. #define LCDC_PCR 0x18
  65. #define LCDC_HCR 0x1C
  66. #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
  67. #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
  68. #define HCR_H_WAIT_2(x) ((x) & 0xff)
  69. #define LCDC_VCR 0x20
  70. #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
  71. #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
  72. #define VCR_V_WAIT_2(x) ((x) & 0xff)
  73. #define LCDC_POS 0x24
  74. #define POS_POS(x) ((x) & 1f)
  75. #define LCDC_LSCR1 0x28
  76. /* bit fields in imxfb.h */
  77. #define LCDC_PWMR 0x2C
  78. /* bit fields in imxfb.h */
  79. #define LCDC_DMACR 0x30
  80. /* bit fields in imxfb.h */
  81. #define LCDC_RMCR 0x34
  82. #define RMCR_LCDC_EN_MX1 (1<<1)
  83. #define RMCR_SELF_REF (1<<0)
  84. #define LCDC_LCDICR 0x38
  85. #define LCDICR_INT_SYN (1<<2)
  86. #define LCDICR_INT_CON (1)
  87. #define LCDC_LCDISR 0x40
  88. #define LCDISR_UDR_ERR (1<<3)
  89. #define LCDISR_ERR_RES (1<<2)
  90. #define LCDISR_EOF (1<<1)
  91. #define LCDISR_BOF (1<<0)
  92. #define IMXFB_LSCR1_DEFAULT 0x00120300
  93. /* Used fb-mode. Can be set on kernel command line, therefore file-static. */
  94. static const char *fb_mode;
  95. /*
  96. * These are the bitfields for each
  97. * display depth that we support.
  98. */
  99. struct imxfb_rgb {
  100. struct fb_bitfield red;
  101. struct fb_bitfield green;
  102. struct fb_bitfield blue;
  103. struct fb_bitfield transp;
  104. };
  105. enum imxfb_type {
  106. IMX1_FB,
  107. IMX21_FB,
  108. };
  109. struct imxfb_info {
  110. struct platform_device *pdev;
  111. void __iomem *regs;
  112. struct clk *clk_ipg;
  113. struct clk *clk_ahb;
  114. struct clk *clk_per;
  115. enum imxfb_type devtype;
  116. bool enabled;
  117. /*
  118. * These are the addresses we mapped
  119. * the framebuffer memory region to.
  120. */
  121. dma_addr_t map_dma;
  122. u_int map_size;
  123. u_int palette_size;
  124. dma_addr_t dbar1;
  125. dma_addr_t dbar2;
  126. u_int pcr;
  127. u_int pwmr;
  128. u_int lscr1;
  129. u_int dmacr;
  130. bool cmap_inverse;
  131. bool cmap_static;
  132. struct imx_fb_videomode *mode;
  133. int num_modes;
  134. struct regulator *lcd_pwr;
  135. };
  136. static const struct platform_device_id imxfb_devtype[] = {
  137. {
  138. .name = "imx1-fb",
  139. .driver_data = IMX1_FB,
  140. }, {
  141. .name = "imx21-fb",
  142. .driver_data = IMX21_FB,
  143. }, {
  144. /* sentinel */
  145. }
  146. };
  147. MODULE_DEVICE_TABLE(platform, imxfb_devtype);
  148. static const struct of_device_id imxfb_of_dev_id[] = {
  149. {
  150. .compatible = "fsl,imx1-fb",
  151. .data = &imxfb_devtype[IMX1_FB],
  152. }, {
  153. .compatible = "fsl,imx21-fb",
  154. .data = &imxfb_devtype[IMX21_FB],
  155. }, {
  156. /* sentinel */
  157. }
  158. };
  159. MODULE_DEVICE_TABLE(of, imxfb_of_dev_id);
  160. static inline int is_imx1_fb(struct imxfb_info *fbi)
  161. {
  162. return fbi->devtype == IMX1_FB;
  163. }
  164. #define IMX_NAME "IMX"
  165. /*
  166. * Minimum X and Y resolutions
  167. */
  168. #define MIN_XRES 64
  169. #define MIN_YRES 64
  170. /* Actually this really is 18bit support, the lowest 2 bits of each colour
  171. * are unused in hardware. We claim to have 24bit support to make software
  172. * like X work, which does not support 18bit.
  173. */
  174. static struct imxfb_rgb def_rgb_18 = {
  175. .red = {.offset = 16, .length = 8,},
  176. .green = {.offset = 8, .length = 8,},
  177. .blue = {.offset = 0, .length = 8,},
  178. .transp = {.offset = 0, .length = 0,},
  179. };
  180. static struct imxfb_rgb def_rgb_16_tft = {
  181. .red = {.offset = 11, .length = 5,},
  182. .green = {.offset = 5, .length = 6,},
  183. .blue = {.offset = 0, .length = 5,},
  184. .transp = {.offset = 0, .length = 0,},
  185. };
  186. static struct imxfb_rgb def_rgb_16_stn = {
  187. .red = {.offset = 8, .length = 4,},
  188. .green = {.offset = 4, .length = 4,},
  189. .blue = {.offset = 0, .length = 4,},
  190. .transp = {.offset = 0, .length = 0,},
  191. };
  192. static struct imxfb_rgb def_rgb_8 = {
  193. .red = {.offset = 0, .length = 8,},
  194. .green = {.offset = 0, .length = 8,},
  195. .blue = {.offset = 0, .length = 8,},
  196. .transp = {.offset = 0, .length = 0,},
  197. };
  198. static int imxfb_activate_var(struct fb_var_screeninfo *var,
  199. struct fb_info *info);
  200. static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  201. {
  202. chan &= 0xffff;
  203. chan >>= 16 - bf->length;
  204. return chan << bf->offset;
  205. }
  206. static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
  207. u_int trans, struct fb_info *info)
  208. {
  209. struct imxfb_info *fbi = info->par;
  210. u_int val, ret = 1;
  211. #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
  212. if (regno < fbi->palette_size) {
  213. val = (CNVT_TOHW(red, 4) << 8) |
  214. (CNVT_TOHW(green,4) << 4) |
  215. CNVT_TOHW(blue, 4);
  216. writel(val, fbi->regs + 0x800 + (regno << 2));
  217. ret = 0;
  218. }
  219. return ret;
  220. }
  221. static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  222. u_int trans, struct fb_info *info)
  223. {
  224. struct imxfb_info *fbi = info->par;
  225. unsigned int val;
  226. int ret = 1;
  227. /*
  228. * If inverse mode was selected, invert all the colours
  229. * rather than the register number. The register number
  230. * is what you poke into the framebuffer to produce the
  231. * colour you requested.
  232. */
  233. if (fbi->cmap_inverse) {
  234. red = 0xffff - red;
  235. green = 0xffff - green;
  236. blue = 0xffff - blue;
  237. }
  238. /*
  239. * If greyscale is true, then we convert the RGB value
  240. * to greyscale no mater what visual we are using.
  241. */
  242. if (info->var.grayscale)
  243. red = green = blue = (19595 * red + 38470 * green +
  244. 7471 * blue) >> 16;
  245. switch (info->fix.visual) {
  246. case FB_VISUAL_TRUECOLOR:
  247. /*
  248. * 12 or 16-bit True Colour. We encode the RGB value
  249. * according to the RGB bitfield information.
  250. */
  251. if (regno < 16) {
  252. u32 *pal = info->pseudo_palette;
  253. val = chan_to_field(red, &info->var.red);
  254. val |= chan_to_field(green, &info->var.green);
  255. val |= chan_to_field(blue, &info->var.blue);
  256. pal[regno] = val;
  257. ret = 0;
  258. }
  259. break;
  260. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  261. case FB_VISUAL_PSEUDOCOLOR:
  262. ret = imxfb_setpalettereg(regno, red, green, blue, trans, info);
  263. break;
  264. }
  265. return ret;
  266. }
  267. static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
  268. {
  269. struct imx_fb_videomode *m;
  270. int i;
  271. if (!fb_mode)
  272. return &fbi->mode[0];
  273. for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
  274. if (!strcmp(m->mode.name, fb_mode))
  275. return m;
  276. }
  277. return NULL;
  278. }
  279. /*
  280. * imxfb_check_var():
  281. * Round up in the following order: bits_per_pixel, xres,
  282. * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  283. * bitfields, horizontal timing, vertical timing.
  284. */
  285. static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  286. {
  287. struct imxfb_info *fbi = info->par;
  288. struct imxfb_rgb *rgb;
  289. const struct imx_fb_videomode *imxfb_mode;
  290. unsigned long lcd_clk;
  291. unsigned long long tmp;
  292. u32 pcr = 0;
  293. if (var->xres < MIN_XRES)
  294. var->xres = MIN_XRES;
  295. if (var->yres < MIN_YRES)
  296. var->yres = MIN_YRES;
  297. imxfb_mode = imxfb_find_mode(fbi);
  298. if (!imxfb_mode)
  299. return -EINVAL;
  300. var->xres = imxfb_mode->mode.xres;
  301. var->yres = imxfb_mode->mode.yres;
  302. var->bits_per_pixel = imxfb_mode->bpp;
  303. var->pixclock = imxfb_mode->mode.pixclock;
  304. var->hsync_len = imxfb_mode->mode.hsync_len;
  305. var->left_margin = imxfb_mode->mode.left_margin;
  306. var->right_margin = imxfb_mode->mode.right_margin;
  307. var->vsync_len = imxfb_mode->mode.vsync_len;
  308. var->upper_margin = imxfb_mode->mode.upper_margin;
  309. var->lower_margin = imxfb_mode->mode.lower_margin;
  310. var->sync = imxfb_mode->mode.sync;
  311. var->xres_virtual = max(var->xres_virtual, var->xres);
  312. var->yres_virtual = max(var->yres_virtual, var->yres);
  313. pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
  314. lcd_clk = clk_get_rate(fbi->clk_per);
  315. tmp = var->pixclock * (unsigned long long)lcd_clk;
  316. do_div(tmp, 1000000);
  317. if (do_div(tmp, 1000000) > 500000)
  318. tmp++;
  319. pcr = (unsigned int)tmp;
  320. if (--pcr > 0x3F) {
  321. pcr = 0x3F;
  322. printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
  323. lcd_clk / pcr);
  324. }
  325. switch (var->bits_per_pixel) {
  326. case 32:
  327. pcr |= PCR_BPIX_18;
  328. rgb = &def_rgb_18;
  329. break;
  330. case 16:
  331. default:
  332. if (is_imx1_fb(fbi))
  333. pcr |= PCR_BPIX_12;
  334. else
  335. pcr |= PCR_BPIX_16;
  336. if (imxfb_mode->pcr & PCR_TFT)
  337. rgb = &def_rgb_16_tft;
  338. else
  339. rgb = &def_rgb_16_stn;
  340. break;
  341. case 8:
  342. pcr |= PCR_BPIX_8;
  343. rgb = &def_rgb_8;
  344. break;
  345. }
  346. /* add sync polarities */
  347. pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
  348. fbi->pcr = pcr;
  349. /*
  350. * Copy the RGB parameters for this display
  351. * from the machine specific parameters.
  352. */
  353. var->red = rgb->red;
  354. var->green = rgb->green;
  355. var->blue = rgb->blue;
  356. var->transp = rgb->transp;
  357. pr_debug("RGBT length = %d:%d:%d:%d\n",
  358. var->red.length, var->green.length, var->blue.length,
  359. var->transp.length);
  360. pr_debug("RGBT offset = %d:%d:%d:%d\n",
  361. var->red.offset, var->green.offset, var->blue.offset,
  362. var->transp.offset);
  363. return 0;
  364. }
  365. /*
  366. * imxfb_set_par():
  367. * Set the user defined part of the display for the specified console
  368. */
  369. static int imxfb_set_par(struct fb_info *info)
  370. {
  371. struct imxfb_info *fbi = info->par;
  372. struct fb_var_screeninfo *var = &info->var;
  373. if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32)
  374. info->fix.visual = FB_VISUAL_TRUECOLOR;
  375. else if (!fbi->cmap_static)
  376. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  377. else {
  378. /*
  379. * Some people have weird ideas about wanting static
  380. * pseudocolor maps. I suspect their user space
  381. * applications are broken.
  382. */
  383. info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
  384. }
  385. info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
  386. fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
  387. imxfb_activate_var(var, info);
  388. return 0;
  389. }
  390. static int imxfb_enable_controller(struct imxfb_info *fbi)
  391. {
  392. int ret;
  393. if (fbi->enabled)
  394. return 0;
  395. pr_debug("Enabling LCD controller\n");
  396. writel(fbi->map_dma, fbi->regs + LCDC_SSA);
  397. /* panning offset 0 (0 pixel offset) */
  398. writel(0x00000000, fbi->regs + LCDC_POS);
  399. /* disable hardware cursor */
  400. writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
  401. fbi->regs + LCDC_CPOS);
  402. /*
  403. * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt
  404. * on other SoCs
  405. */
  406. writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
  407. ret = clk_prepare_enable(fbi->clk_ipg);
  408. if (ret)
  409. goto err_enable_ipg;
  410. ret = clk_prepare_enable(fbi->clk_ahb);
  411. if (ret)
  412. goto err_enable_ahb;
  413. ret = clk_prepare_enable(fbi->clk_per);
  414. if (ret)
  415. goto err_enable_per;
  416. fbi->enabled = true;
  417. return 0;
  418. err_enable_per:
  419. clk_disable_unprepare(fbi->clk_ahb);
  420. err_enable_ahb:
  421. clk_disable_unprepare(fbi->clk_ipg);
  422. err_enable_ipg:
  423. writel(0, fbi->regs + LCDC_RMCR);
  424. return ret;
  425. }
  426. static void imxfb_disable_controller(struct imxfb_info *fbi)
  427. {
  428. if (!fbi->enabled)
  429. return;
  430. pr_debug("Disabling LCD controller\n");
  431. clk_disable_unprepare(fbi->clk_per);
  432. clk_disable_unprepare(fbi->clk_ahb);
  433. clk_disable_unprepare(fbi->clk_ipg);
  434. fbi->enabled = false;
  435. writel(0, fbi->regs + LCDC_RMCR);
  436. }
  437. static int imxfb_blank(int blank, struct fb_info *info)
  438. {
  439. struct imxfb_info *fbi = info->par;
  440. pr_debug("imxfb_blank: blank=%d\n", blank);
  441. switch (blank) {
  442. case FB_BLANK_POWERDOWN:
  443. case FB_BLANK_VSYNC_SUSPEND:
  444. case FB_BLANK_HSYNC_SUSPEND:
  445. case FB_BLANK_NORMAL:
  446. imxfb_disable_controller(fbi);
  447. break;
  448. case FB_BLANK_UNBLANK:
  449. return imxfb_enable_controller(fbi);
  450. }
  451. return 0;
  452. }
  453. static struct fb_ops imxfb_ops = {
  454. .owner = THIS_MODULE,
  455. .fb_check_var = imxfb_check_var,
  456. .fb_set_par = imxfb_set_par,
  457. .fb_setcolreg = imxfb_setcolreg,
  458. .fb_fillrect = cfb_fillrect,
  459. .fb_copyarea = cfb_copyarea,
  460. .fb_imageblit = cfb_imageblit,
  461. .fb_blank = imxfb_blank,
  462. };
  463. /*
  464. * imxfb_activate_var():
  465. * Configures LCD Controller based on entries in var parameter. Settings are
  466. * only written to the controller if changes were made.
  467. */
  468. static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info)
  469. {
  470. struct imxfb_info *fbi = info->par;
  471. u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21;
  472. pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
  473. var->xres, var->hsync_len,
  474. var->left_margin, var->right_margin);
  475. pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
  476. var->yres, var->vsync_len,
  477. var->upper_margin, var->lower_margin);
  478. #if DEBUG_VAR
  479. if (var->xres < 16 || var->xres > 1024)
  480. printk(KERN_ERR "%s: invalid xres %d\n",
  481. info->fix.id, var->xres);
  482. if (var->hsync_len < 1 || var->hsync_len > 64)
  483. printk(KERN_ERR "%s: invalid hsync_len %d\n",
  484. info->fix.id, var->hsync_len);
  485. if (var->left_margin > 255)
  486. printk(KERN_ERR "%s: invalid left_margin %d\n",
  487. info->fix.id, var->left_margin);
  488. if (var->right_margin > 255)
  489. printk(KERN_ERR "%s: invalid right_margin %d\n",
  490. info->fix.id, var->right_margin);
  491. if (var->yres < 1 || var->yres > ymax_mask)
  492. printk(KERN_ERR "%s: invalid yres %d\n",
  493. info->fix.id, var->yres);
  494. if (var->vsync_len > 100)
  495. printk(KERN_ERR "%s: invalid vsync_len %d\n",
  496. info->fix.id, var->vsync_len);
  497. if (var->upper_margin > 63)
  498. printk(KERN_ERR "%s: invalid upper_margin %d\n",
  499. info->fix.id, var->upper_margin);
  500. if (var->lower_margin > 255)
  501. printk(KERN_ERR "%s: invalid lower_margin %d\n",
  502. info->fix.id, var->lower_margin);
  503. #endif
  504. /* physical screen start address */
  505. writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
  506. fbi->regs + LCDC_VPW);
  507. writel(HCR_H_WIDTH(var->hsync_len - 1) |
  508. HCR_H_WAIT_1(var->right_margin - 1) |
  509. HCR_H_WAIT_2(var->left_margin - 3),
  510. fbi->regs + LCDC_HCR);
  511. writel(VCR_V_WIDTH(var->vsync_len) |
  512. VCR_V_WAIT_1(var->lower_margin) |
  513. VCR_V_WAIT_2(var->upper_margin),
  514. fbi->regs + LCDC_VCR);
  515. writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask),
  516. fbi->regs + LCDC_SIZE);
  517. writel(fbi->pcr, fbi->regs + LCDC_PCR);
  518. if (fbi->pwmr)
  519. writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
  520. writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
  521. /* dmacr = 0 is no valid value, as we need DMA control marks. */
  522. if (fbi->dmacr)
  523. writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
  524. return 0;
  525. }
  526. static int imxfb_init_fbinfo(struct platform_device *pdev)
  527. {
  528. struct imx_fb_platform_data *pdata = dev_get_platdata(&pdev->dev);
  529. struct fb_info *info = dev_get_drvdata(&pdev->dev);
  530. struct imxfb_info *fbi = info->par;
  531. struct device_node *np;
  532. pr_debug("%s\n",__func__);
  533. info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
  534. if (!info->pseudo_palette)
  535. return -ENOMEM;
  536. memset(fbi, 0, sizeof(struct imxfb_info));
  537. fbi->devtype = pdev->id_entry->driver_data;
  538. strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
  539. info->fix.type = FB_TYPE_PACKED_PIXELS;
  540. info->fix.type_aux = 0;
  541. info->fix.xpanstep = 0;
  542. info->fix.ypanstep = 0;
  543. info->fix.ywrapstep = 0;
  544. info->fix.accel = FB_ACCEL_NONE;
  545. info->var.nonstd = 0;
  546. info->var.activate = FB_ACTIVATE_NOW;
  547. info->var.height = -1;
  548. info->var.width = -1;
  549. info->var.accel_flags = 0;
  550. info->var.vmode = FB_VMODE_NONINTERLACED;
  551. info->fbops = &imxfb_ops;
  552. info->flags = FBINFO_FLAG_DEFAULT |
  553. FBINFO_READS_FAST;
  554. if (pdata) {
  555. fbi->lscr1 = pdata->lscr1;
  556. fbi->dmacr = pdata->dmacr;
  557. fbi->pwmr = pdata->pwmr;
  558. } else {
  559. np = pdev->dev.of_node;
  560. info->var.grayscale = of_property_read_bool(np,
  561. "cmap-greyscale");
  562. fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse");
  563. fbi->cmap_static = of_property_read_bool(np, "cmap-static");
  564. fbi->lscr1 = IMXFB_LSCR1_DEFAULT;
  565. of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr);
  566. of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1);
  567. of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr);
  568. }
  569. return 0;
  570. }
  571. static int imxfb_of_read_mode(struct device *dev, struct device_node *np,
  572. struct imx_fb_videomode *imxfb_mode)
  573. {
  574. int ret;
  575. struct fb_videomode *of_mode = &imxfb_mode->mode;
  576. u32 bpp;
  577. u32 pcr;
  578. ret = of_property_read_string(np, "model", &of_mode->name);
  579. if (ret)
  580. of_mode->name = NULL;
  581. ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE);
  582. if (ret) {
  583. dev_err(dev, "Failed to get videomode from DT\n");
  584. return ret;
  585. }
  586. ret = of_property_read_u32(np, "bits-per-pixel", &bpp);
  587. ret |= of_property_read_u32(np, "fsl,pcr", &pcr);
  588. if (ret) {
  589. dev_err(dev, "Failed to read bpp and pcr from DT\n");
  590. return -EINVAL;
  591. }
  592. if (bpp < 1 || bpp > 255) {
  593. dev_err(dev, "Bits per pixel have to be between 1 and 255\n");
  594. return -EINVAL;
  595. }
  596. imxfb_mode->bpp = bpp;
  597. imxfb_mode->pcr = pcr;
  598. return 0;
  599. }
  600. static int imxfb_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi)
  601. {
  602. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  603. if (!fi || fi->par == fbi)
  604. return 1;
  605. return 0;
  606. }
  607. static int imxfb_lcd_get_contrast(struct lcd_device *lcddev)
  608. {
  609. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  610. return fbi->pwmr & 0xff;
  611. }
  612. static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast)
  613. {
  614. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  615. if (fbi->pwmr && fbi->enabled) {
  616. if (contrast > 255)
  617. contrast = 255;
  618. else if (contrast < 0)
  619. contrast = 0;
  620. fbi->pwmr &= ~0xff;
  621. fbi->pwmr |= contrast;
  622. writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
  623. }
  624. return 0;
  625. }
  626. static int imxfb_lcd_get_power(struct lcd_device *lcddev)
  627. {
  628. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  629. if (!IS_ERR(fbi->lcd_pwr) &&
  630. !regulator_is_enabled(fbi->lcd_pwr))
  631. return FB_BLANK_POWERDOWN;
  632. return FB_BLANK_UNBLANK;
  633. }
  634. static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power)
  635. {
  636. struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
  637. if (!IS_ERR(fbi->lcd_pwr)) {
  638. if (power == FB_BLANK_UNBLANK)
  639. return regulator_enable(fbi->lcd_pwr);
  640. else
  641. return regulator_disable(fbi->lcd_pwr);
  642. }
  643. return 0;
  644. }
  645. static struct lcd_ops imxfb_lcd_ops = {
  646. .check_fb = imxfb_lcd_check_fb,
  647. .get_contrast = imxfb_lcd_get_contrast,
  648. .set_contrast = imxfb_lcd_set_contrast,
  649. .get_power = imxfb_lcd_get_power,
  650. .set_power = imxfb_lcd_set_power,
  651. };
  652. static int imxfb_setup(void)
  653. {
  654. char *opt, *options = NULL;
  655. if (fb_get_options("imxfb", &options))
  656. return -ENODEV;
  657. if (!options || !*options)
  658. return 0;
  659. while ((opt = strsep(&options, ",")) != NULL) {
  660. if (!*opt)
  661. continue;
  662. else
  663. fb_mode = opt;
  664. }
  665. return 0;
  666. }
  667. static int imxfb_probe(struct platform_device *pdev)
  668. {
  669. struct imxfb_info *fbi;
  670. struct lcd_device *lcd;
  671. struct fb_info *info;
  672. struct imx_fb_platform_data *pdata;
  673. struct resource *res;
  674. struct imx_fb_videomode *m;
  675. const struct of_device_id *of_id;
  676. int ret, i;
  677. int bytes_per_pixel;
  678. dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
  679. ret = imxfb_setup();
  680. if (ret < 0)
  681. return ret;
  682. of_id = of_match_device(imxfb_of_dev_id, &pdev->dev);
  683. if (of_id)
  684. pdev->id_entry = of_id->data;
  685. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  686. if (!res)
  687. return -ENODEV;
  688. pdata = dev_get_platdata(&pdev->dev);
  689. info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
  690. if (!info)
  691. return -ENOMEM;
  692. fbi = info->par;
  693. platform_set_drvdata(pdev, info);
  694. ret = imxfb_init_fbinfo(pdev);
  695. if (ret < 0)
  696. goto failed_init;
  697. if (pdata) {
  698. if (!fb_mode)
  699. fb_mode = pdata->mode[0].mode.name;
  700. fbi->mode = pdata->mode;
  701. fbi->num_modes = pdata->num_modes;
  702. } else {
  703. struct device_node *display_np;
  704. fb_mode = NULL;
  705. display_np = of_parse_phandle(pdev->dev.of_node, "display", 0);
  706. if (!display_np) {
  707. dev_err(&pdev->dev, "No display defined in devicetree\n");
  708. ret = -EINVAL;
  709. goto failed_of_parse;
  710. }
  711. /*
  712. * imxfb does not support more modes, we choose only the native
  713. * mode.
  714. */
  715. fbi->num_modes = 1;
  716. fbi->mode = devm_kzalloc(&pdev->dev,
  717. sizeof(struct imx_fb_videomode), GFP_KERNEL);
  718. if (!fbi->mode) {
  719. ret = -ENOMEM;
  720. goto failed_of_parse;
  721. }
  722. ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode);
  723. if (ret)
  724. goto failed_of_parse;
  725. }
  726. /* Calculate maximum bytes used per pixel. In most cases this should
  727. * be the same as m->bpp/8 */
  728. m = &fbi->mode[0];
  729. bytes_per_pixel = (m->bpp + 7) / 8;
  730. for (i = 0; i < fbi->num_modes; i++, m++)
  731. info->fix.smem_len = max_t(size_t, info->fix.smem_len,
  732. m->mode.xres * m->mode.yres * bytes_per_pixel);
  733. res = request_mem_region(res->start, resource_size(res),
  734. DRIVER_NAME);
  735. if (!res) {
  736. ret = -EBUSY;
  737. goto failed_req;
  738. }
  739. fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  740. if (IS_ERR(fbi->clk_ipg)) {
  741. ret = PTR_ERR(fbi->clk_ipg);
  742. goto failed_getclock;
  743. }
  744. /*
  745. * The LCDC controller does not have an enable bit. The
  746. * controller starts directly when the clocks are enabled.
  747. * If the clocks are enabled when the controller is not yet
  748. * programmed with proper register values (enabled at the
  749. * bootloader, for example) then it just goes into some undefined
  750. * state.
  751. * To avoid this issue, let's enable and disable LCDC IPG clock
  752. * so that we force some kind of 'reset' to the LCDC block.
  753. */
  754. ret = clk_prepare_enable(fbi->clk_ipg);
  755. if (ret)
  756. goto failed_getclock;
  757. clk_disable_unprepare(fbi->clk_ipg);
  758. fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  759. if (IS_ERR(fbi->clk_ahb)) {
  760. ret = PTR_ERR(fbi->clk_ahb);
  761. goto failed_getclock;
  762. }
  763. fbi->clk_per = devm_clk_get(&pdev->dev, "per");
  764. if (IS_ERR(fbi->clk_per)) {
  765. ret = PTR_ERR(fbi->clk_per);
  766. goto failed_getclock;
  767. }
  768. fbi->regs = ioremap(res->start, resource_size(res));
  769. if (fbi->regs == NULL) {
  770. dev_err(&pdev->dev, "Cannot map frame buffer registers\n");
  771. ret = -ENOMEM;
  772. goto failed_ioremap;
  773. }
  774. fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
  775. info->screen_base = dma_alloc_wc(&pdev->dev, fbi->map_size,
  776. &fbi->map_dma, GFP_KERNEL);
  777. if (!info->screen_base) {
  778. dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
  779. ret = -ENOMEM;
  780. goto failed_map;
  781. }
  782. info->fix.smem_start = fbi->map_dma;
  783. if (pdata && pdata->init) {
  784. ret = pdata->init(fbi->pdev);
  785. if (ret)
  786. goto failed_platform_init;
  787. }
  788. INIT_LIST_HEAD(&info->modelist);
  789. for (i = 0; i < fbi->num_modes; i++)
  790. fb_add_videomode(&fbi->mode[i].mode, &info->modelist);
  791. /*
  792. * This makes sure that our colour bitfield
  793. * descriptors are correctly initialised.
  794. */
  795. imxfb_check_var(&info->var, info);
  796. ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
  797. if (ret < 0)
  798. goto failed_cmap;
  799. imxfb_set_par(info);
  800. ret = register_framebuffer(info);
  801. if (ret < 0) {
  802. dev_err(&pdev->dev, "failed to register framebuffer\n");
  803. goto failed_register;
  804. }
  805. fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd");
  806. if (IS_ERR(fbi->lcd_pwr) && (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER)) {
  807. ret = -EPROBE_DEFER;
  808. goto failed_lcd;
  809. }
  810. lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi,
  811. &imxfb_lcd_ops);
  812. if (IS_ERR(lcd)) {
  813. ret = PTR_ERR(lcd);
  814. goto failed_lcd;
  815. }
  816. lcd->props.max_contrast = 0xff;
  817. imxfb_enable_controller(fbi);
  818. fbi->pdev = pdev;
  819. return 0;
  820. failed_lcd:
  821. unregister_framebuffer(info);
  822. failed_register:
  823. fb_dealloc_cmap(&info->cmap);
  824. failed_cmap:
  825. if (pdata && pdata->exit)
  826. pdata->exit(fbi->pdev);
  827. failed_platform_init:
  828. dma_free_wc(&pdev->dev, fbi->map_size, info->screen_base,
  829. fbi->map_dma);
  830. failed_map:
  831. iounmap(fbi->regs);
  832. failed_ioremap:
  833. failed_getclock:
  834. release_mem_region(res->start, resource_size(res));
  835. failed_req:
  836. failed_of_parse:
  837. kfree(info->pseudo_palette);
  838. failed_init:
  839. framebuffer_release(info);
  840. return ret;
  841. }
  842. static int imxfb_remove(struct platform_device *pdev)
  843. {
  844. struct imx_fb_platform_data *pdata;
  845. struct fb_info *info = platform_get_drvdata(pdev);
  846. struct imxfb_info *fbi = info->par;
  847. struct resource *res;
  848. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  849. imxfb_disable_controller(fbi);
  850. unregister_framebuffer(info);
  851. pdata = dev_get_platdata(&pdev->dev);
  852. if (pdata && pdata->exit)
  853. pdata->exit(fbi->pdev);
  854. fb_dealloc_cmap(&info->cmap);
  855. kfree(info->pseudo_palette);
  856. framebuffer_release(info);
  857. dma_free_wc(&pdev->dev, fbi->map_size, info->screen_base,
  858. fbi->map_dma);
  859. iounmap(fbi->regs);
  860. release_mem_region(res->start, resource_size(res));
  861. return 0;
  862. }
  863. static int __maybe_unused imxfb_suspend(struct device *dev)
  864. {
  865. struct fb_info *info = dev_get_drvdata(dev);
  866. struct imxfb_info *fbi = info->par;
  867. imxfb_disable_controller(fbi);
  868. return 0;
  869. }
  870. static int __maybe_unused imxfb_resume(struct device *dev)
  871. {
  872. struct fb_info *info = dev_get_drvdata(dev);
  873. struct imxfb_info *fbi = info->par;
  874. imxfb_enable_controller(fbi);
  875. return 0;
  876. }
  877. static SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume);
  878. static struct platform_driver imxfb_driver = {
  879. .driver = {
  880. .name = DRIVER_NAME,
  881. .of_match_table = imxfb_of_dev_id,
  882. .pm = &imxfb_pm_ops,
  883. },
  884. .probe = imxfb_probe,
  885. .remove = imxfb_remove,
  886. .id_table = imxfb_devtype,
  887. };
  888. module_platform_driver(imxfb_driver);
  889. MODULE_DESCRIPTION("Freescale i.MX framebuffer driver");
  890. MODULE_AUTHOR("Sascha Hauer, Pengutronix");
  891. MODULE_LICENSE("GPL");